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• Any FPGA design can be converted into an ASIC design with minimal or zero modifications, and usually with a substaintial performance improvement. There are several companies out there that will take your synthesized netlist and give you an ASIC, and will do it cheaply. The FPGA vs ASIC break even point is in the ball part of 100,000 units and it's getting better every day.

• While it may take a Virtex-II to compete with a decent accelerator for all applications, it may be possible to have multiple optimized implementation that are specific to specific applications. For instance, you could program the FPGA with an image optimized for 2D applications for general purpose use and then reprogram it with an image optimized for 3D applications as soon as you run your favorite FPS. Also, A decent sized Virtex-II can be purchased for US $323 in single quantities, and roughly half that in quantities of 1,000 or more.

• Design tools from Xilinx are less than US $1,000. And if you use their web-based tools, they are free.

• The circuit board would not be a major problem. I recently designed a PCI board with an FPGA and SDRAM on it (and wrote the FPGA code) and we got our 10 board for less than US $2,000. Most of this is set up cost, of course, so it gets really cheap really quickly as the numbers go up.

• 266 Mhz DDR RAM really only runs at 133 Mhz, and high end FPGAs can run at 300 Mhz. FPGA vendors often have hardware build into the FPGA to suppport high speed interfaces like that, or provide HDL source so that you can implement your own.

• Even if it takes 5A to run these chips (slightly excessive IMHO), the requirement is at the core voltage (1.5V for the Virtex-II mentioned earlier). With a 85% efficient switching regulator (typical), that would equal 2.7A @ 3.3V or 1.8A @ 5V or 750mA @ 12V (all of which are available on the AGP connector). Besides 5A @ 1.5V is just 8W after you include the switching inefficies, and you probably have at least a 300W power supply, so it's less than 3% of your total power budget.

• We do need to factor in assembly costs, which for a prototype run of 10 boards is going to to be about $3000 total, but the costs get really cheap if the quantity goes up, especially if the through-hole components are soldered by the enthusiasts who buy these cards.

  So, you don't really need all that much capital, and the open-source development model will provide the large teams of engineers.

  Unfortunately I can't contribute to this project because I code not in VHDL but in Verilog (which gets a lot more done for the same amount of effort in my opinion and others here and here).

• Any FPGA design can be converted into an ASIC design with minimal or zero modifications, and usually with a substaintial performance improvement. There are several companies out there that will take your synthesized netlist and give you an ASIC, and will do it cheaply. The FPGA vs ASIC break even point is in the ball part of 100,000 units and it's getting better every day.

• While it may take a Virtex-II to compete with a decent accelerator for all applications, it may be possible to have multiple optimized implementation that are specific to specific applications. For instance, you could program the FPGA with an image optimized for 2D applications for general purpose use and then reprogram it with an image optimized for 3D applications as soon as you run your favorite FPS. Also, A decent sized Virtex-II can be purchased for US $323 in single quantities, and roughly half that in quantities of 1,000 or more.

• Design tools from Xilinx are less than US $1,000. And if you use their web-based tools, they are free.

• The circuit board would not be a major problem. I recently designed a PCI board with an FPGA and SDRAM on it (and wrote the FPGA code) and we got our 10 board for less than US $2,000. Most of this is set up cost, of course, so it gets really cheap really quickly as the numbers go up.

• 266 Mhz DDR RAM really only runs at 133 Mhz, and high end FPGAs can run at 300 Mhz. FPGA vendors often have hardware build into the FPGA to suppport high speed interfaces like that, or provide HDL source so that you can implement your own.

• Even if it takes 5A to run these chips (slightly excessive IMHO), the requirement is at the core voltage (1.5V for the Virtex-II mentioned earlier). With a 85% efficient switching regulator (typical), that would equal 2.7A @ 3.3V or 1.8A @ 5V or 750mA @ 12V (all of which are available on the AGP connector). Besides 5A @ 1.5V is just 8W after you include the switching inefficies, and you probably have at least a 300W power supply, so it's less than 3% of your total power budget.

• We do need to factor in assembly costs, which for a prototype run of 10 boards is going to to be about $3000 total, but the costs get really cheap if the quantity goes up, especially if the through-hole components are soldered by the enthusiasts who buy these cards.

  So, you don't really need all that much capital, and the open-source development model will provide the large teams of engineers.

  Unfortunately I can't contribute to this project because I code not in VHDL but in Verilog (which gets a lot more done for the same amount of effort in my opinion and others here and here).

There are 6 pins on the back of the unit These are longer, single-sided pads, probably for use with some sort of card edge connector, not to be soldered to the xbox. Six pins matches the standard Xilinx programming cable: VCC/GND/TDO/TDI/TCK/TMS for JTAG, or VCC/GND/DP/DIN/CLK/PROG for their non-JTAG FPGAs.

It seems like making nano FPGAs would be the easy way to go, but never having made one myself I wouldn't really know, would I? I have done a bit of research on the subject though and apparently there is skepticism of the current king of FPGA, Xilinx, has been criticized for using an inefficient and non-standard design in their FPGAs that would supposedly work better in a much simpler layout. Obviously simplicity of design could be helpful when dealing with nanoscale materials.
On a totally separate note, I thought the DNA experiment about the party guests was a bit suspicious. I've written GRE study guides in the past and so I've spent quite a bit of time analyzing those kinds of analytical questions. From a test writer's perspective, their experiment raises some interesting issues. The GRE frequently uses seven or more entities with special requirements in the analytical section and most of the questions can be solved with a piece of paper and pencil in a few minutes using simple logic. If that wasn't the case, then how would the test writer be sure what the correct answer is if they couldn't verify it?
So, if they've got all these special case situations with perhaps dozens of variables for each party goer then how do they know what the right answer is and that there are not more than one right answer --the bane of test writers. And if they do know how to accurately calculate this data, then is it really as complicated as they make it seem?

I attended an IEEE meeting at my school recently, and a guy from Xilinx presented and demoed FPGAs (their brand of course) and told us why we should use FPGAs for our signal processing needs. Of course, being an SE student, there were quite a few thngs that were over my head, but of course talking about the massive paralellism clicked with me, and of course hearing that one client of theirs had OC-768 signal processing within one FPGA chip, well, that was pretty damn cool. Also, being able to design your circuits with a nice GUI interface, rather than in VHDL or Verilog or whatever, looked pretty damn cool.

Most of those are 2G or 2.5G. This page lists various 2.5G and 3G standards.

You can use Xilinx Webpack tools, available free from Xilinx. Supports both VHDL and Verilog. (I wish they had a native Linux version.)

With the XC2S200, you can fit a 32-bit RISC CPU, a bunch of peripherals, and a little memory all into the FPGA.

Try asking on comp.arch.fpga.

But just from a quick search on Xilinx's store, a JTAG connector and Prototype board runs about $550. The chips themselves can be pretty cheap (between $5 and $50), and they have stripped down toolkits available online.

Try asking on comp.arch.fpga.

But just from a quick search on Xilinx's store, a JTAG connector and Prototype board runs about $550. The chips themselves can be pretty cheap (between $5 and $50), and they have stripped down toolkits available online.

Xilinx (FPGA semiconductor ompany) has a tool in early beta which let's you write Java, in a normal software way, which is then translated to Verilog. It looks pretty cool, and is free to use at this point (beta). Check out: this link.

They seem to have gotten some fairly decent speed/area results.

Lat I checked, Verilog wasn't even a company. I bet you're thinking of Xilinx or Altera. Note that Xilinx gets badass points for providing free development tools that aren't half bad, even if they are for Windoze.

As far as speed is concerned, there are two big factors that determine how fast you can run a hardware implementation of a design. First, there's the maximum clock speed of the FPGA. This is a parameter of the FPGA used, and, like CPUs, varies with the manufacturer and model. While it is possible to circumvent this with totally asynchronous designs, as you're not required to use the chip-wide clock, it's only practical in only a few unique applications (ARM AMULET). Second, the size of the design will affect the speed at which it will run. A simulation of an Athlon or a Pentium III (excluding large memories, like caches and ROMs) will be forced to run slowly because the propagation delay between far away cells in the FPGAs and, in extreme cases, between individual FPGAs themselves, will be too great to support high clock speeds. Plus, the gate propagation will be slower in an FPGA than on raw silicon. This factor is also somewhat dependent on the HDL CAD tool used and how smart its automatic floor planner is. Now put something simple like an ARM in an FPGA, and you can probably hit much higher speeds.

BTW, if anyone is really interested in FPGA's, Xilinx has a hellass pile of info here.

Finally, I wanted to ask any current FPGA users if they find that they get different performance stats on the same design on different compiles. When I was doing work on Xilinx, I found that the compiler would produce designs of various speed, based on routing and the number of CLB's it used. On a couple of occasions, my longest path delay was decreased by about 25% just because i recompiled a couple of times.

BTW, if anyone is really interested in FPGA's, Xilinx has a hellass pile of info here.

Finally, I wanted to ask any current FPGA users if they find that they get different performance stats on the same design on different compiles. When I was doing work on Xilinx, I found that the compiler would produce designs of various speed, based on routing and the number of CLB's it used. On a couple of occasions, my longest path delay was decreased by about 25% just because i recompiled a couple of times.

I used to work for a company that manufactures a very similar device as an add on card for PCs. True enough, a single transistor on the FPGA in each of these devices is capable of firing much faster than the clock speed of available processors. However, this is the switching speed of a single transistor on the device. When transistors are chained together, you get a phenomenon called gate delay, which is the amount of time each transistor takes to react to its inputs before the output level is changed. So if a single transistor is 1000 times faster than the clock speed of a PII, and we chain 1000 of these transistors together, our usable clock speed is now the same as the PII. Another item of worry for the designers of the image to go on the FPGA is clock tree generation. The clock signal for the FPGA must be generated in such a way that all areas of the chip are synchronized. Very often, the clock tree is the biggest problem in the design as it skews as each route gets longer.

These devices are fantastic if you have a very specific application that you wish to design them for (e.g. Image processing, voice analysis, SETI@Home). With the ability to be reconfigured at a moments notice, they are also much more reusable than an ASIC. But don't be misled by the speeds given in the marketing info. Get a demo chip from Altera or Xilinx and play with it for a while. Then make your own judgements about speed.

It's actually a NAND gate. Every combination of NOT, AND, OR, XOR, and so on can be represented by combinations of NAND gates. Any [logic] circuit could be built with significant numbers of them. That seems to be what Altera and Xilinx do for a living. I know that Xilinx has some pretty great educational prices, and you can pick up a PCI board with FPGA onboard for around $270 if memory serves.

Xilinx offer free design tools for their family of chips. Look at Free Virtex Tools A company I am involved with is working a standard CPU (PowerPC) FPGA assisted Application specific computing platform.

See Internet Reconfigurable Logic from Xilinx. These chips are now in the multi million gate range.

When FPGAs get cheap enough, this is exactly what will happen. See e.g. Xilinx who have an impressive product line up to several million gates. Unfortunately, the big ones cost hundreds of dollars right now.

Robotics is a way to get people doing electronics in a fun way. Many simple robot designs don't even need a CPU, just carefull tuning. Take a look at BEAM robotics (Solarbotics has some BEAM type kits). They are simple brainless robots that move around based on simple hardware programming. Learning what it takes to make these tick would help tremendously at teaching electronics. BEAM style robots rely on feadback loop electronics to operate. LEGO Mindstorms is another way into robotics. After one has mastered what the LEGO parts can do, one can start building your own electronics hardware interfaces.

** We're using Xilinx's WebPack CPLD programing tools. Other companies also have tools available for free or cheep.

The whole field of Configurable Computing has been trying out architectures like this for some time (don't know why /. hasn't covered this technology more).

I'll tell you why /. hasn't covered the technology more: because FPGAs on their own are mainly just an amorphous sea of gates. You need a lot more than that before you have a viable (and therefore interesting) computing engine. StarBridge came up with such a working system and so it was no surprise to see it featured on Slashdot.

In contrast, Xilinx's strides in FPGA and RC technology tend not to feature because there's a gulf between a beautiful RC chip like the 6200 and actually being able to compute with it. Even Xilinx know that now -- their newer devices are more advanced FPGAs but they don't even attempt to carry the generic RC mantle like the 6200 tried to do, unsuccessfully. It came close, but you need a lot more than just an FPGA to make a useful RC: you needs a preconfigured computing architecture to start with, otherwise the programmer needs to think in terms of gates, and that's one paradigm shift too far. The 6200 suffered from not being specific enough. That's a peculiar observation to make in the FPGA field, but it reflects reality in the computing field, and even RCs need to take that into account.

And that's what PACT seem to have done with their XPP. Sure, its reconfigurable parts are based on FPGA technology (the only sensible way of doing it), but they've created a whole new dataflow computing engine with that RC resource, and it's the latter that's interesting for computing people, not the FPGA itself nor the internal RC mechanism.

I'm working on a project with a FPGA chip. It takes my 800 MHz machine about 1.5 minutes to compile the chip's design, using the Xilin x Foundation Software, for a relatively small design without much synthesis! Even a tiny change to just one gate and I've got to wait 1.5 minutes. It was about 5 minutes before I upgraded the CPU to 800 MHz. My chip is a 10k gate (supposed capacity). It's hard to imagine how anybody can compile designs for the really large devices. I suppose they use more high-level simulation and don't do as much in-circuit download. Whatever they do, I'd image that companies paying top dollar for engineers to sit in front of slow software will be among the first in line for faster cpus!

There are lots of other high-end applications like this. The low-cost PC is the bulk of the market, without a doubt, but it doesn't take a lot of imagination to see high-end applications that really need more CPU horsepower. If I'm still doing a lot of FPGA work when the chips are actually available (at $1000 to $1500), I might even upgrade my own home machine!

I'm working on a project with a FPGA chip. It takes my 800 MHz machine about 1.5 minutes to compile the chip's design, using the Xilin x Foundation Software, for a relatively small design without much synthesis! Even a tiny change to just one gate and I've got to wait 1.5 minutes. It was about 5 minutes before I upgraded the CPU to 800 MHz. My chip is a 10k gate (supposed capacity). It's hard to imagine how anybody can compile designs for the really large devices. I suppose they use more high-level simulation and don't do as much in-circuit download. Whatever they do, I'd image that companies paying top dollar for engineers to sit in front of slow software will be among the first in line for faster cpus!

There are lots of other high-end applications like this. The low-cost PC is the bulk of the market, without a doubt, but it doesn't take a lot of imagination to see high-end applications that really need more CPU horsepower. If I'm still doing a lot of FPGA work when the chips are actually available (at $1000 to $1500), I might even upgrade my own home machine!

About how windoze sucks... last night I installed a removable drive bay, and put the IDE drive into my machine. My computer has no other IDE devices, the disk and cdrom are both SCSI. Windows pops up a blue screen saying that it's going to have to switch to "compatibility mode", only because I just installed an IDE disk drive! Compatibility mode means everything is running 16 bit drivers, as I understand it. Well, the next couple boots both crashed, for no apparant reason. I finally did get it to boot, opened a DOS window and ran FDISK and FORMAT on the new drive. Somewhere near the end of FORMAT, the machine completely crashed, with some sort of message about the system being "halted" for some reason. I did finally get the drive formated by creating a "startup disk", booting the computer with that. Under this config, the drive letters were reversed from their appearance in windows... another thing that isn't a problem in linux. Fortunately I noticed the drive sizes before formatting "D:" and losing my existing windows installation.

Even after I removed the IDE drive and attached it to my hardware, Windows is really messed up. It's still in compability mode, and how to fix that is a good questions.... at least not without using linux.

In the last year or so, I've been using Linux to make backups of my windows partition. I have another machine that runs linux 24/7 and exports some shares with samba. I always save my work to "F:", so "C:" only has the system, software, and other non-data files. Many windows programs always default to saving stuff on "C:", often in their own installation directories, which seems like a bad idea to me, but it's only a minor annoyance compared to windows crashing.

Anyways, to back up my windows partition, I type something along the lines of:

cat /dev/sda3 | bzip2 -9 - > /tmp/sda3_windoze_backup.bz2

and then later on, when windows gets itself all messed up in a state which is more or less not recoverable, I just "cat" that image file back onto the /dev/sda3, and just like magic windows is back in a previously working state, completely reinstalled, and with only one reboot.

Actually, before I do the backup, I type "cat /dev/zero > /dos/dummy.bin" to fill the unused space with zeros, and then delete the file, so that the backup image will compress well.

I'm glad that you don't have any problems with Windows, and I wish my experience was the same. Right now, my windows partition is really messed up, and I need to find the CDR that I burned that big .bz2 backup file onto.

At the risk of getting moderated down for blantent self promotion, here's a link to my little MP3 player project, which is the reason I needed to temporarily add an IDE drive to my machine, and why Windows went south.

Unfortunately, who the heck has the resources to punch out one of these things besides the major chip manufacturers anyway?

For a MicroSPARC? I would guess that you need full custom logic, which isn't that expensave if you are buying tens of thousands of the device. It's suck if you want, say, three.

For the OpenCore CPU? That one is being targeted at FPGAs, which cost a small number of thousands (like two-ish) allready soddered on a PCI bord and ready for love (this would be for the million-gate-ish FPGAs). The "smaller" FPGAs, like 10k to 200k gates are available for way cheep, like under $10 for some of them (with 100k gates even!), very few over $100.

Remember that the first SPARC implmentation was a 20K gate array, it ran at about 10MIPS if the wind was going it's way (Sun 4/110). So you can probbably design a low speed CPU on a $5 FPGA and have room for a USB interface. Spend $40 and you have room for some periphrials too.

Unfortunitly the hard part is the dev tools. Many cost over $100k. I don't know of any Open Source FPGA design tools. Wish I did. I would love to design a non VHDL language!

For FPGA examples and prices look at xilinx. Not sure where to go to look for software pricing.

Xilinx makes a field programmable gate array which allows you to wire the thing on the fly. That is, they'll sell you a chip which contains anywhere from 100,000 gates to 1,000,000 gates which can be dynamically wired to provide all sorts of functionality, from microprocessor cores to UARTs to RAM cells. You don't need millions in fab equipment. Just one of these chips and an EEPROM programmer and some freeware software (links here) will do the trick.

It's not the same as editing masks using a VLSI design tool, but it does the trick.

Further, most people who design chips don't have or need millions in fab equipment. When I was at Caltech about a dozen years ago, I took a class on VLSI design where we simulated the results, and for the final, sent our design to a fab house which specializes in one-off fabrication for testing. One-off fabrication costs a few hundred to a few thousand per chip, but gives you a way to test your designs in hardware once your prototype checks on the simulator software.

Beyond that, you don't really even need to do this if you simply want to translate your FPGA design into an ASIC core for mass production. There are several fab houses who will take your FPGA data and turn it into an ASIC core for you by automatically laying out the chip-level logic from the FPGA data.

So no, you don't need "tens of millions of dollars worth of fab equipment." Far from it; just a couple of FPGA samples from Xilinx, and some software, and some descrete components for building prototype circuitry that uses your FPGA circuit from a company such as Electronix Express will do the trick.

And hell, just poke around the Free IP site; they've got two processor cores available for download, including one of which simulates the 6502 very well on several FPGA vendor's products.

It's being done by Sun with the picoJava and SPARC cores.

eg3.com has a list of Open Source hardware links.

Tom Coonan has donated a free 8-bit microprocessor core to the Open Source IP community. One interesting aspect of this is that you can "build it yourself" using an FGPA booted from an EEPROM you can burn yourself.

And speaking of FGPAs, Xilinx has a whole page of IP for downloading and burning into their FGPAs here. What makes this super-spiffy is that you can write logic for these things and program them yourself--they download the gate configuration logic from an external ROM (or EPROM) or other source. In fact, many people are using these things by downloading the gate configuration from other sources, such as a data file.

The Open Source Hardware community apparently is thinking along the lines of using FGPAs to experiement with creating a various open source microprocessor cores in order to get the bugs out. Once the bugs are out, you can then create an ASIC core from the same data files and burn chips for production. What makes this strategy interesting is that probably for around $500 (or less) in hardware, you can build your own test bed. In fact, I could see building an FGPA "loader" which is basically a 6502 and a UART chip connected to your serial port which contains all the logic necessary to boot and download logic into an FGPA from your desktop as a sort of "in-circuit" emulator.

But my hardware days are behind me, at least for now...

It's being done by Sun with the picoJava and SPARC cores.

eg3.com has a list of Open Source hardware links.

Tom Coonan has donated a free 8-bit microprocessor core to the Open Source IP community. One interesting aspect of this is that you can "build it yourself" using an FGPA booted from an EEPROM you can burn yourself.

And speaking of FGPAs, Xilinx has a whole page of IP for downloading and burning into their FGPAs here. What makes this super-spiffy is that you can write logic for these things and program them yourself--they download the gate configuration logic from an external ROM (or EPROM) or other source. In fact, many people are using these things by downloading the gate configuration from other sources, such as a data file.

The Open Source Hardware community apparently is thinking along the lines of using FGPAs to experiement with creating a various open source microprocessor cores in order to get the bugs out. Once the bugs are out, you can then create an ASIC core from the same data files and burn chips for production. What makes this strategy interesting is that probably for around $500 (or less) in hardware, you can build your own test bed. In fact, I could see building an FGPA "loader" which is basically a 6502 and a UART chip connected to your serial port which contains all the logic necessary to boot and download logic into an FGPA from your desktop as a sort of "in-circuit" emulator.

But my hardware days are behind me, at least for now...

Patents claims aside, these hardware ideas are not new. What's going to make or break any of these ventures is at the software level-- how they efficiently transmute one set of instructions into hardware (either microcode or gate-array logic). From our experience with all the different flavors of Java virtual machines and their relative performance and compatability, we should recognize how difficult it will be to come up with a "MetaOS" that drives configurable hardware.

The speed of tailored gate array logic at specific tasks is phenomenal. The reconfigurability of "field-programable" gate arrays, like those produced by Xilinx have already proved useful in creating lightening fast photoshop plugin filters.

We should cheer if Transmeta or Starbridge come up with novel hardware and software that increases the generality and usefulness of these ideas. Be skeptical of the hype, but not the vision.

Previous Slashdot reference to starbridge is here.

Look carefully (and subjectively, how rarely that happens) at the performance specifications. The IBM Pacific Blue did 1.2 TeraOps sustained peak running the actual ASCI codes (albeit in their own labs, SGI beat those numbers and did it on site). The SBS HAL-4rW1 did 12.8 TeraOPs doing a sequence of 4 bit additions, or 3.8 TeraOPs on a 16 bit adder.

This means that the memory and I/O subsystems aren't even exercised. Nobody uses a 4 bit addition as a performance spec, not even Intel.

The actual product description is unbelievable as well. The largest Xilinx FPGA's might be capable of being configured to fully emulate a 16 bit microprocessor. I haven't worked with them in a long time but when I worked with the 4000 series I figured I could shoehorn a rudimentary 8 bit processor into the largest devices. (which would mean that a rudimentary 8 bit microprocessor was produced for over one thousand dollars incidently. It's a bit cheaper to buy a PIC from MicroChip)

They said that they reached these performace levels with 280 of the largest Xilinx FPGA's. My take on what they've done is cram as many 4 bit adders onto a single FPGA and replicate it 280 times. They then had them all execute in parallel and pretended that this made up a supercomputer.

Keep in mind that performance on an FPGA isn't stunning. We're talking on the order of 10 nanoseconds to do the 4 bit addition.

So... if they've even designed and built this thing (which I doubt) the specifications are a complete fabrication.

I haven't checked yet, but browse through Xilinx's web site. If they don't mention this wonder of reconfigurable computing then it doesn't exist.