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Silicon Will Get CPUs To .07 Micron
ruiner writes: "This post at EE Times discusses that it now appears that silicon dioxide can be used as an insulator down to a process of .07 micron for processors. This will buy processor manufacturers a few more years to develop solutions for smaller processes. "
Too bad all these processes only allow companies w/billions of dollars in the bank to play.
Perhaps it would then be better to begin pushing for more efficient programming usage of multi-processors on a single system? From what I know which isn't a lot, we could make more use of parallel processing than most systems currently allow for, or am I completely wrong?
> The next step is 10Ghz, not 1.1Ghz
:: 150 MHz : 100 MHz. (I think I got that notation right).
What an excellent idea! Why didn't *my* company think of it first! Forget that that piddly 1 GHz crap, why don't we just jump straight to 10? I'll get right on it...
Are you really trying to tell me that you were content with your 100 MHz Pentium Classic right up until a month or so ago when that 1 GHz chips came out? All of those small jumps in the middle there didn't mean a thing, I suppose.
While it's true that the steps that companies increment their clock in should be increasing (they should now be releasing in 50-100 MHz steps, not 33 MHz steps), the percentages should scale. 1.5 GHz : 1 GHz
Now, I *do* think that the race to 1 GHz was kind of silly, but hey! It was marketing. Faster is better, but clock isn't everything. Intel hasn't released a new core since 1996, and you can really feel it. Coppermine and others are slight improvements, but they really need to get their new architecture (IA-64) out the door. Athlon is still eating their lunch.
just a disgruntled computer architect,
--Lenny
Faster chips are great but x86 is getting tired and the I/O on a PC is really limiting the usefullness of the chips we're capable of making now. We need a platform capable of useing what we have now.
When someone yells "Stop" or goes limp, or taps out, the fight is over.
Electrical signals travel at the speed of light. Therefore, the smaller you can make a circuit, the faster a signal will get from one end of it to the other. And of course you can pack more of them into a given area, leading to smaller die size, which equates to more units per wafer, higher yields, and lower prices.
At this point we're getting to the limits of what can be done on a silicon substrate. The problem here is that with circuits smaller than 0.07 micron, you are in danger of splitting silicon atoms if you pump any energy at all through the circuit. Yes, you read that right -- splitting silicon atoms, resulting (theoretically) in a release of energy equivalent to the Hiroshima bomb. This, as you may have guessed by now, is the real reason the US government considers high-powered CPUs to be "munitions". Just imagine what could happen if a bunch of Islamic terrorists got hold of a few thousand such CPUs and set themselves up as a mail-order PC company.
This is not, by the way, a problem unique to ICs. The real reason for the classification of data compression products as "munitions" is related to this too. You see, if data is compressed too much, the atoms comprising the individual bits can actually begin to participate in atomic fusion, leading (for a 32 kb block of data) to a release of energy equivalent to the original H-bombs of the 1950s. There are some papers here to document all this.
Just goes to show... the government doesn't always tell you the real reasons for the decisions they make, but that doesn't mean those reasons aren't justified.
Goody. If the rate of CPU growth slows, it'll force people to realized speed gains by actually writing more efficient code. Eat that, Wintel!
Can your IM do this?
This is stretching the limits of physics. A 70 nm layer is only about 200-300 Si=O bonds thick. We're almost in the area where quantum effects become an overriding concern. I can't be bothered to work out the probability of an electron with a given voltage tunnelling through a layer this thin, but I suspect that we are in the area where voltage regulation and temperature control become *very* important. Put another way, these babies won't be candidates for aggressive overclocking.
What this really means is that we *may* have a little longer to go before we have to start using 'exotic' oxides. This is good news. One of the great things about SiO2 is that the manufacturing properties are well understood (although, at this size, lithography is going to be, er, interesting.
And they say there's a chance that they can take it even further. Gordon Moore will be pleased. His law looks good for the forseeable future.
That sounds great from a science point of view, but just not realistic from a business point of view. Let's say that a big chip company puts no money in .07 micron technology and dumps every last R&D dollar into truly next generation CPUs. What if the R&D doesn't produce a working chip until 2007? Do you think a spokesperson for AMD could take a podium in 2004 and say, "In response to Intel's announcement of 6.4 GHz CPUs, we would like to ask everyone to hold off for three years when we will deliver our 150 GHz chips...maybe." They might as well fire everyone and lock the doors. The trick for those companies is to split the funding between evolutionary and revolutionary R&D so that they can keep products coming down the pipeline right up until that huge leap can be made. I certainly don't envy the people drawing up that budget. If you want to give it a shot, try to predict the weather for June first, of next year, and "hot" won't cut it.
-B
I figure that once companies realize the limit, they'll collude and only release faster processors in small increments in "competition" with each other to leech as much money as they can. The alternative is that the first one to reach the limit sells to everyone to get the money before the other guy (Intel vs AMD), but then everyone is out of business because the market is satisfied until freaky quantum or holographic or whatever technology is developed.
How close is anyone to that stuff?
Instant Crisis
Sounds like a .05m channel length to me. 1.5 nm Oxide thickness is mindblowing, considering I'm working with 70 nm right now. It's great to see silicon die decreasing in size. Too bad it doesn't relate to CPUs at all, at least not at such an early stage in the research. To get reproducible results on a large scale, entire processes will have to be reworked, this will take at least five years to even become anywhere near viable for a CPU. Oxide will get ICs to .07m, but it will take a while for the CPU usability of this process to reach maturity. We've had .25 micron for over ten years. It's only been in use for the past three.
Lithography is going to take a while for this stuff to catch up, too. The traditional Novolac/Diazonapthoquinone(DNQ) resist won't stand up at such a small feature size. It should be interesting to see if PolyHydroxyStyrene(PHS) can even hold up well at such a small feature size. 157nm Lithography is a ways off for industry. 193nm is nearly standard now, and it's an _extremely_ easy process to wreck.
Advances like this first get used on 'real' computers - serious SMP servers like IBM's SP series of RS6000s, Suns high-end servers (Starfire), Compaq's WildFire Alpha boxes (drool) and, soon, servers based on AMD Sledgehammer and Intel Merced (Itanium) / Willamette chips.
Machines like this are used for *serious* numbercrunching. They predict the weather, model the economy, help design planes and spacecraft and find oil. These are tasks for which there is still a serious demand for MIPS.
Because of the astounding cost of developing these technologies, it takes years for them to trickle through to the desktop.
I admit that when decent processors get to the desktop, they are wasted. I did some low-level monitoring of my mother's PIII 450 recently. She runs Win98 and MS Word. The processor spends 99.2% of it's time idle, and 60% of it's active time it's waiting for cache misses. The cache miss problem isn't going away any time soon, because memory is still not getting faster at a high enough rate. The only realistic cure is for compiler writers to continue developing *very* clever optimisers. This is happening, but optimisations like this are deep magic.
I/O in modern servers using proprietary technology is awesome. Check out the IBM SP servers for more info. (Can't find the link - I have it on CD). Unfortunately, PCs are hampered by 'legacy' technologies like PCI. There is at least one serious attempt to address this - the Next Generation I/O project
No, this is transistor size. The oxide thickness they are talking about is 15 angstroms, which is far smaller than 0.07 microns. Current oxide thicknesses for modern processes are on the order of 100 angstroms or less (which is 0.01 microns or 10 nm).
They've been saying we'll reach the end of the useful life of silicon for quite a while now. And each time they get close, they figure out how to bum it down by a few microns. I betcha when they get close to .07, they'll figure out how to bum it down again...
I'm trying to teach myself to set people on fire with my mind... Is it hot in here?
Looks like smooth sailing to me!
Lacking <sarcasm> tags,
Secondly, companies aren't going to flog off any more computers, just because the processor is smaller. It would make much more sense, IMHO, to use the scale improvements to build multi-processor CPUs. (If the next generation of Intels or AMDs packed 16 ix64's into a single unit the size of current processors, with all necessary SMP stuff thrown in, you'd have a truly powerful computer.)
Last, but not least, why use all these improvements on the processor? It's not been the bottleneck for years! If you designed a wafer-scale RAM chip at 0.07 microns, you'd be looking at computer memories in the region of 512+ TERAbytes! Can you imagine how responsive KDE would be with that?
It's a small world and it smells funny; I'd buy another if it wasn't for the money; Take back what I paid (SoM)
The dirt counter doesn't actually "see" the dirt. It uses a property known as oblique Reynolds scattering to detect the glint that dirt reflects back at a photodiode. Photolithography is the only practical technique to mass produce ICs. If they were to use a laser to trace each path, it would literally take years for a single chip to be made (think of how many miles of circuit paths there are in even a small IC).
Solid state photonics is coming, and there's nothing you can do about it.
Solid state photonics will still have its feature size limited by the wavelength of the light used within its devices. _Current_ integrated circuit chips use feature sizes that are much smaller - by the time photonics matures, it will already be left in the dust as far as density is concerned.
Use smaller wavelengths of light? Not unless you want to destroy your material by photoionization.
Your next logical argument is to point out that most proposed photonic devices are three-dimensional. My logical counterargument is to point out that you can build three-dimensional electrical devices too. It's just currently cheaper to shrink 2D fabrication processes.
Your next probable point is to make noise about propagation delay in electrical circuits. It turns out that these aren't the limiting issue in conventional ICs - heat dissipation is.
Your next likely point is to say that a photonic circuit would have less heat dissipation. My response is that I'll believe it when I see it. Absorption happens, and whatever diode lasers are pumping this device won't be perfectly efficient either.
Lastly, I'd like to point out that most of the effort that goes into designing integrated circuits goes into designing the logic, not the fabrication processes. Computer engineers would still be employed in your hypothetical universe. Electrical engineers design motherboards and specialized analog ICs, both of which would still exist, so they wouldn't be out of work either.
Summary: Photonics is not the magic wand you hold it out to be.
wire of the same length as in a previous chip would be slower in the new chip because of the reduced driver sizes, thinner wires (increased resistance), and the relatively unchanging capacitance. (The capacitance per unit length stays about the same at smaller sizes because of fringing effects.)
Capacitance is still (AFAIK) dominated by the diffusion capacitance of transistor sources/drains connected to the wire. Second contributor, IIRC, was gate capacitance. Both of these go down with feature size.
You might point out that gate and drain area will only go down in one dimension, as I'll be sticking more devices on the bus, but they'll still go down.
Wire resistance similarly isn't a huge contributor AFAIK. In all of the sets of parameters that I've seen, even a long bus wire would have resistance lower than the effective resistance of a MOSFET in saturation mode.
Lastly, while your drivers get smaller, the W/L ratio of the gates remains the same. This means that, should you be inclined to melt down your circuit, you could still pass the same amount of current through a smaller MOSFET.
Now, as far as using intelligence is concerned... Most of the cynicism I've seen expressed both towards coding and towards IC design has been put forward by people who aren't doing coding or IC design (in general; I don't know what your personal qualifications are). The fact remains that while boneheaded code gets written and while boneheaded ICs are most likely designed, there are still companies that do it right. These gain market share, grow complacent, and fall to the next group that does it right, continuing the grand cycle.
My point being that you aren't likely to get order-of-magnitude performance improvements by "using intelligence". The people you're competing against already are.
As far as the ultimate limits of communication on smaller, faster chips are concerned, I doubt this will become a serious problem. Designers will simply focus more on pipelining and asynchronus operation of modules to relax system-wide signal timing constraints.
Perhaps it would then be better to begin pushing for more efficient programming usage of multi-processors on a single system? From what I know which isn't a lot, we could make more use of parallel processing than most systems currently allow for, or am I completely wrong?
It turns out that, for several reasons, multiprocessors aren't likely to dominate desktops for a few years yet.
The first reason is that systems with multiple _discrete_ processors are more expensive. You need to pay for multiple processor modules, and the motherboard needs a more complex chipset. Joe Average Gamer is better off spending the same amount of money getting a top-of-the-line video card, and a new single processor six months later. Joe Average Non-Gamer doesn't need a multiprocessor for email and office apps.
The second reason is that writing good parallel code is much more difficult than writing good sequential code. Race conditions, interprocess communication, and so forth add plenty of complexity, and compiler tools won't save you - parallelism is designed in at a higher level than compilers deal with.
The third reason is that interprocessor communications bandwidth and memory coherency overhead are *big* problems for multi-processor systems, and they keep on getting bigger as more processors are added. Something like a Starfire, for instance, isn't a large set of processors and memory with a bus tacked on - it's the Bus Network of the Gods with processors and memory tacked on as an afterthought. It has to be, to handle supercomputer communications loads. This means that a lot of the money you spend on a parallel system *won't* be on processing power. If, on the other hand, you're willing to wait another design generation, you can get a comparable processor for a much lower price.
The fourth reason is that while we could indeed integrate many old cores on a new die, we get better performance by doing other things. Adding more cache, for instance, or adding fast, complicated FP units that would have taken too much silicon to add before. Making a bigger translation lookaside buffer (important with a 64-bit address space). Improving branch prediction (a big source of stalls). Adding deeply pipelined load/store units (another big source of stalls). Or adding whatever other performance-enhancing widgets are invented over the next five years. Multple cores are an interesting idea, but at _present_ aren't the most effective way of increasing performance.
All of these factors mean that parallel processing isn't used except by those who really, *really* need it (dual-processor doesn't count).
Now, the caveat.
Once cache performance saturates - and it eventually will - we'll have a lot of silicon to play with when moving to higher linewidths. At the same time, we'll also have to break chips into asynchronus pieces to solve the clock skew problem. We may also be reaching limits to superscaling (scheduling is an NP-complete problem, and approximations reach diminishing returns eventually). At this point, it starts to make sense to put multiple cores in a chip, along with the coherency logic and communications pathways needed.
However, I don't see your desktop machine running a processor like that for 5-15 years, for the reasons mentioned above.
Ha! Try an k6-2/400 system in a TigerDirect midtower case. Now that thing gets toasty. Add to that an iMac 400mHz DV (That thing is a freaking space heater in itself. I fear it's going to melt through the desk) and a 486 with no case. I have a nice warm room. ;]
In the summer, I leave the iMac and the 486 off and put big fans around my 400mHz Linux box. Works great.
Angry IT woman in big clompy boots. And talking lint!.
Say one proc could be used for all the I/O tasks and the other could be used for whatever else is needed.
The I/O processor would be idle much of the time on a modern system. Most of the I/O load goes through bus mastering devices these days. The CPU queues it up, and gets an interrupt when the transfer completes (in some cases, overhead is reduced by holding the interrupt until several I/O requests complete).
What is needed is a good processor affinity so that the cache stays warmer. The Linux 2.3.x kernel is moving in that direction with internal structures. 2.2.x allready has CPU affinity for user processes.
There are situations where dedicating one CPU to a specific process can be a good idea, but it's not common enough to be in a mainstream kernel.
I used to do some work with GaAs in semiconductor lasers, and I have no idea where you get the idea that GaAs is less effort. For semiconductor lasers, it is less effort, but for device fab, the major problem is the lack of a native oxide. What this means in laymans terms is that you can process silicon, let it oxidize(rust), use a photomask to lay down a pattern, etch away the oxide in the pattern, and start over again. There is no such native oxide for GaAs which means that you have to somehow invent a non-native oxide such as GaAlAs which is a real pain in the ass. As for GaAs being faster, this is also only partially true. I can't remember exactly, but I believe that at low frequencys, GaAs has a higher electron mobility, but this effect drops off at higher frequencies to the point where GaAs and Si are similar in speed. The net result is that GaAs has a limited range of applications for which it is acutally better, and it always costs more. It's true that the cost is decreasing rapidly for GaAs, it is decreasing just as fast or faster for Si.
There were some 3D chips I saw a few years ago, they had vertical interconnects rather than horizontal. The catch was these were DRAM chips, the idea being you could stack several small (cheap) ICs to make one large one. This might be feasible with processors if they had teeny tiny gates and a relatively low clock so they didn't generate too much heat.
I'm a loner Dottie, a Rebel.
A smaller die means less electrical resistance which means *drumroll* less energy dissapation! The smaller the die size the less eletricity it needs so it produces less heat.
I'm a loner Dottie, a Rebel.
I think most people misunderstand what's going on here. The story is about the SiO2 insulator thickness. This oxide sits under the gate of the transistor which is used to control the flow between the source and drain. This is 0.07um OXIDE THICKNESS, which is NOT the same as the gate length. The gate length is the usual parameter quoted when referring to a process (i.e. 0.25um, 0.18um, etc).
.25, .18 m is the feature size. the gate/channel length is lambda which is half of this. Please, for your own sake, understand the topic at hand before posting.
Usually, it helps to understand the topic you're discussing. I grew a 700 angstrom (.07 m) oxide last week on my PFET wafers. If you were correct (which you're not) this article would be over fifteen years late in the coming. Also "wash and deposit" are not terms used in industry. We use "develope, etch and diffusion" since you forgot a step, too. The size which is referred to by
Actually, the scientifically proven limit of silicon technology is much smaller than this. I remember a couple months ago, someone proved that the minimum thickness of the insulator was 4 atoms. Of course, mass-producing on that scale would require lasers with such a short wavelength that the energy delivered by that high-frequency beam would wreak all kinds of havoc on the chip, so a manufacturing process that small is only possible under extremely limited conditions, which will not likely be overcome any time before the next major breakthrough in computing technology.
Personally, I'm more interested in the molecular scale quantum computing technology. I believe it was Los Alamos that put 3 quantum transistors on a single proline molecule. You know, proline, one of them amino acids. We might even be able to grow our computer chips from a DNA or RNA template in the distant future. That is something that could go a lot farther.
WARNING: there is a trojan on your
Bipolar designs are great, but getting the lithium dose right is a royal pain. Ever try to convince a bipolar chip that it needs its meds?
It's a small world and it smells funny; I'd buy another if it wasn't for the money; Take back what I paid (SoM)
I got a couple of old, low clock rate boards for nothing, and I only had MII chips on hand to pair them up to. So I have a pair of MII-300's clocked at 233 and 266. Their uptime has only been dictated by how long I can go without 'tweaking' something..
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Two words: 'Utilities included'..
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