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AMD's x86-64 Moves Forward
MBCook writes "AMD Hammer line is definatly moving forward. The Inquirer has a supposidly leaked memo from MS saying that they have working x86-64 silicon that runs both 32 and 64-bit Win XP. Van's Hardware is reporting that MS is backing x86-64 over Intel's IA-64, and that MS has apparently convinced Intel to move to x86-64! There is an article over at Ace's Hardware from CeBIT that includes some coverage of AMD's Hammer line (including its NUMA). Last but not least is News.com's report that MS is preparing Windows to support NUMA." And it looks like the line will be named Opteron.
To me it sounds like a dinosaur ... look ma, all those wild Opterons running around.
Hmmm ... like a bunch of cows is a "herd" ...
Will a bunch of Opterons be called a "beowulf"?
Oh come on. Linux will support whatever those kooky kernel programmers want it to. Hell, I remember a few months ago some article said that AMD already ported it so they could test it, but I haven't got the link handy.
I find it highly unlikely that _anyone_ could convince Intel (or any company, for that matter) to switch to a competitors architecture. Hammer will remain at AMD and IA-64 will stay on course with Intel. I'd need to hear it directly from both BODs to believe otherwise. Then again... I've been wrong before. :)
that would explain why AMD is backing M$ in the M$ trial that's going on!
It scares me to see huge companies like this, conspiring in court.
Honestly though, I thought it would have been Intel, not AMD doing this.
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I can't wait for one of these to be benchmarked against the current Intel line. But Opteron? Reminds me of Optimus Prime from Transformers. Then again, you may need a transformer just to run one of these :)
Check out, http://zdnet.com.com/2100-1103-847712.html and SuSe already supports it, http://www.suse.com/us/press/press_releases/archiv e02/x86_64.html
-Jason Yates
Anyone here to give a good reason not to...
Intel MMX/SSE are 128-bits already.
But here are a few arguments against it--
1. bus widths at 256-bits are a friggin nightmare to design to run at multi-GHz...
2. To support 256-bits, every path needs to be this wide, which would blot the die so much that you couldn't meet gigahertz timing, not to mention how poor the yeilds would be
most game architectures pump graphics data around at 256,512,even 1k-bit wide busses... not the CPU core. But that kind of precision for the geometry processed in the CPU core is not necessary.
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64-bit in the context of this discussion means address bits. It'll be a long time before console games need 64-bit addressing.
- Anyone here to give a good reason not to have 128 or 256 bit processors?
SureSeriously, way-back-when, my company outfitted the management staff with the 386/SX-16 desktop models, while reserving the more powerful 386/DX-25 machines for the development staff.
The majority of the business world (you know, Email, word processing) doesn't even need a 64-bit processor, much less 256-bit.
It probably depends on your application. Simply having them for the sake of having them isn't enough.
Do you have a good reason to have them, aside from bleeding edge video games?
It will crash either twice as fast or twice as hard, but not both. For crashes that are both twice as fast and twice as hard, you'll need the 128-bit version. ;)
The correlation between ignorance of statistics and using "correlation is not causation" as an argument is close to 1.
In the case of PC processors, thing are a little more sane, in that we're generally talking an x-bit processor to mean it has x-bit general purpose registers and an x-bit address space. Sometimes these processors use more bits in other places, like wider registers for SIMD operations, or wider data busses. No doubt if the Pentium was used in a game console, it would be described as 64- or 128-bit (hmm...just like the Xbox), to keep up with the marketing spin from the other consoles.
Microsoft is holding back the industry
And I'm sure it has nothing to do with the fact that every man, woman, child and manager on the earth doesn't want to re-purchase every piece of software and hardware they own.
And a 64 in the processor. IIRC, the processor is based on the Alpha core. And when the alpha came out, it was faster than anything 32 bit. But comparing the X-box and the Nintendo 64, which were released many years apart won't buy you much of a conclusion other than current processors are generally faster than older processors.
All other things being equal, a processors with larger word size (instruction sizes and address sizes) will be faster than those with smaller, though, depending on application, the results can be negligible or even worse, especially if compilers and programs aren't properly optimized.
Of course, I don't really know, I'm just guessing, just like the rest of you ;).
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I wonder why this is listed as a leak.
When AMD announced this at a press conference a few hours ago.
AMD nails Microsoft backing for Hammer-CNET
MS to confirm Hammer support-The Register, UK
Microsoft to Support AMD's Hammer-eWeek
A webcast of today's conference call announcing Opteron is available here
-Mark
I'm gonna hold off on thinking that MS is supporting x86-64 completely. They already have code that works in IA-64. If I had to guess, I would say that MS will release products for both architechtures. The source code for Windows or office is the same for either 64-bit platform, and all it takes is compiling for one or the other. They already have tools that works for IA-64, and I read somewhere they have x86-84 stuff in the works. It won't cost them any money to publish both versions.
They'll probably push one or the other once the market starts leaning in a particular direction. I really hope it's IA-64. I want x86 to die as soon as possible.
This info sounds about 23 days late to me.
Slashdot's queue must be way deep.
Don't sweat the petty things. But do pet the sweaty things.
Hmm. Well. This kinda sums it up:
;-)
1) Cost.
If you have to make everything X times wider (eg registers, buses..) you will use approx X times more chip area -> Higher cost. So to keep a constant cost, you have to wait until the silicon guys come up with some process that can make your chip X times smaller.
2) Power consumption (heat dissipation)
A wider bus will need more current to charge it's capacitive load. If the load gets higher your only options to keep a constant power consumption and keeping your processor from melting are these:
* lower probability for bitchange (smarter coding)
* lower frequency (not desired, right?), or
* lower voltage (1990: 5V, 2002: 3.3V. 2010: 1.5V?)
Perhaps 2) is not a real issue wrt bus sizes, I haven't investigated it. Take it for what it's worth; a semi-educated guess.
I guess that in video game consoles they have either the margins to take the higher cost, or they use 128-bits only in parts of the processor and didn't tell the marketing department.
When a graphics processor is 128-bit, it means you can work on 128 pixels at once, basically doing the same thing to each one in parallel. Or, alternatively, 16 pixels at once, operating on an 8-bit color channel, still doing essentially the same operation to each one at the same time, in parallel.
When a CPU is 64- or 128-bit, that means its computational units can crunch on integers 64 bits in size. Roughly speaking, a 32-bit processor can work on integers between 0 and a few billion (2^32 is around 10^9), and a 64-bit processor can work on integers between 0 and a billion billion (2^64 is around 10^18). Think of a pocket calculator with twice as many digits across the display, and you have the right idea. Same old calculator, bigger numbers.
My perception of "Opteron" was being derived from "optical"
For example, using optical chip technology.
I guess that's entirely forgiveable as Intel's "coppermine" implied using copper interconnects.
Computer Science is no more about computers than astronomy is about telescopes. --E. W. Dijkstra
Much of the stuff mentioned in the article is confirmed and true, but this is a blatant lie to me:
:)
Van's Hardware is reporting that MS is backing x86-64 over Intel's IA-64
Windows XP has been running on IA-64 for ages now, Nvidia's got drivers for it, why would they support x86-64 OVER IA-64? Why not both? It appears they're doing both, and I've seen absolutely nothing to say otherwise.
It wouldn't make any sense for MS not to support both ISAs. It's entirely possible (it's been done already), so why not keep them out there?
I think Van Smith's a little off here.
Looks like AMD is getting their end of the bargain. Whether windows will even run on intels new chips or not, AMD looks like they have a headstart and the backing of M$.
I suppose I should have expected this. AMD was staking it's whole future on their 64 bit solution support for which might have been iffy. With this they practically guarantee their future, maybe even take the lead from intel. We'll have to see how well prepared intel was with plan B (copying AMD if plan A failed).
Now we can re-do those bill gates phonecalls in the last story and fill in the proper information.
Bill Gates: Hello mr Sanders, I need a favour. How would you like M$ to back amd-64 over intel-64?
Sanders: Ok Bill. What can I do for you?
Bill Gates: We would like you to be our witness in this pesky antitrust trial. What do you think you could say in our support?
Liberty.
One thing that worries me about x86-64 is the page tables. They're 4 levels deep, and that still only gives a 48-bit address space. They stick with 4k pages. I guess they had to do it for backward compatibility, but to me this is clearly not the best approach.
Though, IA-64 is pretty questionable too. The VLIW aspect is cool, but the compilers are a nightmare. Nobody knows how to write compilers to take advantage of speculative execution, for one thing.
I'm not familiar with any other 64-bit architectures, but surely they're better than both of these?
Patrick Doyle
I mod down every jackass who puts his moderation policy in his sig. Oh, wait a sec....
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Those 16 Billion GB of data fill up 64-bit. Say you had a 256-bit processor? You could count to a LARGE number. Whoop-de-frickin'-doo. When was the last time you needed to count to that large a number? Or one of your programs did? Probably very rarely.
SIMD uses aside (which have been mentioned elsewhere in responses to this), you don't need that much. In fact, 256 bits would decrease performance. Why? Because when you tried to pull that information in out of memory to the cache, or from disk to the memory, you'd have more time spent waiting for these bits to be transferred around. In fact, this sucks the most because almost all of those bits will be 0 (unless you're dealing with small negative numbers, in which case they'll all mostly be 1).
Numbers that are this big are used so infrequently that you can use bignums (used in lisp, for example) to represent them without taking much of a performance hit at all in the common case, and the exceptional case (VERY rare) will only be maybe twice as slow, which makes the average case faster.
Thus, if you want a slower computer, go design a 256-bit processor, by all means.
-Dan
I can't say what's correct myself, but I think you may be jumping to conclusions.
I've come across a lot of people saying that x86 is outdated, but people aren't willing to move to the next level. Isn't there some way to cut out old instructions slowly? Say make some new instructions to replace certain ones and then promote a standard where the software is labeled "exclusive version X support" and those instructions are used instead. Applications could run both at once but those "exclusive" applications could still run once another processor is released supporting the rest of the updates and dropping the rest of the originals. I'm not all that familiar with CPU workings, but tell me, is it possible upgrade a CISC chip line by replacing the codes in two stages?
Remember "Bring 'em on"? *sigh
Given how well AMD designed and executed the K7 (Athlon) my expectations are to see some seriously good performance for their follow-on chip.
But, past performance is no guarantee of future results. Intel's IA-64 is evidence of that.
Does anyone have any idea how fast the K8 will be in real life?
Everywhere I've looked I haven't seen any performance numbers for the Hammer. How does it compare to say, the Power4?
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The Alpha proved that the MARKET is not ready for a non-backwards compatible chip.
It's not what I want, it's not what you want, it's what the MARKET wants. I know. I used to work at DEC/Compaq and API. The market drives technology, not the other way around.
If you read about the architectures, you'll see that when you compare x86, x86-64, IA-64, and Alpha, that -technically-, the Alpha was the best. However, it's applications that call the shots. x86 might not be as "elegant" solution as IA-64, but it allows easy migration to 64-bit computing without the expense of moving to a totally different architecture. It's a low risk solution. You can convince your boss to update your servers to these new fast AMD systems and run your apps as is, then be a hero when you migrate some big database to use 64-bit addressing and memory management without buying a new server!
I fully expect to see Clawhammer-based motherboards and CPU's at around $300 or so LONG before you'll see IA-64 at that price point. That alone will push x86-64 from the ground up.
(And because of architectures like Alpha, Linux will be ready to roll, fully 64-bit) Not to mention laptops running on Clawhammer!
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Yeah, I didn't mean to bring price into it - that will of course change everything. That's why I said "all things being equal" - assume that applies to price too ;) The most important part of "64-bit" for most people is address space. There can be some performance benefit as well, but as you say, they're not worth the cost considering alternative ways to get the same raw horsepower. The address space increases exponentially, but the performace gains from parallelism increase only linearly. This cost increase is probably somewhere in between.
XML causes global warming.
Dear God! How fucking lame!
Another hacked on extention to the same old architecture that we've been using since the 4004 and 8080 (no, seriously). The basic 8-bit core, the bizarrely segmented registers, the warped-ass extentions, and the CISC instruction set... it all makes me sick. Not to mention that we're still using a fucking BIOS.
Have you ever used something with OpenBoot? It's incredibly nice.
But no, we're still using a system that's basically an overglorified 386DX.
Despite the speed hit, the IA64 architecture was a step in the right direction. A big step. In this case, AMD is going to be setting the industry back.
Dragging people kicking and screaming into reality since 1996.
Hmmm... that's half an argument....
What do you suggest replacing it with???? There's always going to be 1 dominant force in any industry. I don't see what other architecture you could replace it with.
Even if you spent gazillions of $$$$$$s to fab something twice as fast for the same price the competition would catch up within 18 months anyway and there's no way your gonna get all those x86 binaries recompiled in time.
The nearest anyone got was Alpha with FX!32 recompling those x86 binaries on the fly. On the other hand how much faster is it now.... (please factor in cost) and where's that chip designer fellow gone... Hmmmmm....
There are many architectures to be chosen from - for now we have a clear winner - hyper pipelined CPUs with a huge instruction decoder chopping up the x86 instruction format. Perhaps stack machines or some kind of programmable logic perhaps logic in memory. 1 thing is clear - it had better be able to keep up with the best x86 CPU whilst running x86 code. It is the dominant binary format.
Matthew
"None of this shit works" -W.Shatner
How on Earth did Apple manage the migration from 68k to PowerPC then? I can even run my old 68k applications under _classic_ under OSX.
The wheel is turning, but the hamster is dead.
Just as a historical footnote... it doesn't always pay to try to jump too far ahead. Check out the history of the Intel 432... ahead of its time, but not exactly a success.
I disagree from an architectural standpoint. In an ideal world, we'd all have 8-bit machines. All our arithmatic would be insanely fast; we'd be able to use combinational logic to allow two probagation levels for ANY operation (add, sub, mul, div, sqrt, log, etc). That's because it's cost effective to do so; a minimal set of possible outcomes. I'm not completely sure, but I'll speculate that it's possible to arbitrarily generate an arbitrarily sized number from just these 8 bits; though most likely it would be programatically (even if done via micro-code), and thus would be non-optimal for larger than 8-bit data-sets. So obviously, as we've been able to, we've increased the data-length throughout history as we've demonstrated a need.
Contrary to the impression that's given in these posts, a larger word size fundamentally is slower in calculating smaller values. Sticking with higher performance two-stage combinational logic requires an exponentially increasing number of transistors. Breaking the logic up into tiers allows designers to trade the number of transistors for the number of probagation delays. The more delays, the slower the clock; the more transistors, the less practical the design (due to heat, cost, and feasibility of fabrication). Pipelining somewhat helps aleviate the issue of extreme probagation delay, but it's impossible to achieve 100% efficiency, and thus you're practically garunteed slower operation for deeper pipelines. What's more, pipelining requires additional probagation layers for buffering, so you take an immediate performance hit; speculating that you'll achieve greater over-all performance.
In an ideal architecture, you'd minimize the probagation delays for each instructional unit, but practical measures say you must group most, if not all, of the CPU such that the slowest part drives the system. (P4's are nice in that they sub-divide the clock for the simpler integer units).
Combining the two ends, we can better appretiate the trade-off.. If we're performing large-valued arithmetic which is slow programatically (emulated 64bit), then it's worth the extra cost (towards the speed of each operation, and in terms of the number of transistors). In other words, one hardware 64bit add is most certainly faster than than several assembly language instructions that piece together 32bit values. BUT, now all your 32bit arithmetic is slower (unless you have separate 32bit/64bit logic cores).
It's possible to design 32/64bit cores that only take as many clock-ticks to complete as necessary, and thus 32bit arith isn't horribly slower, but there are definately additional probagation delays. The augmentation to 64bit can never increase the speed of a 32bit operation. (Any speed ups must be due to over-all advances in computational efficiency, which should benifit a pure 32bit core even more).
The trade-off must then be a statistical one. We cost out the largest word size that provides benifit. You're going to have arbitrarily large ALU operations (just look at encryption), so choose a cutoff where a certain percentage of all operations occur at that high of a word size. This is how we moved from 8 to 16 bit, and then the painful shift from 16 to 32 bits. And for server-targeted machines, the shift has already been cost-out to adopt 64bits. The desktop has not yet made sufficient requirements to adopt 64bits, though the underlying x86 CPUs are being shared in server-space which is nudging 64bit's acceptance.
Another important factor (which is presumably obvious in concept) is that a higher word-size has a greater probability of wasted space. A 1-bit boolean, for example, wasts 63bits.. Booleans are very common, and though they can easily be consolidated in c-struct's, such is rarely the case, since there are memory alignment issues (and flat-out laziness on the part of programmers). The wasted word-space also affects the instructions. Rarely do you actually see 64bit aligned CPU-instructions (except in VLIW or in places that the data-word-size was irrelevant). Such a situation would have massive implications towards performance. But one serious consideration is that the population of 64bit constants using a 32bit instructional word is expensive. Now you have to perform at least 3 (probably 4 or 5) instructions just to load a constant. Suddenly "a++" starts to look scary (at least when non-optimal compilers are used). In all cases sub-word-size'd instructional arguments are permissable to the delight of compiler designers, but there are still classes of problems that thwart this.. Namely memory addressing...
Memory addressing is arguably the strongest supporter of 64bit architectures. The 4GB limit is already apon us on desk-top machines (I have half a gig on all my home machines, and I don't need it). When you add swap-space, it's entirely possible for modern desk-tops to run enough apps to desire 4+Gig of memory. (Especially considering that large chunks of the address space are wasted). Aside from the various tricks designers have employed over the years to avoid augmenting the address space (8086's segment-registers, 80386's segment-selectors, OS's swapping out apps completely from memory, etc), it's arguably slower to emulate larger address spaces.
In addition to the above arguments against larger address spaces, there is massive cache polution; doubling the word-length, literrally halves the usefulness of a cache-line-load, unless you were previously emulating a larger word-size. You can only load 4 words on a pentium-class cache-line-fill instead of 8. Your bandwidth requirements litterally double (unless you don't standardize at one word-length).
Now in contrast, there are a few advantages. If your minimal word-size is larger, then the number of address pins that you need are reduced. But this is really independent of the core word-size. Pentiums have long required 64bits for their external bus, and use even larger cache-line sizes. Thus most of the advantages attributed to this argument are moot.
Theoretically, an architecture can be designed to split an ALU such that it acts as either 1 64bit unit or 2 32bit units. This is especially true for vector-cores (which are already up to 128bits for main-stream processors). In general, however, there is still the trade-off here, since additional logic-probagations are required which slow down the general case of only a single But comparing the X-box and the Nintendo 64, which were released many years apart won't buy you much of a conclusion other than current processors are generally faster than older processors.
I'd like to address the nature of large bit-sizes with respect to graphics. While this isn't my expertise to the extent of the above, this primarily affects the bus width. In graphics, you commonly have multi-integer structures (red, blue, green, alpha (opacity), Z-depth (the depth into the screen the geometrical object that drew this dot is), stencil, etc). The entire structure is usually just 16bits, 32bits, 64bits, etc. The larger the structure, both the more features you can pack into it, and the more accurate each individual number can be. Thus saying that an architecture is 128bits purely based on this is very misleading. What's even worse are labeling the bus-width numbers (e.g. 128, 256). That's like calling the Pentium I a 64bit CPU, just because it has a 64bit bus (used purely for cache-line burst fills). Yes it makes it go faster, but so does shortening the length of each wire; it's not really innovative. I'll throw this in, but I'm starting to get in over my head; Graphics units (especially the filtering parts) make heavy use of hard-wired combinational logic units. The number of bits going into these units is really meaningless (how many thousands of wires go into the control logic portion of a CPU?). Thus the ability of a custom pieces of hardware to utilize larger bit-depths is unimpressive. What would be impressive would be to say that a Graphics unit does it's integer / floating arithmetic in 128bits so as to minimize error (even though the input/output might only be 8 or 16bits per atomic unit).
-Michael
-Michael
The N64 uses a MIPS processor, not an ALPHA processor. MIPS processors have been 64-bit capable for a very long time...
I print, therefore I am.
The cost, in fact, will be in the middle. The cost will be on the order of n^8 or so, I think. Where n is the number of bits.
-Dan
PS: That is, in fact, huge.
It may be 'kick ass', but the utility as of right now is pretty limited.
Consider: To process any character in the English language, you need only eight bits. That's it. That's one-quarter a register in a 32-bit machine.
And, unless you or the assembler uses a decent amount of technical trickery, that's all you can get in there.
(Case: Intel processors have four main registers: EAX, EBX, ECX, and EDX. These have a high word and a low word (the low words are AX, BX, CX, DX for reverse compatibility with 16 bit code). Each low word has a high bit [ABCD]H and a low bit [ABCD]L. )
Addionally, for numbers.. There ain't too many folks that need to process numbers on the order of 2 to the 128th power, or floats that have, what? twenty digits? thirty digits of precision?
When the numbers get that detailed, you're better off with a quantum system anyway.
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Real life is underrated.
heres a wierd question...Why dont they put some sort of optical controller and coupler between chips?
...but we know most about Intel and AMD's because they need the marketing gee-whiz factor to sell their crap.
Cost. The bill of materials on a motherboard is insanely tight -- they count resistors, remember! All of the fancy interconnect to go optical is way to expensive, and has very little benefite: aka, ROI.
Beside, what good does it bring? I agree that copper limits on a motherboard are approaching rapidly: anyone who has ever tried to debug a RAMBUS implementation knows how painful it is to build interface hardware to debug a 1ghz strobed differential bus. However, I would think that until the b/w at the CPU and DRAM _PINS_ vastly exceeds what is possible with a copper trace, the ROI on optical would be nonexsitant.
I need to re-read AMDs point-to-point proposal, I'm not sure I buy their claim that adding additional CPUs doesn't decrease bandwidth.
As for symmetric-MP, et al: there are lots of weird topologies for MP out there in server-land. The first teraflop machine was PentiumPro bus architecture, which is only 4P scalable on Intel arch, but custom chipsets can do anything!
And when I say "crap", I mean, "crap". I firmly believe that if both giants were not chained to their product roadmap and stock-holders, aka profits, then we would see some truly efficient high-performing architectures. A giant can't take a 90-degree turn... that's why all x86 architectures are basically suped up jalopies -- making too sudden a change can be devastating if you don't have the capital. Look at Itanium -- if AMD spent the resources Intel did, it would have broken their bank like the Cold War broke Russia's. Look at AMD bolting on *-64, it's basically a blower on a Chevette!!!
I'm _really_ rambling, I'll stop now.
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Just your average computer science senior. I like doing assembly work for something like MIPS, and I don't like doing it in x86. The "usual rant" is that x86 is a very old architechture, with ad-hoc features added every so often to let it keep up. As usual as that rant may be, it's quite true. 8 general purpose registers suck. We can do a lot better nowadays.
The engineer in me doesn't like x86 because it's kludgy, and overly complex (has 4 operating modes of which most folks use 2, for example). Intel and AMD have to waste a lot of silicon that translates x86 instructions into their internal instructions. Seems like it's about time to start using something modern, not built on a legacy ISA.
Admittedly, I haven't done too much assembly work. Perhaps x86 is great. But most of the reading I've done and the system architechture classes I've taken lead me to believe that x86 is just a little too dated.
When the 8086 processor debuted it was by far an inferior processor to both the Zilog Z8000 and the Motorola 68000. It wound up dominating the market place for several reasons.
1. Software - the 8086 had a leg up on everyone because it had a translator which allowed the thousands of CP/M applications to be ported to it easily. The killer ap at the time was WordStar.
2. The 8086, and in particular the 8088, were less expensive to build machines around.
3. The 68000 and the Z8000 were comparatively elegant and beautiful designs; the 8086 was strong and ugly. Pick Mike Tyson over Cindy Crawford in a fight. Intel was able to turn marketing from a engineering and software beauty contest into a fight - and it came out on top.
Today the shoe is on the other foot.
1. The Opteron does a much better job of running 32 bit aps than either Merced or Mckinley - similar to advantage 1 above.
2. The Amd processor will be a lot less expensive to build for - reason number 2 above.
3. The Intel processor has the beautiful new architecture - the Opteron the good old strong and ugly one.
The only way Intel is going to come out on top this time is to make an even stronger and uglier 64 bit version of the X86; something which looks like a 64 bit version of the current Pentium 4 - ridiculous pipeline for super high clock speeds etc.
Right now things don't look very good for Intel.
The first thing that comes to my mind is "optional", which is perhaps not so good for the company holding the second place in the market. Maybe they should have called it the "Superon".
Incidentally, I wonder how many people relalize that "durus" means "hard" in Latin, so "Duron" was kind of suggestive...
Aren't these are the same men, women, and managers (children, managers, whatever ;-) who buy new computers and apps every 1.5 years anyway because their previous computers die of Old Windows Disease/Planned Obsolescence/Lack of Support/etc? They re-buy most of their hardware and software over and over again.
Besides a larger memory address space, does this 64-bit architecture do anything significantly better than the 32-bit stuff out there now?
-ted
8 bits?! Why 8 bits? You make it sounds like this is atomic, when it's not. At all. If you're going to go for the theoretical minimum, go for 1 bit. The CM-1 used 1 bit processors, and could do everything. But why 8 bit?! That's sort of whack.
A) consolidate in c-structs? Programmer laziness?
Don't bash the programmer, at all. That's just cruel. The programmer shouldn't have to. That's the compiler's job. However, that can often slow down the code, when it has to mask all the bits, op, then mask all the bits again. So, just using one word for a boolean makes sense. Surely, though, a compiler could do what it wans.
B) Constants get loaded into a different segment than the code, so they won't be in the code, most likely. Unless they're ints or somesuch, in which case you can just use an add-immediate to move them in, and in almost all cases (as you YOURSELF very specifically state) they won't take up more than one immediate.
C) "a++ looks scary"? Umm, a++ will still take one operation (add $rx, $rx, 1). What are you even talking about? Not to mention that compilers optimize.
D) You can still have 32 bit data values in a 64 bit computer by loading the words from memory differently, so don't think that suddenly EVERYTHING has to be in memory as a 64 bit value just because your architecture is that.
E) On a 32 bit architecture (at least, real ones), the 4 gig memory limit (2 on certain ones, e.g. MIPS) is per process, not per system. Thus, you can have many processors, each of which have 4 gigs of memory allocated and using running on a computer with 512K of memory. It would be slow, but that's the beauty of software.
So what you have is a SIMD processor, that can work on 16 8-bit operands at the same time (same opeartion, parallel data). The MMX/SSe ALU is 8-bit wide, not 128bits!!!!
The original post asked for wider buses like game consoles. Are you under the impression that game boxes are multiplying 128-bit long numbers together? No. They're working on little pixels and single-precision floating point coordinates.
Very few people need 64-bit integers for math, either. As I said, the big deal is longer address pointers.
Then again most people here have no frigging idea about CPU design, and they speak from their asses.
Rest assured, I know plenty about CPU design.
Nothing magical about 8bits, except that we like multiples of 8. An 8bit add requires two 8bit numbers = 16input bits, and 8 output bits. Ignoring optimization and implementation complexities, that's on the order of 65 thousand transistors for a two-level adder. That's definately do-able in today's technology.
Two 16bit numbers on the other hand, would likewise require on the order of 4 billion transistors, which it not currently possible with today's technology (my guess is that by the time it is, we'll be using 128bit ALU's).
My point was to find the most practical pure combinational logic unit. Thus to suggest a 1-bit machine implies that we miscommunicated.
An alpha has a nice little byte-swapper which relatively efficiently extracts a byte out of a multi-byte word. It's computationally slower to work with than just testing the whole word, but when you take into account bandwidth / cache-space considerations, it's a boon. It can't be easy for a compiler to optimize away:
struct {
int f_flag1, f_flag2;
}
Can it drop the flags down to 1 byte?
While it's not always true for each architecture, you should find higher performance swapping out the int's with char's.
I'm not familiar enough with the state-of-the-art in compiler technology, so perhaps this can be determined. I was just generalizing on this type of point, nothing more.
The points you mentioned here would be included in the sort of tricks that have been devised over the years to avoid upping the word. It just furthers the idea that larger word-sizes are expensive and worth side-stepping.
-Michael
-Michael
I think the problem with IA-64 is the fact in order to take advantage of the CPU you have to essentially write every application program from scratch. That is quite expensive, given the costs of development hardware and programming time.
With x86-64, you can jump to 64-bit computing without having to dump your legacy code altogether. With some careful recompiling, just about all Microsoft apps today should run in 64-bit mode on the x86-64 platform fairly quickly.
Also, Linux support for x86-64 has been around for some time. I'm sure that it wouldn't take much to release an x86-64 compliant version of every major Linux commercial distribution within one year anyways.
Besides, the cost of IA-64 hardware is still somewhere in the stratosphere, to say the least.
"64-bit processors tend to be slower than there 32-bit counterparts"
Depends on the Architecture, if the instruction
sizes are the same, and the 64-bit chip can
also run 32-bit code, then clearly the 64-bit
one will be faster.
Best guesses so far, reckon
that x86-64 code should be about 15% faster than
x86 code, mostly due the doubling of the number
of registers from 8-int 8-fp (SSE) to 16-int
16-fp. This is in additional to a estimated
25% gain in speed over the Athlon at the same
clock speed and however many, more GHz AMD can
squeese out the new core.
You don't need the hardware. There has been an AMD produced emulator for x86-64 available for some time so people could work on ports. See AMD's x86-64 website. Linux (and/or a BSD variant) got ported to x86-64 some time ago - all without hardware. It was a front page story on Slashdot when it was announced.
Top Most Bizarre/Disturbing Error Messages
I think AMD did pretty well with promoting and supporting x86-64. The x86-64 website has soeme decent stuff including emulator, experimental compiler, etc. It was a smart move and got the developers on board early.
Top Most Bizarre/Disturbing Error Messages
So big bad Intel is going to face even more competition. Boo Hoo. Competition is good. My only concern in all this is that AMD being in bed with M$ will mean they won't be as inclined to say.. help tweak gcc for their new architecture. Intel would be smart to fully embrace the Open Source community at this time.
Check out http://www.x86-64.org/. It's AMD's site dedicated to porting Open Source software to x86-64. This includes the Linux kernel.
Why should MS recompile anything? They can just translate the binary from 32-bit to 64-bit opcodes. That is how they ported 8-bit 8080 BASIC to the 16-bit 8086 after all.
Whenever I hear the word 'Innovation', I reach for my pistol.
Umm, adders are actually linear in size of transistors (at least without special logic). I think that a 16 bit adder would take on the order of 500 transistors, not 4 billion. No chip, yet, has 1 billion transistors (that I know of).
B) That's why people have bool's already. Also, if you only assign 1's or 0's to the ints, then it can drop them down. This is how auto-vectorization works.
E) This isn't a matter of upping the word, it's a matter of virtualization, which is a useful abstraction.
But microsoft can't compete with AMD. It would take them too long to spin up, and they don't know shit about that industry. AMD, on the other hand, could EASILY compete with microsoft, by the simple expedient of hiring some programmers to work on linux, or some other open source operating system. I just used linux as my example to yank your chain. They contribute code, gain cred, and make a whole bunch of crap work beautifully with their equipment.
Won't happen though, because business as usual is good for everybody - Well, if everybody's a big company. It sucks for us, good thing competition isn't going to go away any time too soon. Even if AMD or intel went under, there would still be other CPUs in the world. But anyway, intel and AMD could conceivably swap places - over time, and they are getting closer, you must admit - but it would just end up being AMD vs. intel with AMD in the position of power. We can play musical chairs, but the tune stays the same.
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
LAHF = Load AH with flags
The LAHF instruction loads some of the condition flags into the AH register. The bit positions emulate the flags register of the 8008 processor so LAHF+PUSH AX is equivalent to PUSH A. This instruction was designed to support automatic translation of 8085 code to 8086.
All x86 processors still support this instruction (yes, that includes your latest Pentium)
Stop worrying about the risks of nuclear power and start worrying about the risks of not using nuclear power.
The PS2's CPU, the Emotion Engine, has 128-bit wide general registers, 32 of them to be specific (GPR00-GPR31). It has a 128-bit wide internal bus. However, most common MIPS-inherited instructions only act on the lower 32 bits of the registers; there is a special class of "parallel" instructions that work much like MMX, i.e. they act on parts of each register in parallel. Clear?
;^)
And the 2560-bit wide thing is inside the Graphics Synthesiser, between the rasterizer and the memory. It has 4 MB of frame buffer, implemented on the same chip (embedded DRAM), which is why the bus can be that big. It gives for nice-looking bandwidth numbers, if nothing else.
main(O){10<putchar(4^--O?77-(15&5128 >>4*O):10)&&main(2+O);}
[i] When was the last time you needed to count to that large a number[/i]
Prime numbers, large numerical simulations of gas glouds (yes I know there are other ways of doing this....)
One of the bugs I found in Absoft's compiler came when I made an array too large: in a derived type in a copiler of Cray lineage, the resulting array is bit-addressed. I had the physical memory for the array I needed, but couldn't adress it in 32 bits . .
hawk, who had more memory than any of absoft's test machines at the time
hawk
More likely 'cause MS are the proven abusers of a monopoly position. Each of the others are big players but none have the power of Microsft (who are the only people I can think of that they gang up on!).
Never underestimate the dark side of the Source
Intels solution puts a huge responsibility on the compilers to "get it right".
Then again, alot of former Alpha compiler folks are now working for Intel. They are probably the best compiler engineers on the planet.
What's my Karma Mr. Burns? "Excellent"