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Strained Silicon Chips From Intel
Quirk writes "NewScientist is reporting...
"Intel has taken the wraps off a secret technique it is using'Strained silicon' chips to increase the speed of its Pentium and Centrino chips. The technique boosts the rate at which transistors switch, without having to make them smaller.""
I know IBM has been publically working with this, at least in research, for a long time, and it's a fair bet other firms were too.
IIRC they've even used SSoI (Strained Silicon on Insulator) for some production ASICs...
"The worst tyrannies were the ones where a governance required its own logic on every embedded node." - Vernor Vinge
Dupe, Maybe read this 2.5 year old story
Shoot, I should tell you about strained silicon. That overclocking experiment I did a couple years ago went horribly wrong when the water pump failed and smoke started pouring out of the case. THAT was decidedly strained silicon. :-)
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Intel sees chip futures strained
Intel strains to find new chips
Intel strains to make chips faster
etc... ad nauseum.
Pulling on my processor with two pairs of pliers just bent a few of the pins and made it smoke a bit...
All of this is at the atomic level, but I do wonder how these things hold up to mechanical and thermal stress.
To stretch the silicon lattice, Intel deposits a film of silicon nitride over the whole transistor at high temperature. Because silicon nitride contracts less than silicon as it cools, it locks the silicon lattice beneath it in place with a wider spacing than it would normally adopt. This improves electron conduction by 10 per cent.
What temperature ranges does this become an issue? If my processor gets warm, will its performance decrease because the strain dissapeared?
Would mild mechanical stress on the chip (i.e. application of heat-sink) alter the strain?
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...who claim we're coming to the limits of silicon, and XXXX MHz is the highest that can be achieved. Technology will keep on advancing relentlessly, changing and adapting.
Pick an absolute limit for the speed of a CPU... then proceed to completely ignore it. Can't go wrong there.
The announcement, at the International Electron Devices Meeting in Washington DC last week, gives a glimpse into the intensely secretive way chip firms attempt to gain an edge over their competitors in a market worth over $100 billion a year. Chip market worth 100 billion dollars ? Wow. That is the thing that stood out for me in the article.
-Vib, videogame freelancer for news0r.com, videogame.net, and vnorby.tk
Still, Butler is frustrated with what he thinks of as myopia in the US computer business. "Europe and Japan have been investing in diamond semiconductor research," he says, citing the Japanese government's announcement in December that it would begin allocating $6 million a year to build a first-generation diamond chip. "Bob Linares has given the US the advantage, but nobody's paying any attention," he says. "If we're not careful, the Japanese or the Europeans are going to claim the diamond niche."
Indeed, Intel's top materials executives weren't aware of the latest research breakthroughs when I spoke to them in June, although they certainly understood the potential for diamonds in computing. "Diamonds represent a seismic change in semiconductors," says Krishnamurthy Soumyanath, Intel's director of communications circuits research. "It takes us about 10 years to evaluate a new material. We have a lot of investment in silicon. We're not about to abandon that."
Click here for full article.
Indeed, in fact this is of absolutely _NO RELEVANCE_ to strained silicon FETS. Please inform yourself before posting, and consider not posting halve-knowledge.
Intel may be right on this one - they always have been conservative and this worked out very well for them. Large companies often wait for smaller companies to take the risk and prove or disprove the viablity of new tech. Nobody knows how well diamond is going to work out!
Remember GaAs?
This is most probably a fake:
o stackable chip - unpropable
o 64Bit extension by module? Good joke, there is just no way to provide this technically..
o "lots of wires" - no way, you dont get above 20MHz when connection a CPU by wires
o 4000MHz front side bus - no way there is a tenfold increase.
Try harder next time..
In a response, AMD announced development of "stressed silicon", while VIA reportedly has only managed to "get their silicon slightly worried", according to one unnamed source. China, meanwhile, announced a multi-million dollar project to have silicon going into hysterics within five years.
Trust the Computer. The Computer is your friend.
Silicone? I was expecting a story about Pamela Anderson.
Damn.
And the Intel fanboys make fun of the AMD fanboys? Very mature.
Intel and AMD both have a variety of technologies available to them, sometimes uniquely, sometimes shared or licensed.
Currently AMD holds the speed crown with the hammer series of chips. Before that, intel held the speed crown when the P4 series ramped up to the very high clockspeeds it was capable of. Before that, AMD held the speed crown when it beat intel soundly to 1GHz. Before that, intel was everything.
When you consider that now, AMD seems to be a low-end commodity CPU technology leader (first to get 64bit on the desktop and all), and intel have changed their plans by announcing work on an x86-64 CPU, but intel by far has a huge installed base and the same entrenched loyalty in consumers that Bill Gates enjoys (They are the biggest, most expensive company so their product is more reliable FUD).
I'm interested in seeing who will win out - the larger company with the market share (but less innovative product), or the innovator with a cheaper, more powerful product. I think intel will win, after observing the linux/windows market competition.
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Microsoft has been stressing silicon, including Intel's, for many years!
Anything P4 and later has the built in temp sensor that slows down the cpu if it overheats. If your cpu is getting so hot that its melting silicon then you have bigger problems to deal with. The tomshardware video still gives me a chuckle when the AMD chip goes *poof* and smokes without a heatsink. Trying to save a few cents I suppose.
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Note that Intel improved the P channel devices 25% and the N channel devices 10%. Since N channel devices are usually 2 to 3 times stronger than P channel devices, this reduces the difference and makes CMOS design a little bit nicer.
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Headline-Intel sees IBM and AMD tech doing well, decides to copy.
link
Silicon on Insulator, Copper Interconnects, DDR memory, dual core, but not HyperTransport yet.
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If Linux could run all the programs that MS does, I would say your logic made some sense but the fact is that linux is "johny come lately" when 90% of the desktop was already tied to MS. Linux can't run everything that MS does and it is not realistic for most people to switch all software and everything they know to something completely new. That arguement does not hold true for the AMD/Intel market. What runs on Intel will run just as well on AMD with no change in user experience (often without any knowledge of what chip they are using).
I miss the Karma Whores.
The only way to get 3D straining would be to have a 3D substrate, with the transistor material embedded within.
It seems to me that, in such a configuration, the substrate would interfere with the operation of the transistor.
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Sure strained silicon is great, but the real advance was the world's smallest colander.
Letter To Iran
Some factual mistakes in your post.
1. I don't recall Intel announcing anything about any x86-64 CPU.
2. Intel's products are more reliable, as they spend a _lot_ more time testing and qualifying their products than any other manufacturer.
There are several new technologies that either are speeding up chips, or will speed up chips, and the best part is that they'll all work together.
For some time, SOI (silicon-on-insulator) has been helping chip manufacturers squeeze out extra performance. And the straining of the silicon lattice (strained silicon) helps as well. And you can combine them into SSOI, strained-silicon-on-insulator.
Well, there's also one other technology that's been developed, called "fully depleted silicon". And guess what - it should/will be possible to make fully-depleted, strained silicon-on-insulator chips. (FDSSOI?)
Between moving to 90 nm, then 65nm, and then further, as well as integrating high-K dialectrics and fully-depleted, strained silicon-on-insulator manufacturing technologies, we've still got a lot of headroom to keep cranking out faster and faster processors. Moore's law has still got a long time to live. And that's even if we don't make any new breakthroughs, but my guess is that the chip makers will continue to pull aces out of their sleeves, so to speak.
steve
Oh, you're not stuck, you're just unable to let go of the onion rings.
I'd like to know if the lattice could be stretched in all three directions, rather than just one. And if so, would that provide any benefit? Or does the benefit come from that directionality?
It would be stretched in all directions, but usually the thickness is kept as small as possible, so the effect in that direction is minimal. The idea is to increase the carrier mobility between the source and drain, which is mostly a 1-D proposition: the electrons (or holes) flow from the source towards the drain, in as close to a straight-line as possible. Of course, the other 2 dimensions count as well, but not nearly as much as on the plane between the source and drain.