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Strained Silicon Chips From Intel
Quirk writes "NewScientist is reporting...
"Intel has taken the wraps off a secret technique it is using'Strained silicon' chips to increase the speed of its Pentium and Centrino chips. The technique boosts the rate at which transistors switch, without having to make them smaller.""
I know IBM has been publically working with this, at least in research, for a long time, and it's a fair bet other firms were too.
IIRC they've even used SSoI (Strained Silicon on Insulator) for some production ASICs...
"The worst tyrannies were the ones where a governance required its own logic on every embedded node." - Vernor Vinge
Dupe, Maybe read this 2.5 year old story
Shoot, I should tell you about strained silicon. That overclocking experiment I did a couple years ago went horribly wrong when the water pump failed and smoke started pouring out of the case. THAT was decidedly strained silicon. :-)
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Intel sees chip futures strained
Intel strains to find new chips
Intel strains to make chips faster
etc... ad nauseum.
Pulling on my processor with two pairs of pliers just bent a few of the pins and made it smoke a bit...
All of this is at the atomic level, but I do wonder how these things hold up to mechanical and thermal stress.
To stretch the silicon lattice, Intel deposits a film of silicon nitride over the whole transistor at high temperature. Because silicon nitride contracts less than silicon as it cools, it locks the silicon lattice beneath it in place with a wider spacing than it would normally adopt. This improves electron conduction by 10 per cent.
What temperature ranges does this become an issue? If my processor gets warm, will its performance decrease because the strain dissapeared?
Would mild mechanical stress on the chip (i.e. application of heat-sink) alter the strain?
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...who claim we're coming to the limits of silicon, and XXXX MHz is the highest that can be achieved. Technology will keep on advancing relentlessly, changing and adapting.
Pick an absolute limit for the speed of a CPU... then proceed to completely ignore it. Can't go wrong there.
Intel potentially uses a new technology that AMD doesn't have, and fan boy talks about how much better AMD will be than Intel when AMD implements said technology. ROFL.
The announcement, at the International Electron Devices Meeting in Washington DC last week, gives a glimpse into the intensely secretive way chip firms attempt to gain an edge over their competitors in a market worth over $100 billion a year. Chip market worth 100 billion dollars ? Wow. That is the thing that stood out for me in the article.
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Still, Butler is frustrated with what he thinks of as myopia in the US computer business. "Europe and Japan have been investing in diamond semiconductor research," he says, citing the Japanese government's announcement in December that it would begin allocating $6 million a year to build a first-generation diamond chip. "Bob Linares has given the US the advantage, but nobody's paying any attention," he says. "If we're not careful, the Japanese or the Europeans are going to claim the diamond niche."
Indeed, Intel's top materials executives weren't aware of the latest research breakthroughs when I spoke to them in June, although they certainly understood the potential for diamonds in computing. "Diamonds represent a seismic change in semiconductors," says Krishnamurthy Soumyanath, Intel's director of communications circuits research. "It takes us about 10 years to evaluate a new material. We have a lot of investment in silicon. We're not about to abandon that."
Click here for full article.
I'd like to know if the lattice could be stretched in all three directions, rather than just one. And if so, would that provide any benefit? Or does the benefit come from that directionality?
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That is definitly not true - please supply reference if you believe otherwhise.
Indeed, in fact this is of absolutely _NO RELEVANCE_ to strained silicon FETS. Please inform yourself before posting, and consider not posting halve-knowledge.
Intel may be right on this one - they always have been conservative and this worked out very well for them. Large companies often wait for smaller companies to take the risk and prove or disprove the viablity of new tech. Nobody knows how well diamond is going to work out!
Remember GaAs?
This is most probably a fake:
o stackable chip - unpropable
o 64Bit extension by module? Good joke, there is just no way to provide this technically..
o "lots of wires" - no way, you dont get above 20MHz when connection a CPU by wires
o 4000MHz front side bus - no way there is a tenfold increase.
Try harder next time..
In a response, AMD announced development of "stressed silicon", while VIA reportedly has only managed to "get their silicon slightly worried", according to one unnamed source. China, meanwhile, announced a multi-million dollar project to have silicon going into hysterics within five years.
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Silicone? I was expecting a story about Pamela Anderson.
Damn.
Microsoft has been stressing silicon, including Intel's, for many years!
It's somebody else's joke (I think I read it on the Register or the Inquirer), I can't take credit for it.
I found it pretty funny though.
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Anything P4 and later has the built in temp sensor that slows down the cpu if it overheats. If your cpu is getting so hot that its melting silicon then you have bigger problems to deal with. The tomshardware video still gives me a chuckle when the AMD chip goes *poof* and smokes without a heatsink. Trying to save a few cents I suppose.
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Note that Intel improved the P channel devices 25% and the N channel devices 10%. Since N channel devices are usually 2 to 3 times stronger than P channel devices, this reduces the difference and makes CMOS design a little bit nicer.
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Headline-Intel sees IBM and AMD tech doing well, decides to copy.
link
Silicon on Insulator, Copper Interconnects, DDR memory, dual core, but not HyperTransport yet.
ignorance is bliss. googlefiberatx.com
Strained Silicon: Ancient Chinese Secret....
-gong-
nothing.can.stop.me.now
If my silicon is always straining, should I dap a little Preperation H on the heat sinks?
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What the hell does this have to do with the article?
What? Me? Worry?
Sure strained silicon is great, but the real advance was the world's smallest colander.
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This is so laughably stupid on so many levels I can only assume it's an inelegant attempt at a troll.
What's funny is you probably think it's subtle and clever. _That's_ why I laugh.
There are several new technologies that either are speeding up chips, or will speed up chips, and the best part is that they'll all work together.
For some time, SOI (silicon-on-insulator) has been helping chip manufacturers squeeze out extra performance. And the straining of the silicon lattice (strained silicon) helps as well. And you can combine them into SSOI, strained-silicon-on-insulator.
Well, there's also one other technology that's been developed, called "fully depleted silicon". And guess what - it should/will be possible to make fully-depleted, strained silicon-on-insulator chips. (FDSSOI?)
Between moving to 90 nm, then 65nm, and then further, as well as integrating high-K dialectrics and fully-depleted, strained silicon-on-insulator manufacturing technologies, we've still got a lot of headroom to keep cranking out faster and faster processors. Moore's law has still got a long time to live. And that's even if we don't make any new breakthroughs, but my guess is that the chip makers will continue to pull aces out of their sleeves, so to speak.
steve
Oh, you're not stuck, you're just unable to let go of the onion rings.
This is why slashdot needs a "Moron: -1" or "No longer on speaking terms with reality:-2" Moderation. . .
RTFA, the tech is old, the story is they are giving away the technique. And thank you for demonstrating that you have no idea what you're talking about when it comes to chip design.
The sort of blind zealotry you are exhibiting frightens me deeply, did you even think about what you wrote? Do you REMEMBER what utter CRAP AMD chips used to be???
Note: Every system I've built in the last 3 years has been an AMD.
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This is slashdot. You must be new here!
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Francis Smit
The article states that compressing p-doped regions improves hole conduction and stretching n-doped regions improves electron conduction. Fair enough, but to me the p-doped and n-doped designations are either backwards or irrelevant.
For example, an n-channel MOS device is built in a p-type well. The channel (region between source and drain) is p-type when the device isn't conducting current, but the channel must be inverted to n-type before electrons can flow from source to drain. Correct me if I'm wrong, but it would make more sense to say that the p-well is stretched so that when it is inverted, electron conduction in the channel is improved.
I wonder how much layout re-work had to be done to implement moats of SiGe around individuel transistors or groups of transistors. Yikes!
I've been reading /. for quite a while now and still shake my head at some of these responses, I made an opinionated statement which I'm entitled too and have been attacked for such and called ignorant as well as being moderated (in my opinion unfairly) as a flamebite.
The hostilities that have been prevelant throughout most posting are often extremely disheartening and unprofessional. Personally I'm just a bit awe-struck. Maybe it could have been worded better, maybe it could have been better researched, maybe i have no clue what I'm talking about, but beratement is just going to turn me off of this site and lack of understanding is going to make me resent this place and eventually I may just turn into one of these bitter posters who have nothing constructive to say and therefore rely on showing my own supposed intellectual superiority by belittling those who are actually trying to improve upon their own knowledge. Therefore, I say if you don't have something constructive to say gfy.
"And The Geek Shall Inherit The Earth" --Jeff Darlington
I stumbled upon your post at a very unfortunate time, and my reply was made in haste and at wits end. It was a very petty and unprofessional thing to do, but it seemed to sum up, exactly, the attitude that was, at that very moment causing me such grief.
you have my formal appology for what was written previously. Allow me to make another attempt at it.
My experiance with Pre K7 chips from AMD (a K5, a K6-2 and a K6-3) left me with a very bad taste in my mouth as to the performance of early AMD chips. In three words "It was shit", this all changed when the K7 line came out, but AMD hasn't always been the paragon of virtue and excellent design. If I remember correctly, there were Bad Things involving floating point calculations. (Though not as bad as the Pentium FPU 'issue')
The artical stated that the tech was old and that Intel ahd been using it for a while. The news worthy part of it was that they were publicly releasing their technique. I would assume that they would not do this if their top competitor had not already been using the same, or an equivelent, technique. Thus it's old news to everybody it matters to, but nifty to know how it works.
Your offhand dismissal of things is a big part of why my reply was so heated, and why I'm sure you got moderated as flamebait. (Which, as a point of note, your post was, as it collected a few flames). As an example "Not to mention with AMD's new 64 bit architecture this silicon stressing will really be just to keep up with AMD." 64 bit architecture is old hat in fields of Very Serious Computing, it's new to the desktop though and that's something spiffy. But it's not "AMD's new 64 bit. . " The G5 is 64 bit, Intel has a 64 bit chip. AMD has just brought it to market the best.
Yes it 'just focuses on the clock speed of a processor', yes a 20% boost in clock speed is not a 20% boost in performance over all situations, but it is a valid increase in performace in many situations.
"Switching faster won't increase the bandwidth, maybe it will just be able to push more through the same amount of space then?" I presume you're talking about RAM CPU bandwidth? Once again the performance inpact that this has is highly dependent upon the code being excecuted. If you do not believe this then please go learn assembly, it may be a very rewarding and enriching experiance.
Perhaps, in the future, if you worded you posts more like you were one of "those who are actually trying to improve upon their own knowledge" and less like you were stating Immutable Truths of the Universe, you would recieve more friendly replies.
As I briefly stated in the first post, I am a very happy AMD consumer, and I use AMD chips in every desktop that I've built for myself or others in the last several years. My current desktop is an AthlonXP (2400+) running at 2.3GHz on a 200MHz FSB, I love that chip. It was inexpensive, and has awsome performance. But that does not preclude me from admiring some of the accomplishments Intel ahs brought to the board in terms of pushing clockspeed (which, don't forget, is pretty much the primary requirement if you're going to be running instructions which MUST be excecuted in serial). Interl has done some very interesting things, but right now AMD kicks ass.
Don't let your love of something blind you to it's flaws or to the virtues of others.
Undoubtably this post is filled with spelling and grammer errors. But I never clamed to know anything about those. . .
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