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A History of PowerPC
A reader writes: "There's a article about chipmaking at IBM up at DeveloperWorks. While IBM-centric, it talks a lot about the PowerPC, but really dwells on the common ancestory of IBM 801" Interesting article, especially for people interested in chips and chip design.
IBM Also announced a ton of new PPC information and tech today at an event in new york. Opening up the ISA to third parties including Sony.
I hope you die painfully and alone.
Cut up a russet potato into thin strips or wedges.
Fry in oil or bake in oven.
Salt.
Enjoy!
I still want a PPC ATX board. Pegasos was supposed to deliver, but their boards are still so expensive. :-(
/* oops I accidentally made a comment, sorry */
I'm not a fan of big endian... or is it little endian... I dont remember, but I do know, if it's backwards, it's backwards because it's reverse of what I'm used to.
http://github.com/gbook/nidb
They seem to have left out the part about Motorola totally giving up on PPC advancement, seriously hurting apple.
- Sherman
They also have a very good article about the PowerPC's three instruction levels and how to use implementation-specific deviations, while code stays compatible. This introduction to the PowerPC application-level programming model will give you an overview of the instruction set, important registers, and other details necessary for developing reliable, high performing PowerPC applications and maintaining code compatibility among processors.
John.
You find Douglas Adams fans all over, don't you?
To a Lisp hacker, XML is S-expressions in drag.
"Finally, the Fishkill operation is so hip that the server room runs exclusively on Linux."
I didn't think it was possible to use the words "Fishkill" and "hip" in the same sentence with a straight face.
Gone where the intelligent disk and network subsystems. No more die cast aluminimum chassis.
Whilst I can understand in some sectors the incessant drive for highest MIPS per $, is there not also a place for bullet proof proven technology?
And if you thought that was boring you obviously havn't read my Journal ;-)
back in 94 or so, when the AIM were predicting that they were going to completely obliterate the x86 in a few years. Anyone still have those neat graphs that showed exactly where Intel would hopelessly fall behind while PPC would accellerate exponentially into the atmosphere?
Motorola has a nice overview graphic - you can also checkout a more generalized article at The Star Online.
Correct me if I'm wrong, but isn't the PlayStation 2's EmotionEngine processor a proprietary MIPS-derived ISA?
VHDL, Verilog, something else entirely?
Doesn't it make you feel good to know that our freedoms are protected by politicans, lawyers and journalists.
Is its revolutionary three level cache architecture, utilising a 3-way 7 set-transitive cache structure, which gives performance equivalent to a 2-level traditional x86 style cache for more content addressable memory. Each processor has a direct triple-beat burstless fly-by cache gate interface capable of fourteen sequential memory write cycles, including read/write-back and speculative write-thru on both the instruction and data caches. Instruction post-fetch, get-post, roll-forward and cipher3 registers further enhance instruction cache design, and integrated bus snooping guarantees cache coherency on all power PC devices with software intervention. Special cache control and instructions were necessary to control this revolutionary design, such as 'sync', which flushes the cache, and the ever-popular 'exeio' memory fence-case instruction, named after the line in the popular nursery rhyme.
The PPC ISA has support for both big- and little-endian modes. However, the little-endian mode is a bit screwy. There are some appnotes on the Motorola website on using little-endian mode.
(S(SKK)(SKK))(S(SKK)(SKK))
Self-modifying silicon? Geez. And I though self-modifying code was complicated.*
The Sony connection is nothing surprising, as it has already been announced that Sony is creating silicon with IBM for their next-gen chipset. I wouldn't be the slightest bit surprised to see a PS3 running on a cluster of rebranded (and possibly modified) PPC chips.
P.S. Does anyone know why Windows has never been adapted to run under PPC? While the transition for Apple from PPC to x86 may be without technical merit, why hasn't Microsoft created a server line based on the lower-powered PPC chipset?
*they mention that 'researchers and electronics makers' will be able to modify the chip, and as such the above quote is probably incorrect. The chip may be modifiable, but it is unlikely that will happen at runtime.
The ______ Agenda
I don't see how computer history that goes back to the 1960s can fail to be "IBM-centric." Remember, these were the big guys Microsoft was afraid of pissing off in the 1970s and 1980s. No one ever got fired for buying IBM, because they pretty much wrote the book on chip design before Intel hit it big.
You should check out: Momentum Computer
Sure its pricey, but I suppose if your interested in such price isn't the key issue.
Sunny Dubey
The core has a full mips-3 instruction set, with extensions from mips-4 and mips-5
link
So yes, it is in a way MIPS derived, but the MIPS core does very little of the actual processing, it's more of a bootloader and I/O coprocessor.
There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
Not sure I'd want that on my resume. Wasn't IBM's greatest success -- even given their unmatched maketing department.
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
Had to be a typo, meant "Playstation 3"
MIPS is still popular in some embedded areas, especially since you can buy a parameterized MIPS core ASIC macro, and built custom functions around it. I worked on a project that used one a little while ago.
(S(SKK)(SKK))(S(SKK)(SKK))
Geez, I can't believe I'm saying this, but it would be cheaper to just buy a Mac.
LK
"Hi. This is my friend, Jack Shit, and you don't know him." - Lord Kano
(Which is great until you mispredict a branch, of course. :-)
There are two MIPS processors in the PS2. The main CPU is the Emotion Engine which is based on a MIPS R5900 core and the IO processor which is based on a MIPS R3000 core.
It's actually closer to Intel's Vanderpool technology that allows you to partition the cpu through firmware.
Example: Windows is running on slice 1, BSD on slice 2, and Linux on slice 3.
BSD gets a kernel panic and crashes, the slice is restarted without affecting the remaining running OS's. It's, for the lack of a better term, Hyperthreading for the whole computer.
I hope you die painfully and alone.
Or, you could always settle for an RS/6000.
RS/6000
Or, a Power-based IBM workstation,
Workstation
This sounds like just a bunch of buzz words thrown together.
These blades have a 970 (G5)
______/
/
// / \__
/ / \______ Intel
Time ->
Large and hyphenated! It's nice when technical writers get to slip a little something in on the side.
Wah!
Also, when you say that POWER4/PPC970 can process 200 instructions at once, you need to explain a bit better what having "instructions in flight" really means. It's not that it can do 200 instructions every clock cycle.
Submitted this on the feedback form at the bottom of the article as well. The above just don't ring right as expressed.
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
Maybe this is a sign that it has been too long since I learned about computer architecture, but is it really fair to call a CPU that has a deep pipeline, a crypto-RISC CPU?
When my buddy first told me about this exciting new RISC idea one of the design goals was each instruction was to take a single instruction cycle to execute. Isn't this completely contrary to a deep pipeline? The Pentium 4 has a 20-stage pipeline IIRC.
Was I wrong to laugh when I heard hardware manufacturers claim, "sure, we make a CISC, but it has RISC-like elements .
What I am reminded of is the change in how musicians are classified. When I grew up rock music was just about all that young people listened to. Rap and punk music had never been heard of. And country music was considered incredibly uncool. Now country music's coolness factor has grown considerably. And a strange thing has happened. Lots of artists who were unquestionably considered in the Rock camp back then, like Neil Young, or Credence Clearwater, are now classified as Country music, as if they had never been anything else.
It has been a long time, but I remember learning in my computer architecture course about wide microcode instruction words, and narrow microcode instruction words. Wide microcode instruction words allowed the CPU to do more operations in parallel. Ie. the opposite of a RISC. So, I ask in perfect ignorance -- how wide are the Pentium 4 and Athlon microcode?
If I am not mistaken the Transmeta was a very wide instruction word. And if I am not mistaken, doesn't that make it the opposite of a RISC?
Can anyone tell me where I can buy a G5 laptop?
Yea, IBM is a little late to the virtual processor market. About -10 to -20 years.
Damn them! Dam them to HELL!!!!
I worked on the RS64III ("Pulsar") from June 1997 until March 1998, as a designer of the on-chip bus clock multiplier circuits. This part of the processor was hard-core, full-custom, transistor-level circuit design! :)
Macosrumors.com has an article suggesting an IBM chip known as the PPC975 may be used for future Apple Macintosh computers at speeds of up to 3Ghz.
http://www.macosrumors.com/33004M.html
Please note that MOSR has a long history of being completely and utterly wrong in their predictions, so don't get your hopes too high...
I have been a user for about 10 years. This ends Feb 2014. The site's been ruined. I'm off. Dice, FU
IBM announced today that they will be offering more information on the architecture of its PowerPC and Power server chips to device makers and software developers. First software with Linux, and now hardward with their own Power Line. If intel can only do this for the Centrino line. :-/
Expanding the data to 64 bits has no effect on existing code, whereas the big-endian case will have to change all the pointer values
So, you're reading in an array of integers, which are now 64 bit vs 32 bit and no code change is needed?
Programs NEED to know the size of the data they're working with. Simply pulling data from an address without caring for it's size is a recipee for disaster!
"That's so plausible, I can't believe it!" - Leela
Can anyone tell me where I can buy a G5 laptop?
Sure! Send me your CC info and I promise I'll send you a G5 laptop! I'm also selling Playstation 5s.
...with assembly language and use higher level languages, you wouldn't be concerned with this. ;)
"The RSC implementation of the POWER1 microprocessor was used as the central processor for the Mars Pathfinder mission and is the chip from which the PowerPC line is descended"
I guess that's why it's still up there, not bluescreened...
There exists no way of exchanging information without making judgments. --Bene Gesserit Axiom
What kind of design tools did you use? And don't say pen and paper.
Doesn't it make you feel good to know that our freedoms are protected by politicans, lawyers and journalists.
Gotta love the "Add to Cart" buttons on the POWER 275 workstation page :)
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RISC made each instruction simple. That's how the name was chosen. But the point of machine each instruction simple was so that every transistor could be used in each cycle. By using every transistor, you maximize your performance on a per-transistor basis.
So, to do this, you drop specialized functionality. This meant simplifying the instruction set.
But that produced code bloat, because to really follow the idea you have to ditch stuff like dividers. Dividers are very difficult to fit into a pipeline and so the proper way to follow the mantra is to to expand a division into 32 separate instructions that do one step of the process (or 17 stages with other dividing methods). These 32 instructions could be pipelined, and thus you maximized your transistor reuse.
But this leads to code bloat. At the minimum, you have to do some call setup and takedown to call a division function. So that hardware was put back in. And other hardware followed, until even specialized vector units are allowed.
CISC can produce good performance also if they can utilize all their transistors better.
Did you read this? Look at the second-to-last paragraph:
That is the first step in self-evolving machines.
Yes, it is a minor step, but it is a friggin first step, OK? If they can pull this off, they are creating machines with the ability to adapt and evolve.
This is what I would call artificial life. Once that step is taken, it's only a matter of time before the machines start evolving themselves.
P.S. Now think about the kinds of viruses that could happen in that environment.
I found this site a couple years ago, and i'm sure everyone has heard of it, but just in case: apple-history.com
In the dsp range vliw gets more attention. Take the TI C6000 serie for example. Pure VLIW (8 instruction/cycle for the 8 exec-units) Risc (dedicated load-store arch. etc.) with no pipeline interlock and a very short pipelines you have impressive performance at low cycles/s. In addition you have the advantace off compile ones and have a dedicatet behavior at runtime. Unlike cisc cpus which have to rearange the instructions at runtime you can (if you want) literaly move at compile time any the assembler instruction to the cycle/exec.-unit you want at runtime. Schlaefer i'm sorry for my poor engl.
Seriously, check these quotes from the IBM site: [blockquote] Thus, in the days when computing was still so primitive that people thought that digital watches were a neat idea, it was CMOS chips that powered them. [/blockquote] [blockquote]Figure 1. It's wafer-thin[/blockquote] [blockquote]One of the reasons for that is IBM's new top-of-the-line fab in Fishkill, New York. The Fishkill fab is so up-to-date that it is capable of producing chips with all of the latest acronyms, from copper CMOS XS to Silicon-on-Insulator (SoI), Silicon Germanium (SiGe), and low-k dielectrics -- all on 300mm wafers. And the Fishkill facility is so advanced that the workers don't even have to wear "bunny suits," because the wafers spend all of their time in hermetically sealed FOUPs (front opening unified pods). Finally, the Fishkill operation is so hip that the server room runs exclusively on Linux.[/blockquote]
It doesn't mean much now, it's built for the future.
Help me out here. A quote from the article is:
POWER3
Released in 1998: 15 million transistors per chip
The first 64-bit symmetric multiprocessor (SMP)
Didn't several companies have 64-bit multiprocessor machines out back then? Unless I'm mistaken, Sun's Starfire was before then, having up to 64 UltraSparc II's - which, as I recall, were 64-bit chips. And that's just Sun, ignoring the other players.
So, it is just that they used "SMP", as opposed to other forms of multiprocessing, or is my memory completely skewed?
steve
Oh, you're not stuck, you're just unable to let go of the onion rings.
It doesn't mean much now, it's built for the future.
That's quite impressive. Throw the 970 in that mix and it's even more impressive. The bottom line is that Intel isn't alone at the top of the mountain when it comes to producing high quality, fast, and reliable chips. On a side note, as a soon-to-be-graduating CS major, I dream about working at a place like IBM.
I imagine what they really mean is that there can be up to 200 instructions in flight in the pipeline at a time.
Actually, I believe the wording is intended to communicate the notion of vector processing. Rather than doing the "fetch operand, perform operation, store result" repeated again and again, vector processing allows you to fetch a bunch of operands in a row, then perform a single operation to that vector of data (that is, the data you just fetched), and then store all the results. It turns out it's much faster to do data processing in this fashion.
Supercomputers have done this for years, and it's one of the key ingredients in creating a system which is extremely fast at doing repetitive operations.
Note that the benefits of vector processing are minimal if you're not processing the same type of data again and again. For those cases, a reasonably fast processor is sufficient. It's when you get into repetitive stuff (for an average home user, this might be decoding DVD data) that you'll see the real performance benefits of vector processing.
From this article on the PowerPC 970:
"The PowerPC 970 design starts by remapping one of the POWER4 processor cores to 0.13-micron technology and increasing its frequency up to 1.8 GHz. Next, one of the L2 cache banks was resized to 512 KB. These POWER4 features were then complemented with a vector-processing engine and a redesigned bus interface to keep the 970 fed with data. The result is a higher-performance single-core POWER4 derivative that includes enhanced multimedia processing on a smaller, lower-power die."
to quote the Jargon file:
...such as the IBM S/360 mainframe, had complex and redundant (or "orthogonal") instruction sets...
Orthogonal: Mutually independent; well separated; sometimes, irrelevant to. Used in a generalization of its mathematical meaning to describe sets of primitives or capabilities that, like a vector basis in geometry, span the entire 'capability space' of the system and are in some sense non-overlapping or mutually independent.
to quote the article:
Othogonal is pretty damn close to an antonym of "complex and redundant". In fact, a RISC ISA should be as orthogonal as practical (under the other constraints of constant word size etc.)
While we are at it, the article notes:
"All of that changed back in the thermionic valve (or "vacuum tube") days with the introduction of the IBM S/360(TM) line of computers, in 1964."
Huh? IBM was producing "transfer resistor" ("transistor") computers by the 1960's and the 360 was based on those newfangled "integrated circuits" (or "chips"). At that point tubes were as anachronistic as they are now!
One last howler: the sidebar title "Breaking the speed limits of Moore's Law" I always thought gemometric rates of increase didn't class as a speed limit as much as a brutal taskmaster, if the Transportation Department legislated a doubling of speed every 16 months beginning in 1960, transwarp drives would be required equipment on cars since we would have a minimum speed limit of warp 44!
Nice one!
Doesn't it make you feel good to know that our freedoms are protected by politicans, lawyers and journalists.
I bought IBM stock at 99 per share than again at 92 a share, i was sure it was going to split but all its been doing is falling. i was hoping that all of the new things theyve been doing would drive their stock though the roof bu nothings happening. im starting to think that all stock traders need an IT lesson.
But seriosly, i wounder if sun will end up standardising on the PPC or the AMD 64 chips. their own proccesors are a little long on the tooth.
I'm wondering why they refer to a chip having redundant machine language instructions as being "orthogonal". One would think that redundant functionality would be "non-orthogonal". Sigh.
The nice thing about jargon is that people can resort to it in order to hide their complete ignorance and spread more ignorance and disinformation in the process. It's one of those things that kept me away from computer science in college (not to mention humanities courses. Juxtaposing everything in sight just wasn't my cup of tea).
You don't know shit about hardware design, do you, you fuck-brained, turd-licking, ball-rubber?
I think you do. You're so smart afterall.
From the article:
"What do the Nintendo GameCube's Gekko, Transmeta's first Crusoe chips, Cray's X1 supercomputer chips, Xilinx Virtex-II Pro processors, Agilent Tachyon chips, and the next-generation Microsoft XBox processors-which-have-yet-to-be-named all have in common? All of them were or will be manufactured by IBM."
What the hell? I thought the XBox Next CPU being a PowerPC was still an unconfirmed rumor?
Pegasos deliverd, Pegasos II is available from stock from a number of shops on the internet, and while somewhat more expencive than my x86 Mb I do not think 299 euros is all that expencive.
But it also has a couple of hardware features that are surpricingly enough more advanced than those on my PC such as gigabit ethernet (+ a 100 chip as well) , which for some reason is still surpricingly expensive on a PC, switcher/hup prices are still too high for a home setup though but I have a dual set in one of my PC, one card is connected to a hub while the other has a patch connection between the gigabit cards, the difference in speed is more than noticable.
try : http://www.pegasosppc.com/
What kind of ejaculate have you been drinking, you mindless, butt-slamming cod-licker?
Well, it's my big, stinking, anonymous dick. OK?