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Philips, ARM Collaborate On Asynchronous CPU

Sean D. Solle writes "While not an actual off-the-shelf chip, Philips and ARM have announced a clockless ARM core using what they call "Handshake Technology." Read on for more about just what that means; according to this article, the asynchronous ARM chip has yet to be developed, but the same Philips subsidiary has applied similar technology to other microprocessors.

Sean D. Solle continues "Back in the early 1990's there was a lot of excitement (well, Acorn users got excited) about Prof. Steve Furber's asynchronous ARM research project, "Amulet". The idea is to let the CPU's component blocks run at their own rate, synchronising with each other only when needed. Like a normal RISC processor, one instruction typically takes one clock cycle; but in a clockless ARM, a cycle can take less time for different classes of instructions.

For example, a MOV instruction could finish before (and hence consume less power than) an ADD, even though they both execute in a single cycle. As well as energy-efficiency, running at effectively random frequencies reduces a chip's RFI emissions - handy if it's living in a cellphone or other wireless device."

163 comments

  1. Intel were first... by rhs98 · · Score: 1, Troll

    1997 - "Intel develops an asynchronous, Pentium-compatible test chip that run three times as fast, on half the power, as its synchronous equivalent. The device never makes it out of the lab."

    1. Re:Intel were first... by Anonymous Coward · · Score: 1, Funny

      The device never makes it out of the lab.

      Duh everybody know Intel is all about the clockspeed. How can they sell a clockless cpu?? How could they claim their processor was better than AMD's without some silly numbers to use?

    2. Re:Intel were first... by h0tblack · · Score: 3, Informative

      Read the story.. there were ARM based asynchronous chips in the lab (AMULET) a long time before 97.

    3. Re:Intel were first... by kf6auf · · Score: 4, Interesting

      So the question is WHY didn't it make it out of the lab? Did it cost too much to produce? That's the only real possibility I can think of - I don't think Intel's Marketing Division had absolute power over the company in 1997 to push the MHz agenda.

    4. Re:Intel were first... by jimicus · · Score: 4, Informative

      No they weren't. From TFA:

      The AMULET1 microprocessor is the first large scale asynchronous circuit produced by the APT group. It is an implementation of the ARM processor architecture using the Micropipeline design style. Work was begun at the end of 1990 and the design despatched for fabrication in February 1993. The primary intent was to demonstrate that an asynchronous microprocessor can offer a reduction in electrical power consumption over a synchronous design in the same role.

    5. Re:Intel were first... by Dusabre · · Score: 1

      The dark side is more powerful than you can ever imagine.

    6. Re:Intel were first... by NanoGator · · Score: 1

      "So the question is WHY didn't it make it out of the lab? Did it cost too much to produce? That's the only real possibility I can think of -"

      I read about this once ages ago. The reason it didn't get out the gate was that it would still have taken time to produce. By the time it was done, it wouldn't be 3x faster anymore, it'd actually be slower than whatever was out at the time.

      Take with a grain of salt, I'm not claiming to have a strong grasp of this particular topic.

      --
      "Derp de derp."
    7. Re:Intel were first... by Anonymous Coward · · Score: 2, Insightful

      The biggest problem with asynchronous chips lies in the fact that all the design tools, fabrication facilities, and testing methodologies are geared toward synchronous processors. If Intel or any chip maker were to release an asynchronous processor on a large scale, it would require a MASSIVE overhaul of the industry. It's an investment that requires both time and money on a risky departure from decades of acquired knowledge in designing synchronous chips.

    8. Re:Intel were first... by Anonymous Coward · · Score: 0

      Difficult to debug and everything is based on handshaking protocol. A hybrid between clocked and asynchronous is a more viable choice.

      Async design is very custom hand-made design. You can put the same effort on incorporating more functionalities rather than tweaking a small circuit to give out the last juice.

    9. Re:Intel were first... by mwood · · Score: 1

      So how long did they study the PDP-6 to learn how to do it? :-}

    10. Re:Intel were first... by Pxtl · · Score: 1

      Easy: FlOps.

    11. Re:Intel were first... by drmerope · · Score: 1

      Actually the first Asynchronous Microprocessor (in VLSI) was developed in 1989: The First Asynchronous Microprocessor: The Test Results. A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic, and P.J. Hazewindus. Computer Architecture News, 17(4), 95-110, June 1989. [CS-TR-89-06] The Design of an Asynchronous Microprocessor. A.J. Martin, S.M. Burns, T.K. Lee, D. Borkovic, and P.J. Hazewindus. ARVLSI: Decennial Caltech Conference on VLSI, ed. C.L. Seitz, 351-373, MIT Press, 1989. [PS | CS-TR-89-02 ]

    12. Re:Intel were first... by nongrata · · Score: 1

      I remember reading about asynchronous chip design (I wish I knew where) and the reason they gave for the non-existence of asynchronous chips is that there is no framework support for it, meaning, they don't teach how to design asynchronous circuits in universities (at least not as the main way of doing things) and there is no software to help chip designers to design asynchronous chips.

  2. Such a processor already exists by philj · · Score: 5, Informative

    See here. Developed by Steve Furber and his team at The University Of Manchester

    1. Re:Such a processor already exists by Anonymous Coward · · Score: 2, Interesting

      Yes, indeed they did. The article doesn't mention any collaboration between the teams, which seems strange because:

      1) ARM like to licence CPU core design IP, as mentioned in a later thread.

      2) One of the major upsides of asynchronous CPU design (said Prof. Furber on the Manc. Uni course) is that because the subcomponents of the CPU aren't nearly so tied to temperature, voltage and clock speed requirements (which directly affect flip-flop "set up" and "hold" time), the intellectual property invested in creating such a chip is far more reusable than any synchronous design.

      So if this is (as I infer from the article) a clean-room implementation separate to the AMULET group's work, it's totally contrary to the ARM licensing model and duplicates a lot of effort. Which seems a shame.

    2. Re:Such a processor already exists by Anonymous Coward · · Score: 0

      May I invest a .50 cal bullet in your personal intellectual property, if there is one.

      There is no such thing as intellectual property, you cannot "own" something that can be written down.

    3. Re:Such a processor already exists by YU+Nicks+NE+Way · · Score: 1

      Actually, the press release did mention the Amulet project -- it's also ARM-supported.

    4. Re:Such a processor already exists by kiniry · · Score: 1

      Actually, the first full-blown asynchronous microprocessor was developed at Caltech. See http://www.async.caltech.edu/ for more details. The company Fulcrum Microsystems spun out of this group (and my living room) to commercialize related technology.

      --
      Joseph R. Kiniry
      http://kind.ucd.ie/~kiniry/
      Lecturer
      UCD School of Computer Science and Informatics
  3. Intresting implications by luvirini · · Score: 3, Interesting

    If we see same thing applied to non ARM architectures, there a many strange things going to happen, as quite many things in current computers are based on the assumption that things have specific clock rates. Obviously things might get very intresting...

    1. Re:Intresting implications by pe1rxq · · Score: 2, Informative

      Usually with these kind of asynchronous cpus the communication with the outside world is made synchronous again. Just the inside of the processor is asynchronous. This is relativly easy since you only have to make sure that the asynchronous path is travelled faster than a clock cycle.
      The big advantage is that not every flipflop has to be active at every clock pulse and thus saves a lot of energy. Also the chip doesn't turn into a giant clock transmitter.

      Jeroen

      --
      Secure messaging: http://quickmsg.vreeken.net/
    2. Re:Intresting implications by fake_name · · Score: 1

      Provided the input/output interfaces of the CPU aren't changed the rest of the system won't care if the internal workings of the CPU are clocked, clockless, or performed by thousands of pixies using pen and paper. Clockless input/output lines would certainly make for some interesting design needs accross the entire device, but after a quick read of the arcticle I suspect the changes relate only to the inner workings of the chip.

    3. Re:Intresting implications by Anonymous Coward · · Score: 0

      The big advantage is that not every flipflop has to be active at every clock pulse and thus saves a lot of energy.

      This is already done with the cutting edge technolgy of 'clock gating'...

      Also, the logic doesn't have to be faster than a clock cycle. It just needs synchronization.

      Asynch. logic design seems to surface every couple of years - the main problem is usually a lack of CAD support. It might be different this time, though.

    4. Re:Intresting implications by fitten · · Score: 1

      There are tradeoffs with asynchronous design. One of the main arguments for asynchronous design was the DEC Alpha with 10% of its chip area devoted to a clock driver and transmission pathways. The other side of the coin is that asynchronous designs typically use a comparable amount of chip area for the logic required to control the circuit. It does tend to use less power though, as you say.

  4. way more elegant by fizze · · Score: 5, Informative

    the very first drafts of microprocessors were clockless.
    just with higher speed and hence, brute force, performance could be achieved easily.
    The problems which could not be solved back then were the obvious synchronisation issues. Setting up a common clock seemed the only way to resolve them.

    The idea behind clockless designs is less a "back-to-the-roots" idea, but more a step to gain the advantages of such a design, which are, amongst others:

    Reduced Power Consumption
    Higher Operation Speed

    Moreover, highly sophisticated compilers could tune program code to match a given performance/power ratio.

    Yet, I would not bet on clockless cores to become the new mainstream, by far not. Clockless cores will most likely be aimed at embedded design appliances, and low- and ultra-low-power applications.

    --
    Powerful is he who overpowers his temptations.
    1. Re:way more elegant by jimicus · · Score: 1

      Yet, I would not bet on clockless cores to become the new mainstream, by far not.

      Mainly because Intel's marketing has depended on clock speed for the last 20 years. I wouldn't be at all surprised to see some of the technology used in future generations of mainstream processors - low power consumption is a selling point when your electricity and air con bills are somewhere up in the stratosphere, particularly if it can still achieve reasonable performance. I don't see it replacing x86 or x86-64, but I could easily envisage the technology being used in a couple of x86-generations time. RISC technology did the same thing...

    2. Re:way more elegant by Anonymous Coward · · Score: 0

      The problems which could not be solved back then were the obvious synchronisation issues. Setting up a common clock seemed the only way to resolve them.

      That's the first thing I thought of. I'm no computer scientist or engineer, but it would seem to me that other things need to be called on like the motherboard, ram, the video card, and so forth, and they need to know when they're going to be doing what they're doing in order to be efficient.

      But I admit I'm talking out of my ass and can't think of any solid examples, so I could be horribly, horribly off base.

    3. Re:way more elegant by renoX · · Score: 4, Interesting

      Agreed that clockless cores have few chance to become mainstream, but still they have a better chance of being used now than before.

      Let me explain: before to reduce power consumption the "easy" thing was to use a process which created smaller transistor, but smaller doesn't means 'reduced power consumption' anymore..
      So clockless CPU becomes more interesting now.

    4. Re:way more elegant by Rattencremesuppe · · Score: 2, Insightful

      Yet, I would not bet on clockless cores to become the new mainstream, by far not. Clockless cores will most likely be aimed at embedded design appliances, and low- and ultra-low-power applications.

      I think that "embedded appliances" are even more "mainstream" than anything else, since there are far more embedded systems around than general-purpose PC workstations, servers, laptops etc altogether.

    5. Re:way more elegant by fizze · · Score: 1

      agreed, in terms of numbers.
      But its those GP-workstations etc. that an extensive bigger amount of money is being made with. ;)

      --
      Powerful is he who overpowers his temptations.
    6. Re:way more elegant by Short+Circuit · · Score: 1

      Modern CPUs frequently execute instructions out of order, where possible. Why not replace clock-based pipelines with clockless functional units, and allow the reorder buffer to put instructions back in the proper order.

    7. Re:way more elegant by Rattencremesuppe · · Score: 1

      But its those GP-workstations etc. that an extensive bigger amount of money is being made with.

      1) This statement is VERY questionable.
      2) This has nothing to do with "mainstream".

    8. Re:way more elegant by fizze · · Score: 1

      frequent ?
      well, it is a highly sophisticated approach to extend the usage ratio of the silicon. But speculative and out of orcer execution give a relatively slow performance gain, and depend on the compiled program.
      If the program itself makes good use of the silicon, such features are a waste of space.

      So much to that. Replacing such highly time critical units with more or less unpredictable (with reasonable effort) units, would greatly jeopardize functional correctness of a design.
      Out of order and speculative executions only can take place when its absolutely certain that the outcome remains unchanged, and it is difficult enough with predictable execution times.
      Besides, the whole pipeline issue is highly tricky when applied to asynchronous cores. While command A would need 5 times longer to decode than command B, simply because they are different, would mean that command B would "overtake" command A in the pipeline and thus change the execution order.
      In a way, this _is_ out of order. ;)

      --
      Powerful is he who overpowers his temptations.
    9. Re:way more elegant by HidingMyName · · Score: 1

      Ivan Sutherland discussed this topic in his Turing Award lecture (he called it Micropipelines) in 1989, using clock transitions to trigger state changes. One problem with high clock rates is that clocks are now so fast that they may not propagate to the entire chip in a single cycle. While I'm not sure that a purely clockless arcihtecture is at hand (since handshaking is not entirely free of cost), clocking could be used within regions on the chips (to reduce gate count and propagation distance) and clockless coordination could be used between regions.

    10. Re:way more elegant by sjames · · Score: 1

      Asynchronous is the right term, but is mis-leading. In this context, it means no clock to synchronize ops, it doesn't mean no barrier sync at all.

      The key to any out of order execution, asynchronous or clocked is that only independant instructions (or those where register renaming can make them independant) are allowed to pass each other. If B is dependant on A, it will simply not be dispatched at all until A retires. It will wait while C and D are dispatched.

      The whole idea behind hyperthreading is that two entirely seperate threads of execution help to avoid bubbles in the pipeline due to instruction dependancy.

    11. Re:way more elegant by sjames · · Score: 1

      and they need to know when they're going to be doing what they're doing in order to be efficient.

      Certainly now they are clock synchronized, but the only actual requirement is that dependant operations occur in order.

      As long as there is a reasonable upper bound on the time an instruction might take the processor need be no less efficient than a clocked CPU. Put another way, a clocked CPU simply makes sure that all instructions execute in the worst case time by holding the result in a latch until the clock ticks.

      The challenge is that on input, instead of just assuming that the clock pulse latched the input values, the inputs must handshake independantly and then signal when all of them have latched a value.

      This is a natural extension of recent developments where wide parallel busses are being replaced by several independantly clocked serial busses.

  5. Encouraging technology, but useful soon? by Dancin_Santa · · Score: 3, Interesting

    The benefit to today's high-functionality embedded operating systems like Linux, Symbian, iTron, and Windows CE is that they implement a preemptive task switching operating system. At any time, the clock interrupt may fire and the operating system will then queue up the next thread into the CPU.

    Nowadays, the whole CPU is not powered at any one time. If an instruction does not access certain parts of the chip, they are dark. Now this does not hold for some predictive processors which may be processing not-yet-accessed instructions, but in general if an instruction is not using some part of the chip, that part of the chip does not require juice.

    Taking out the clock and relying on the chip parts to fire and return means that each application in the system must return to the OS at some point to allow the OS a chance to queue up the next thread. Without the clock interrupt, the OS is at the mercy of the program, back to the bad old days of cooperative multitasking.

    The clock is what tells the OS that it is time to give a time slice to another thread. If we say "OK, well we'll just stick a clock in there to fire an interrupt every x microseconds," then what have we accomplished? We are back at square one with a CPU controlled by a clock. No gain.

    This kind of system would work in a dedicated embedded system which did not require a complex multitasking operating system. Industrial solutions for factories, car parts, HVACs, and other things that need reliability but don't really do that much feature-wise seem to be prime candidates for this technology. "Smart" devices? Not so much.

    1. Re:Encouraging technology, but useful soon? by Anonymous Coward · · Score: 0

      The timer that does an interrupt to the OS won't be dismissed it's only the workings of the cpu that won't be on an one instruction per cock basis.

    2. Re:Encouraging technology, but useful soon? by fizze · · Score: 4, Insightful

      Preemption is a "dirty hack" to achieve nice behaviour in a timely manner.
      For embedded systems where interrupt latency is the primary aspect, other approaches have to be found. also, if the CPU checks after every x instructions if there is an interrupt to process, you get a margin of the timely behaviour.
      I am no embedded / safety critical developer, but I know that the fastest response times on interrupts and worst-case response times vary greatly depending solely on the (RT)OS used.

      --
      Powerful is he who overpowers his temptations.
    3. Re:Encouraging technology, but useful soon? by Anonymous Coward · · Score: 5, Informative

      I think you are getting clock confused with ticker interrupt. A CPU clock is typically measured in nanoseconds. A ticker interrupt is typically measured in milliseconds. A clockless core will still need to field interrupts (for I/O) and very well can still field a ticker interrupt. -cdh

    4. Re:Encouraging technology, but useful soon? by CaptainAlbert · · Score: 5, Informative

      You appear to be confusing the CPU's clock with a real-time clock interrupt. They are fundamentally not the same thing.

      The clock being dispensed with is the one that causes the registers inside the CPU to latch the new values that have been computed for them. At 3GHz, this happens every 333ps. The reason this clock exists is basically because it makes everything in a digital system much, much easier to think about, design, simulate, manufacture, test and re-use. But, it's not an absolute requirement that it be present, if you're clever. (Too clever by half, in fact.)

      The other clock, which you were referring to, fires off an interrupt with a period on the order of milliseconds, to facilitate time-slicing. If your application requires such a feature, you can have one, regardless of whether your CPU is synchronous or asynchronous internally. It's a completely separate issue.

      --
      These sigs are more interesting tha
    5. Re:Encouraging technology, but useful soon? by makapuf · · Score: 1
      We are back at square one with a CPU controlled by a clock. No gain.

      Except said "clock" is one million times slower if we speak millisecond-wide granularity (HZ in the kernel is, what, 1024 now ?), and a lot of asynchronous processing can happen between task switching.
    6. Re:Encouraging technology, but useful soon? by KiloByte · · Score: 3, Informative

      We're talking about two different types of clocks:

      • a timing source needed to preempt a long-running task
      • the heart-beat that dictates when the CPU is going to do the next instruction.
      These two are completely different things. The former can have a pretty low resolution as well -- but is needed for other tasks as well. Any non-degenerate processor will need some kind of timing source, but there is no reason why it would be connected to the number of instructions executed.

      In a multitasking operating system, there are three reasons that can trigger a preemption:

      • a hardware interrupt
        Some outside even has happened. A new bit/byte came in from a serial source, an IO tranfer ended, etc, etc.
      • resource needed
        The process requires some resource that is either held by another process or will require an IO.
      • the time-slice has expired
        A timer interrupt is needed for this, but nothing bad will happen if the resolution is many orders of magnitude bigger than the CPU core clock would be. You don't preempt processes every a handful of CPU cycles, do you?
      --
      The creatures outside looked from Alt-Right to Antifa; but already it was impossible to say which was which.
  6. I am amazed at how stupid you are by Anonymous Coward · · Score: 0, Troll

    "Taking out the clock and relying on the chip parts to fire and return means that each application in the system must return to the OS at some point to allow the OS a chance to queue up the next thread. Without the clock interrupt, the OS is at the mercy of the program, back to the bad old days of cooperative multitasking."

    They will include a clock interrupt, you retard. They just mean the CPU core itself isn't clocked.

    1. Re:I am amazed at how stupid you are by Anonymous Coward · · Score: 0

      Agreed. Its clueless drivel.

    2. Re:I am amazed at how stupid you are by Anonymous Coward · · Score: 0

      or a clever troll?

  7. Quite impressive... by Goalie_Ca · · Score: 2, Interesting

    The complexity of souch a core must be astounding. For all you non-ee's out there, a chip is full of little memory cells called flip-flops. At the end of each circuit rests a flip-flop in which normally the rising edge of the clock stores the results of that circuit so it pass that data on and start new stuff without loosing it. Everythig is synchronized to the clock. This is definently over-simplified but that's essentially why a circuit has a clock.

    To eliminate clocks you would new circuitry such arbitrers and some sort of completion logic which could be used to trigger a flip-flop. To break a slashdot law, i haven't done any reading on any modern techniques so would some one enlighten me on some design issues involving simple tasks such as accessing a register file, or making a memory read. Surely a bus would still maintain a clock.

    --

    ----
    Go canucks, habs, and sens!
    1. Re:Quite impressive... by Anonymous Coward · · Score: 1, Funny
      For all you non-ee's out there, a chip is full of little memory cells called flip-flops.

      Hey, go Philips! Go ARM! I'd love to get John Kerry removed from my chips...

    2. Re:Quite impressive... by destiny_uk · · Score: 1

      The team at Manchester have also developed an Async bus to link Synchronous IP blocks with different timing constraints together on a single chip more easily. If you want to know more about this you can attend CS3212 Asynchronous System Design at Manchester University. I did last year, and it was pretty hard :)

    3. Re:Quite impressive... by rahard · · Score: 2, Interesting
      To eliminate clocks you would new circuitry such arbitrers and some sort of completion logic which could be used to trigger a flip-flop.... enlighten me on some design issues involving simple tasks such as accessing a register file, or making a memory read.

      if you remember your digital design, there's an asynchronous counter. basically, it involves handshaking just like handshaking in a protocol level but at a lower level. yes, there's arbiter, muller c-element (rendezvous), and other nifty components.

      the most novel approach, IMHO, would be ivan sutherland's micropipeline which could be extended into Counterflow Pipeline Processor (CfPP). Here is his Turing Award paper on micropipelines. (very good and readable paper!)

      Other keywords include "self-timed". I believe there's somebody @ SFU Computer Science who did asynchronous design. I forgot the name. (sigh)

    4. Re:Quite impressive... by Anonymous Coward · · Score: 1, Informative

      Philips previously released an asynchronous processor - it was used in pagers and reportedly resulted in 75% longer battery life (I forget the processor number).

      One of the problems with asynchronous circuits is that they are more likely to experience single event upsets (seu's) from glitches in the circuit. These can result in unpredictable behavior - not something you want in your processor. One of the benefits to a _synchronous_ design is that you only have to be concerned that your logic levels are correct during clock edges which is a very small percentage of the time. Your logic can be bouncing all over the place before and after a clock edge but as long as its stable when the clock rises, your circuit behaves as expected. Not so with asynchronous logic - any glitch on a line can start up an unintended computation with potentially disastrous effects.

      One technique that designers use to combat this problem is triple modular redundancy (tmr) which is essentially a majority rules (2 out of 3) circuit. Naturally, this increases the amount of logic in the design which can counter some of the benefits of asynchronous design. Hopefully they've been able to solve some of the problems with asynchronous techniques.

    5. Re:Quite impressive... by drmerope · · Score: 2, Informative

      Since you expressed a particular interest in register files, here is a recent publication:

      David Fang and Rajit Manohar. Non-Uniform Access Asynchronous Register Files. Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems, April 2004.
      http://vlsi.cornell.edu/~rajit/ps/reg.pdf

      The fastest/lowest energy asynchronous circuits do not use clocks for anything. Moreover, very few arbiters are used in practice. The "completion logic" of course is always the hard part, but about 10 years ago, something called "pipelined completion was developed" which alleviates that bottleneck.

      For how arbiters are used and avoided:
      Precise Exceptions and Interrupts in Asynchronous Processors. Rajit Manohar, Mika Nystrröm, and Alain J. Martin. Proc. 21th Conference on Advanced Research in VLSI, IEEE Computer Society Press, March 2001.
      Crossing the Synchronous-Asynchronous Divide. Mika Nyström and Alain J. Martin. Workshop on Complexity-Effective Design, 2002

    6. Re:Quite impressive... by The+Conductor · · Score: 1
      AFAIK, there are basically two ways to implement clockless designs. The simplest, in principle, is to keep track of min/max propagation delays and make sure that everything is guaranteed to settle out without any race hazards. It is a huge bookeeping job for non-trivial designs so this approach doesn't scale very well. That's why people started putting flip-flops and clocks in, to keep the combinatorial stages separated.

      It is also possible, though, to make fundamental mode logic. If you feed outputs back to inputs in your combinatorial logic, you can force the outputs to cascade through certain states as the inputs change. This is much harder to analyze: the technique I learned was to draw arrows on K-maps and the most complex thing I could analyze was a circuit to detect which direction a mouse ball moved based on the phase relation of the optointerrupter signals.

      It looks like these new microprocessor designs are using fundamental mode logic. I have no idea how they analyze (let alone synthesize) their designs, but it definitely isn't K-maps, that would be flippin' impossible!

    7. Re:Quite impressive... by smitten0000 · · Score: 1

      One of the benefits to a _synchronous_ design is that you only have to be concerned that your logic levels are correct during clock edges which is a very small percentage of the time. Your logic can be bouncing all over the place before and after a clock edge

      Not to nitpick, but don't forget about hold times after the rising edge of the clock pulse. I took introductory digital design last year, and IIRC these are significant so that you don't skip through several states in a moore/mealy state machine in a single clock cycle.

      --
      /. sig.
  8. article text by DonaldDuckBigO · · Score: 0

    EINDHOVEN, THE NETHERLANDS AND CAMBRIDGE, UK, -Oct. 27, 2004 - Handshake Solutions, a Royal Philips Electronics line of business, and ARM [(LSE: ARM); (Nasdaq: ARMHY)], today announced the joint development and marketing of an ARM® processor using Handshake Solutions' unique low-power, self-timed technology. The partnership provides Handshake Solutions with a license to develop the breakthrough implementation using their unique design flow and methodology. The ARM processor will utilize Handshake Solutions' Handshake Technology, which is the industry's first production proven methodology for using self-timed circuitry in commercial applications. Handshake Technology has been used for more than five years in tens of millions of products including smart cards, advanced pagers, In-Vehicle Network transceivers, and cordless handsets. The compact asynchronous ARM processor will be particularly useful in the smart card, consumer electronics, and automotive markets because of its very low-power consumption and low Electro Magnetic Interference (EMI). "Handshake Solution's technology has already been successfully implemented in millions of ICs available in the market today," said Wouter Van Roost, chief executive officer, Handshake Solutions. "Applying Handshake Technology to the industry-leading ARM architecture will result in a new type of ultra low-power processor, enabling new classes of application." "ARM has always been the low-power leader in embedded microprocessors," said Mike Inglis, executive vice president, Marketing, ARM. "Our partnership with Handshake Solutions will enable new ultra-low power applications in the smart card, consumer electronics, and automotive markets, while preserving the easy integration common to all ARM processors." This new ARM processor is compliant with the ARMv5TE architecture and optimized for use in both synchronous and asynchronous system-on-chip designs, permitting easy integration by semiconductor makers. The key benefits of the processor include low Electro Magnetic emission, reducing the probability of interfering with sensitive circuitry, and low peak currents, reducing system power requirements. Because asynchronous processors consume zero dynamic power when there is no activity, they can significantly extend battery life. ARM has long recognised the potential of asynchronous design and has supported the Amulet® project led by Professor Steve Furber at Manchester University. Availability and Tool Support The new ARM processor will be available as a licensable core from ARM in Q1 2005. It will be supported by Handshake Solutions' advanced design tools and methodology that enables customers to design a complete or partially asynchronous chip. More information on Handshake Solutions can be found at www.handshakesolutions.com. About Royal Philips Electronics Royal Philips Electronics of the Netherlands (NYSE: PHG, AEX: PHI) is one of the world's biggest electronics companies and Europe's largest, with sales of EUR 29 billion in 2003. With activities in the three interlocking domains of healthcare, lifestyle and technology and 166,800 employees in more than 60 countries, it has market leadership positions in medical diagnostic imaging and patient monitoring, color television sets, electric shavers, lighting and silicon system solutions. News from Philips is located at www.philips.com/newscenter. About ARM ARM designs the technology that lies at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM's 16/32-bit RISC microprocessors, data engines, peripherals, software and tools, combined with the company's broad Partner community, provide a total system solution that offers a fast, reliable path to market for leading electronics companies. More information on ARM is available at http://www.arm.com.

  9. Not relevent by r6144 · · Score: 5, Informative
    As far as I know, Linux and many other operation systems already use an external chip (the 8254 on the PC) for most timing tasks, including preemptive multitasking. For ultra-high precision timing, the CPU clock (the time stamp counter on an IA32 cpu) is used, but they are not all that essential. Last time I heard, since CPU frequencies can change by power management functions on some P4s, they are a bit tricky to use correctly for timing, so they are not used when not absolutely needed.

    As for the power problem, all parts of the CPU is powered, except that gates that aren't switching consume less power (mostly leakage, which seems to be quite significant now). In synchronous circuits, at least the gates connected directly to the clock signal switch all the time, while in asynchronous circuits unused parts of the CPU can avoid switching altogether, so some power may be saved, but I don't know how much it will be.

    1. Re:Not relevent by Scarblac · · Score: 2, Informative

      You didn't understand what this is about. It's not about timing.

      You talk about "CPU frequencies". What is that? That's the frequency of the CPU clock signal. It runs everything inside the CPU - at every 'tick' of the clock, instructions move through the CPU, registers are updated, etc. This is about CPUs that don't use a clock signal at all, different things happening aren't synchronous. These CPUs don't have a frequency.

      (Probably wrong also, I don't have the time to express myself more clearly - just wanted to point out that what chip to use to keep track of time is completely besides the point)

      --
      I believe posters are recognized by their sig. So I made one.
    2. Re:Not relevent by r6144 · · Score: 1

      I mean that current applications on current synchronous chips use external clock chips for the most part, but the CPU's own 3GHz clock is also used occasionally. Since it is not used all that often (definitely not needed for preemptive multitasking), applications that really need to use them currently can still use a high-frequency external clock chip instead when they are ported to these async CPUs.

    3. Re:Not relevent by jovlinger · · Score: 1

      I seem to recall ntp docs pointing out that the software clock (ie increment time counter by 0.0x secods every tick) is order of magnitudes more accurate than the cheapo motherboard rtc. IIRC, the RTC loses several seconds per year.

  10. Philips growing into a Major R&D company by pagal_paanda · · Score: 1

    To me it feels like that Philips is turning into a major R&D company that could one day topple IBM. Looking at their recent expension in Bangalore, no one would disagree. Maybe, a good thing to keep the fire burning under IBM.

    1. Re:Philips growing into a Major R&D company by dtmos · · Score: 3, Interesting

      Philips has been a world-class R&D company for a long time. Philips Research was established in 1914, and has contributed much, from the invention of the pentode vacuum tube (valve) by Tellegen in 1929 to the audio cassette in the 1960s and their more modern work developing CDs and DVDs.

      The fire has been lit under IBM and other corporate research organizations for a long time.

  11. Re:Intel WAS first by Anonymous Coward · · Score: 0, Interesting

    In English, Intel is not singular. It is a composite entity, made up of many people, and as such should be considered plural when choosing the verb conjugation. Many Americans make this mistake.

  12. ARM Business Model by joelethan · · Score: 3, Interesting
    I'm interested becasuse ARM's business model usually involves licensing their chip designs. ARM cpus are widespread in cell phones etc. They have their own market and application area away from Wintel, PowerPC etc.

    Also, anything that might boost my pitiful ARM shares value is most welcome! Why?... Why did I believe the hype?

    /joelethan

  13. ENIAC was first by chris_sawtell · · Score: 4, Funny

    I hope they don't try to patent this.
    Refer to 1944 for prior art.

    1. Re:ENIAC was first by fake_name · · Score: 1

      They may have a legitmate patent if they have designed some gee-whiz new way to build asyncronous circuits that isn't hideously complicated. I did some circuit design while studying electrical engineering at uni and syncronous is vastly easier to werk with, even at the small scales we were working on with only a dozen components.

    2. Re:ENIAC was first by rahard · · Score: 1
      I hope they don't try to patent this.

      you know, it's not a laughing matter.
      some of the ideas on this have been patented.
      try google with "micropipelines patent". you'll find plenty of them.

    3. Re:ENIAC was first by cakoose · · Score: 1
      I hope they don't try to patent this.

      I can guarantee that they have.

  14. Re:Intel WAS first by ThJ · · Score: 1

    That sounds self-contradictive.

    "Intel are a big corporation."

    How can it be "are" if it is "a corporation"?

  15. More efficient by ThJ · · Score: 1

    See my reply to the parent for a more efficient demonstration of this. ;)

  16. Self-contradictions by ThJ · · Score: 1

    "A team are working hard" still sounds self-contradictive...

    1. Re:Self-contradictions by Anonymous Coward · · Score: 0

      You're probably American; American English is a specific dialect, with many differences to English. My main point was not that the grammar Nazi was wrong for all English dialects, merely that he was wrong to say that "British and Australian English speakers" are wrong. Within their respective dialects, they are right; it happens that American resolves the complexities of collective nouns and composite entities in favour of treating them as singular nouns, rather than plural.

    2. Re:Self-contradictions by ThJ · · Score: 1

      As a matter of fact, I'm not a native speaker of English at all. I just happen to be proficient enough in the language to feel confident in debating issues like these. ;) I would categorize my spoken English as leaning towards Brish English. My written English is American English; probably with occational glitches.

    3. Re:Self-contradictions by ThJ · · Score: 1

      Glitches; like typing "Brish" instead of "British".

    4. Re:Self-contradictions by Anonymous Coward · · Score: 0

      Could someone mod this loser down a million points? This is not a discussion about grammar.

  17. Re:Intel WAS first by Anonymous Coward · · Score: 0

    Because corporation is a collective noun. Collective nouns are singular when talking about the collective as part of a group of similar entities, and plural when talking about one collective. Hence "that is a large flock of geese", since you are comparing flocks of geese, but "Bob's flock are a large flock of geese".

  18. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    Ok, I don't know what planet you're living on, but I have never seen, heard or smelt the sentence - Your team are working hard. I think you've been playing a bit too much Zero Wing. All your team are belong to us!

  19. Irregular distinction by ThJ · · Score: 1

    That's a rather irregular distinction if it is in fact made.

    1. Re:Irregular distinction by Anonymous Coward · · Score: 0

      I think he just made that up.

  20. Re:Let's take a non-human group by ThJ · · Score: 1

    Let us use Google to decide: Double-quoted search term "Intel are" gives 27,900 hits. Double-quoted search term "Intel is" gives 344,000 hits...

  21. Re:Intel WAS first by Anonymous Coward · · Score: 2, Funny

    Ummm considering that British English is the Original English, I think those speakers can make that "mistake" as many fucking times as they want. Now STFU and go choke on a freedom fry, you (obviously) American prick.

  22. Re:Let's take a non-human group by Anonymous Coward · · Score: 0
    I'm living on a part of planet Earth where American English is a foreign dialect; in my part of this planet, you are wrong, and I am right.

    In terms of the Internet as a whole, we are both right, since we are speaking different yet compatible dialects.

    As a computer analogy, ISO C99 and GCC G89 are different dialects; by and large, they are compatible, and code written for one is correct in the other; there are subtle differences, and you cannot say that either side is completely wrong in all cases.

  23. Benchmarking Nighmare ahead :) by imsabbel · · Score: 1

    Well, a very cool (?) implication of this technology would be that chip performance would be depending of the, well, performance of the die used and the enviroment. So increasing voltage and decreasing die-temperature would make to chip faster automatically...
    (i can see the "the xxx-chip would have won against the yyy-chip if they had used a bigger HSF" flames comming...)

    --
    HI O WISE PRINCE. WHT TOOK U SO DAM LONG?
    1. Re:Benchmarking Nighmare ahead :) by whatsup_will · · Score: 1

      then the new benchmark, would need to have its proccess run exactly the same each time to give best idea from one run on each benchmark, otherwise to benchmark, you would need to run it 5+ times and average the score.

  24. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    Team != Intel. Furthermore, Intel is also a Proper Noun, and that means saying "intel is" is perefectly correct. I don't know what the fucking official rules of English say. But it is obvious that Your team are working hard, is just wrong English plain and simple. Geez Americans trying to teach the world English lessons. What next? Will they teach us how look for Weapons of Mass Destruction as well? Or how to decide an election result when votes don't get counted due to cheating in Florida? Somebody please mod everybody to blivion so we can end this destructive conflict

  25. Re:Let's take a non-human group by ThJ · · Score: 1

    If the AC by some fat chance is right in his handling of 'composite entities', it must practically be dead in modern English, with a mere 8% of the Internet using it.

  26. Re:Let's take a non-human group by ThJ · · Score: 1

    Wether it is a proper noun or not is only of relevance *if* the status of a 'composite entity' warrants a change to a grammatical plural. I think it does not, neither for "Intel" nor "team".

  27. standardised implemenation. by Anonymous Coward · · Score: 2, Interesting

    When I was at university we studied standard ways to overcome these problems down to gate and transistor level. The impression i was given that its not that hard. Some of the standard ways include doing a calculation twice and waiting for the results to be the same. Of coarse there are no tools to do it in automated fashion that i am aware of like synchronous design. Here the tools are extensive from vhdl to handel C implenentation. Even dynamic logic can be synthesised automatically now. This means its to risky for asic design houses to implement on there own as they would have to do there own custom blocks. This also presents a design flow problem. How would a foundry verify the design for you. In the case of synchronous design the methodology is well established.

    my 2 cents..

    1. Re:standardised implemenation. by bestguruever · · Score: 1

      check out Theseus Logic. They have a process using m-of-n gates with hysteresis which works with existing (or slightly modified ) vhdl tools.

      --
      if you think this is bad, you should have seen my last sig
  28. Re:Intel WAS first by Anonymous Coward · · Score: 1, Insightful

    That's a brit vs. us english difference. The brits think of a collection as a plurality of parts, at least in some contexts as alluded to below, while us english normally treats a collection as a singular entity of its own, regardless of context. Who care... it adds color to the language. :-)

  29. Re:Let's take a non-human group by ThJ · · Score: 1

    More "evidence"... Google gives 5,880,000 results for "team is", but only 1,250,000 results for "team are". That's a ratio of 4.7 to 1.

  30. Re:Intel WAS first by ThJ · · Score: 0

    Okay. I declare that Brits are strange in so unevenly bringing a practical distinction into their grammar.

    This wouldn't by any chance be the same mechanism that is at work in "People are..." sentence constructs?

  31. Commodore/Amiga had ASYNC expansion bus by gilesjuk · · Score: 1

    The Amiga's Zorro expansion bus was asyncronous back in the 1980s.

    Ok, wasn't a processor and one of the chips that drove it was clocked, but it goes to show you how clever the designers of that system were.

    1. Re:Commodore/Amiga had ASYNC expansion bus by Anonymous Coward · · Score: 0

      asynchronous buses are very common unlike processor cores. pretty much everything pre sdram was async for memory as far as im aware. I think vme was too(someone correct me if im wrong i havnt had much to do with it) and most 8/16/32bit micros have async busses. So i dont think you can give anything to the amiga dudes for that one.

    2. Re:Commodore/Amiga had ASYNC expansion bus by Anonymous Coward · · Score: 0

      Both of you are mixing up "clockless" and "asynchronous". Heck, setting a 4:3 (266:200) RAM clock in your BIOS means you went async, BFD...

  32. no way - by Anonymous Coward · · Score: 1, Funny

    ARM? Handshaking? They're having a laugh...

    1. Re:no way - by Anonymous Coward · · Score: 0

      Now they just need to get rid of this damned organlegging problem.

  33. Idea has been around for 30 years by gtoomey · · Score: 2, Informative

    These asyncronous computers are implementations of data flow computers.
    The problem is that the first implementations were very slow.

  34. Re:Intel WAS first by Anonymous Coward · · Score: 0

    When was English grammar ever thought to be fucking simple? It's only been bastardised (with an 's') by dumb americans that wouldn't be able to get their fat heads around a subtlety if it hit them in their fat, dumb faces.

  35. People are? by Anonymous Coward · · Score: 0

    People are killing themselves over this comment!

  36. Re:Intel WAS first by Anonymous Coward · · Score: 0

    no, you stupid yanks mutilated the English language without changing its name to "american".

  37. Re: by Anonymous Coward · · Score: 0

    No it isn't, a corporation is a single person, at least in the US. I can't find the case, but according to the supreme court, a corporation is legally a person just like you are. There is no collective about it, a corporation is a single person not a group.

  38. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    No kidding, genius. UK population is somewhere between one fifth and one sixth that of the US. So, 4.7:1 would be an entirely consistent result. Incidentally, there is no such thing as "American English". English is the language spoken by the English by defintion (including all its subcultures). Thus the language spoken by the population of the USA must be US American.

  39. I had an idea once by ajs318 · · Score: 4, Informative

    The reason why a clock is commonly used in microprocessor circuits is to try to synchronise everything, because different logic elements take a different amount of time for the outputs to reach a stable state after the inputs change. This is known as "propagation delay" and is what ultimately limits the speed of a processor. With CMOS, you can actually reduce the propagation delay a little by increasing the supply voltage, but then your processor will be dissipating more power. {CMOS logic gates dissipate the most power when they are actually changing state, and almost no power at all while stable, whether they are sitting at 1 or 0. This is in contrast to TTL, which usually dissipates more power in a 0 state than in a 1 state, but there are some oddball devices that are the other way around}.

    The clock is run at a speed that allows for the slowest propagation, with data being transferred in or out of the processor only on the rising or falling edges. This allows time for everything to get stable. It's also horrendously inefficient because propagation delays are actually variable, not fixed.

    If you wire an odd number of NOT gates in series, you end up with an oscillator whose period is twice the sum of the propagation delays of all the gates. If you replace one of the NOT gates with a NAND or NOR gate, then you can stop or start the oscillator at will. Furthermore, by extra-cunning use of NAND/NOR and EOR gates, you can lengthen or shorten the delay in steps of a few gates. Obviously at least one of the gates should have a Schmitt trigger input to keep the edges nice and sharp; but that's just details.

    My idea was to scatter a bunch of NOT gates throughout the core of a processor, so as to get a propagation delay through the chain that is just longer than the slowest bit of logic. Any thermal effects that slow down or speed up the propagation will affect these gates as much as the processing logic. Now you use these NOT gates as the clock oscillator. If you want to try being clever, you could even include the ability to shorten the delay if you were not using certain "slow" sections such as the adder. This information would be available on an instruction-by-instruction basis, from the order field of the instruction word. The net result of all this fancy gatey trickery is that if the processor slows down, the clock slows down with it. It never gets too fast for the rest of the processor to keep up with. Most I/O operations can be buffered, using latches as a sort of electronic Oldham coupling; one end presents the data as it comes, the other takes it when it's ready to deal with it, and as long as the misalignment is not too great, it will work. For seriously time-critical I/O operations that can't be buffered, you can just stop the clock momentarily.

    The longer I think about this, the deeper I regret abandoning it.

    --
    Je fume. Tu fumes. Nous fûmes!
    1. Re:I had an idea once by Anonymous Coward · · Score: 1, Insightful

      two words: process variation.

    2. Re:I had an idea once by ajs318 · · Score: 2, Interesting

      That's another reason to scatter the delaying gates throughout the core, and use enough of them. You have to hope that you don't get too many instances of a logic element and one of its associated delaying gates falling on the opposite sides of a process variation boundary. Especially where the effects favour faster propagation in the delaying gate. So, my intention was to aim for the clock delay being slightly but definitely longer than, and not exactly equal to, the logic delay. It would still respond to dynamic effects like temperature better than an external clock oscillator.

      This would also be one of those kinds of circuits that, if it's not built on the same silicon substrate, won't work at all. Power op-amps are another good example: they rely on better thermal coupling than you can achieve with discrete components, and better properties-matching than you can achieve by just pulling transistors out of a bag at random without doing any tests on them. {You can't control the absolute values of most on-chip components precisely, but you can be fairly sure of the relative similarities between them}. Build one out of carefully-gain-matched transistors exactly according to the schematic in the data book, and it might just about work if you put it in a constant-temperature oven. In the best case it will distort like hell, and in the worst case it will go literally into meltdown.

      --
      Je fume. Tu fumes. Nous fûmes!
    3. Re:I had an idea once by chrysrobyn · · Score: 4, Informative

      My idea was to scatter a bunch of NOT gates throughout the core of a processor, so as to get a propagation delay through the chain that is just longer than the slowest bit of logic.

      I assume that you hope to use your self timed logic (as it's known in the industry) to avoid all the problems associated with clocked logic and provide an easy to use asynchronous solution. Please do not forget manufacturing tolerances and that you have to make your self-timed logic 99.99999% certain slower than the slowest asynchronous path. This means that you have to qualify your entire logic library with a specific technology, then guardband it to make sure that when manufacturing shifts due to reasons you cannot explain, your chip still works. For this reason, in my experience, self timed logic has been slower than clocked logic for nominal cases and much slower in fast cases (in special cases, better than breaking even in slow process conditions).

      Self-timed logic of the kind you describe would likely still end up with latches to capture the result / launch into the next self-timed logic block. In this case, you're still paying the latch cycle time penalty for clocking your pipeline. You're still burning the power associated with the clock tree (although you are gating your clocks to only the active logic, known as "clock gating", an accepted practice), and you're additionally burning the power for each oscillator, which I suggest would likely be more than the local clock buffers in a traditional centrally PLL clocked chip.

      An ideal asynchronous chip would be able to not use latches to launch / capture and still be able to keep multiple instructions in flight -- using race conditions for good and not evil. This would involve a great deal of work beyond simply using inverters and schmitt triggers. This is a larger architecture question requiring a team of PhDs and people with equivalent professional experience.

    4. Re:I had an idea once by Anonymous Coward · · Score: 1, Insightful

      ok, one more word - area.

    5. Re:I had an idea once by TonyJohn · · Score: 2, Interesting
      You stated that the clock period (and therefore the length of the ring oscillator) should be about the same length as the critical path through the design. This is likely to be significantly less than 50 gates, and therefore your oscillator will only have 25 inverters. In a design with a million gates or more, this is not really enough to monitor the process and temperature variation across the die (which is surprisingly significant). If you could get enough gates into the ring (use NAND gates?), then they will start consuming significant area, and therefore slow the chip down.

      The idea is good and the physics is sound, but putting something like this into practice is much harder than you make out. Speed binning of chips goes part way to adjusting for process variation. Sophisticated chips have temperature monitors that will scale back the clock when things get too hot (but in a crude, broad-brush way). ARM is already working on more fine-grained closed-loop systems (see here), but as a way of saving power rather than going faster, and with an indirect link between chip speed and clock.

      --
      Owl tried to think of something wise to say, but couldn't.
    6. Re:I had an idea once by phsdv · · Score: 1
      Please do not forget manufacturing tolerances and that you have to make your self-timed logic 99.99999% certain slower than the slowest asynchronous path. This means that you have to qualify your entire logic library with a specific technology, then guardband it to make sure that when manufacturing shifts due to reasons you cannot explain, your chip still works

      Does this not depend HOW you implement your selftimed logic? Do you, by any change, know how Philips did implement this?

      Besides that, for most ARM applications it is not the raw power that count most. It is the power consumption, which will be much lower for the same number of MIPS (no, not the other core, but the million instr. per seconds). Which will increase your battery life time on your next phone, PDA, MP3 player etc.

    7. Re:I had an idea once by chrysrobyn · · Score: 1

      Does this not depend HOW you implement your selftimed logic? Do you, by any change, know how Philips did implement this?

      There are several ways to implement self-timed logic in general and asynchronous architectures as well. I don't claim to know how Philips did this. My points were not meant to be insurmountable, just a statement about how one specific poster's ideas were difficult to implement and just the tip of the iceburg.

      I was responding to my parent post, which stated:

      If you wire an odd number of NOT gates in series, you end up with an oscillator whose period is twice the sum of the propagation delays of all the gates. If you replace one of the NOT gates with a NAND or NOR gate, then you can stop or start the oscillator at will. Furthermore, by extra-cunning use of NAND/NOR and EOR gates, you can lengthen or shorten the delay in steps of a few gates. Obviously at least one of the gates should have a Schmitt trigger input to keep the edges nice and sharp; but that's just details.

      I don't think anybody in their right mind would implement an entire chip using this specific embodiment. I don't know, but I doubt Philips did either. My post was a discussion of this idea presented by its parent and should not be interpreted to have a bearing on what Philips is doing. There are a lot of ways to implement asynchronous processors.

  40. Re: by Anonymous Coward · · Score: 0

    While a corporation MAY, LEGALLY be considerd as a single person (in the USA), it is not ACTUALLY a single person. In the real world (and as originally intended) any company or corporation is a group of people working towards a common goal.

  41. Way Back When by opos · · Score: 5, Interesting

    A long long time ago (1970s) Charlie Molnar, designer of the Linc tape (the Linc computer was an NIH funded (late 1960s) minicomputer that evolved into the PDP 8 and pushed DEC into the minicompuer business) explored asynchronous computing. Along the way they discovered synchronizer failure - i.e. the inability to reliably synchronize asyncronous subsystems - see Chaney, T.J. and Molnar, C.E. 1973. Anomalous behavior of synchronizer and arbiter circuits. IEEE Trans. Comp. pages 421-422. The bottom line is that it is physically impossible to guarantee that the data setup requirements (the minimum time the data must be asserted before it can be reliably clocked into the flip flop) of a flip flop can be met when the clock is asserted by one async component and the data are asserted by another async component. To my knowledge, this fundamental limitation has never been overcome.

    1. Re:Way Back When by BarryNorton · · Score: 2, Interesting

      A good review, as well as the state of the art, afaik, in showing how much we can formally say about what can be achieved practically is Ian Mitchell's MSc thesis (1996, British Columbia) 'Proving Newtonian Arbiters Correct, Almost Surely' (which is an answer to Mendler and Stroup's 'Newtonian Arbiters Cannot Be Proven Correct', paper versions of both being available from the proceedings of Designing Correct Circuits, in 1992 and 1996)

    2. Re:Way Back When by phoenix321 · · Score: 1

      Not sure if that applies, but isn't the whole internet essentially a very large asynchronous switched circuit? Data transfer is still reliable given the right protocols. Even if it is outside reasonable thought to implement a multiprocessor-interconnect over, say, TCP/IP because of latency and bandwidth issues, I think it's not fundamentally impossible to do. I would see SETI@home and United Devices as a kind of asynchronous processing system with very different timings. Bus throughput may be measured in kilobytes, latency in hours and task/context-switching in days - but an asynchronous system nonetheless.

      So either asynchronous components add a huge overhead in synchronization efforts, (sync) error correction and buffering, but is not impossible or I didn't understood what you wrote. ;)

  42. True, but look to the PC world by gilesjuk · · Score: 1

    The PC competition at the time was all stuff like 8Mhz buses. Even PCI has a clock speed, it means redesigning ICs all the time to cope with faster clock speeds.

  43. Re: by Anonymous Coward · · Score: 1, Informative

    No it isn't, a corporation is a single person, at least in the US.

    Which is exactly the point. A corporation is only considered a single entity in the United States of America because there is a legal basis for treating corporations as a real person. In the rest of the world a corporation is a distinct legal entity and thus is not treated as a single entity. A corporation is composed of many people, hence it is a collective noun.

  44. Interesting... by dkf · · Score: 4, Interesting

    It looks like Philips (through their tame spin-off Handshake Solutions) are letting the world see Tangram again (or something very like it.) Back in around 1994/1995 the Amulet team (already mentioned accurately by others) were looking into using the Tangram language to develop their asynchronous microprocessor technology - it was a fairly neat solution that did most of the things we wanted, though there were a few things it was crap at at the time - but then Philips decided to cut us off. It would be entirely fair to say that this was very annoying! Now it looks like they're letting the cat get its whiskers out of the bag again.

    FWIW, ARM have probably known (at least informally and at a level not much deeper than your average slashdot article) a large fraction of what Philips have been up to in this area for at least a decade.

    --
    "Little does he know, but there is no 'I' in 'Idiot'!"
  45. Re:Let's take a non-human group by ynohoo · · Score: 1

    I'm sick of hearing about "single-quote" and "double-quote". One is an "apostrophe", the other is a "quote". I can only assume that the originators of computer languages which use apostrophes as quotes were illiterate.

  46. speeds by zxflash · · Score: 1

    chip manufacturers have been so eager to take the focus off the clock speed (amd+intel using new "model numbers") this type of thing injects thats much more logic into their reasoning if they start to embrace this type of approach... things like cache size and performance benchmarks may eventually be significantly more imporatnt even from a marketing perspectave that how many ghz you can cram into a chip without having it melt through the socket it's embedded in...

    --

    All the torrents you could want.
  47. The WIZ Processor by MarcoPon · · Score: 4, Interesting
    Take a look at The WIZ Processor, by Steve Bush.
    It's a drastic departure from common CPUs. Definitely intresting.

    Bye!

    --

    SeqBox
    1. Re:The WIZ Processor by phoenix321 · · Score: 1

      Pretty interesting stuff, I wish I had mod points.

    2. Re:The WIZ Processor by Anonymous Coward · · Score: 0

      I'm steve bush, and I endorse this processor.

    3. Re:The WIZ Processor by MarcoPon · · Score: 2, Interesting
      Also this thread on MASM forum could be of interest. It was started by Steve Bush himself, and there are a lot of discussions & examples from the point of view of the ASM programmer (but not only that):
      The WIZ - a new and radical processor architecture

      P.S. I'm not associated with Mr. Bush in any way; I simply like this kind of things.

      Bye!

      --

      SeqBox
  48. The 68000 had async operation with /dtack pin by Anonymous Coward · · Score: 2, Interesting
    This was the purpose of the /dtack pin. This was used to acknowledge a transfer when operating async, or you could just ground it and run things at cpu self clocking sync. So how is this new again?



    1. Re:The 68000 had async operation with /dtack pin by vidarh · · Score: 2, Informative

      Because that was for async bus operation, not async internal operation. The 68000 is fully synchroneous internally, as most/all other commercially successfull CPU's. Async buses is nothing new, and the ability to support it on the 68000 was in fact mostly to allow it to integrate with older hardware.

    2. Re:The 68000 had async operation with /dtack pin by NoMercy · · Score: 1

      It's diferent because it's not just a memory interface, it's every logic block in the processor.

  49. Re:Let's take a non-human group by Paradise+Pete · · Score: 1
    The computer cluster is running. *Correct*
    The computer cluster are running. *Incorrect*

    And yet, Pie are squared.

  50. Inconsiderate researchers by Itchy+Rich · · Score: 1

    With chips that don't need a clock, there's no room for obsessive tweaking and rediculous liquid nitrogen cooling systems.

    What will all the overclockers do with their time now?

    Congratulations Science, you've ruined another perfectly good hobby.

    1. Re:Inconsiderate researchers by maxwell+demon · · Score: 1

      Well, I'm not sure. Maybe "overclocking" will just become "overvoltageing", i.e. increasing the core voltage in order to make the chip faster (and since higher voltage inevitably means more heat, you still can use your ridiculous liquid nitrogen cooling systems).

      --
      The Tao of math: The numbers you can count are not the real numbers.
    2. Re:Inconsiderate researchers by Anonymous Coward · · Score: 0

      I'm no EE, but wouldn't a clockless chip just run as fast as the applied voltage allows? It wouldn't be "overclocking" so much as hotrodding. Increase the voltage to up the speed, then apply more cooling to keep it from self-destructing. Those LN2 systems would still do their job just fine.

    3. Re:Inconsiderate researchers by drmerope · · Score: 1

      Allow me to change the other replier's "maybe overvoltage" comment to "absolutely, all it means is that you need to increase the voltage."

      More voltage => more heat => same "overclocking" game.

      Some numbers (sorry, old from the '90s) for an Asynchronous MIPS R3000
      (Vdd, MIPS, power dissipiation (W))
      (1.00, 9.66, 0.021)
      (1.51, 66, 0.29)
      (3.08, 165, 3.4)
      (3.30, 177, 4.2)
      (3.51, 185, 5.1)
      (4.95, 233.6, 13.7)

      source: http://resolver.library.caltech.edu/caltechCSTR:20 01.012

  51. Re:Let's take a non-human group by WhiteDragon · · Score: 1

    they both are quotes in english. For instance:

    Bob said, "Joe said, 'I am Joe', but he was lying."

    --
    Did you mount a military-grade, variable-focus MASER on an unlicensed artificial intelligence?
  52. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    Wrong. One is an "apostrophe" when used alone and a "single quote" when used as one of a pair, the other is a "quote" or "double quote". -- Hope this helped!

    And um, why do you look at originators of computer languages? I have (English) novels printed in the 19th Century which happily use single quotes throughout.

    Like: 'A character says something.'

    I even have some where the typography is: >>A character says something.>>

    (What do you call those, by the way?)

    And then some where we have the double quotes: "A character says something."

    But there is one notable thing about *some* computer hackers: the absolutely perverse abomination of insisting on "inverted" quotes when none are offered by the character set. Such as: ``An example string." Ugh, the butt-ugliness. The horror. The -- the illiteracy!

    Have a nice day now.

  53. speed by Dr.Knackerator · · Score: 1

    how do you improve the speed of one of these things? get the transistors to switch faster? make shorter pipelines for popular instructions?

    all that is a lot of work, do you think thats why intel didn't persue it? because now they can just tweak a basic design every 4 months or so for an extra .2 ghz and charge the earth for it - for relatively little investment compared to the inital design cost of the original processor.

    1. Re:speed by Chirs · · Score: 1

      Increase the voltage, get rid of the resulting heat.

      Async designs are reversable, hence the speed of the chip (and the power consumed) are directly related to the voltage drop over the calculation path. If you increase the voltage, there will be a stronger tendency to finish the calculation, although the power consumption will go up.

    2. Re:speed by drmerope · · Score: 1

      There are two solutions:

      1) get the transistors to switch faster
      2) reduce the number of transitions on the critial paths

      This is the same for synchronous and asynchronous designs.

      1) can be handled using voltage scaling (higher V, faster transitions) or simply with scaling (e.g. going from 180nm to 90nm).
      2) This ultimately comes down to hyper-pipelining something which is slightly easier in asynchronous circuits.

      references:
      http://www.async.caltech.edu/Pubs/P S/2002_energyde layefficiency.ps.gz

  54. Sun has also done work in this area by mdxi · · Score: 2, Informative

    In 2001 they presented a paper on an asynch processor design called FLEETzero/FastSHIP. According to the patents list on this page, they're still doing work on it (see also here.)

    --
    Posted with Mozilla
  55. Re:All dialects are correct by famebait · · Score: 1

    the original language

    as if such a thing exists...

    I defer to logic itself to decide the greater dialect.

    In that case, English in general is right out.

    --
    sudo ergo sum
  56. Re: by Red+Alastor · · Score: 1

    The basis for treating corporation as persons is that it makes thing a lot easier. It is easy to find the "legal person" that is the corporation but hard to find the "collective noun".

    It's the exact same thing in Canada and I guess in most countries.

    --
    Slashdot anagrams to "Sad Sloth"
  57. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    Did you check for things like "members of the team are"? That'll give you a false reading!

  58. Re: What benchmarking nighmare? by Alwin+Henseler · · Score: 1
    "Well, a very cool (?) implication of this technology would be that chip performance would be depending of the, well, performance of the die used and the enviroment. So increasing voltage and decreasing die-temperature would make the chip faster automatically..."

    AFAIK, that is already the case with all IC's (including analog) that I have ever come across.. nothing new here. A fixed clock just limits operating speeds to 'known reliable' over specified voltage/temperature ranges.

    And for including voltage/temperature values in benchmark setups, that is no more than normal if you want reproducable results. Environmental settings are often implied, it's simply understood that benchmarked hardware is run with adequate power supply and cooling. I mean, who would think bad of a lousy benchmark result, when you know that an Athlon or P4 was tested with heatsink removed?

    And you all know overclocking stories, where half of an article is spent on describing voltage settings & cooling measures, colourful pics included.

  59. easier overclocking! by phsdv · · Score: 1

    No, it would be even easier to overclock! Set your CPU in the freezer and it will be faster, no need to change a voltage!!! Or switch of your heater, that is in winter where I live. Or crank up your AC, if you are living in Florida, thats all.

  60. NO NO NO!!! by kompiluj · · Score: 2, Funny

    Give me back my gigahertz!!!
    I want all my precioussss... gigahertz!!!

    --
    You can defy gravity... for a short time
  61. Re:A plea from down under by Anonymous Coward · · Score: 0

    Fuck you and your god bullshit. May the devil live in your butt forever you stupid christian piece of shit.

  62. Re:Let's take a non-human group by Anonymous Coward · · Score: 0
    "Geez Americans trying to teach the world English lessons."

    Original pro-'are' post:
    "In English, Intel is not singular. It is a composite entity, made up of many people, and as such should be considered plural when choosing the verb conjugation. Many Americans make this mistake."
  63. Phased Logic Discussion by hcob$ · · Score: 1
    One of my professors in college, Dr. Bob Reese has been doing alot of research on phased logic. Which in summary is:

    Summary
    Phased Logic (PL) is a self-timed design methodology that provides an automated translation of a clocked system in the form of D-flip-flops and combinational gates to a self-timed netlist of PL gates. The only global net in the self-timed netlist is a reset signal. The PL netlist is a micropipelined system with two-phase control. Two distinct implementation technologies are supported, fine-grain and coarse-grain.
    --ERC Website on Phased logic

    Pretty cool overall.
    --
    Cliff Claven
    K.E.G. Party Chairman
    Founding Leader of: Koncerned for Egalitarin Governance
  64. Question, by chadjg · · Score: 1

    I'm seriously out of my depth in this discussion, but what would an asynchronous chipset and processor do for those overclocking lunatics that like to play with liquid nitrogen? It is my understanding that some of the more extreme efforts are actually running the clocks so fast that signals can't propagate across the chip in time and that the synchronicity gets munged.

    If these "handshaking" asynchronous chips take off, each part of the chip could be cranked way up, and just wait for the slowpoke, right?

    --
    Why do I have this? I don't smoke.
  65. Grammar by notthe9 · · Score: 1

    In the rest of the world a corporation is a distinct legal entity and thus is not treated as a single entity. A corporation is composed of many people, hence it is a collective noun. This doesn't work. My family are leaving now? The group think so?

  66. It's not really very complicated... by Anonymous Coward · · Score: 0

    Instead of having a central clock signal, which you propagate all over the place, you just have individual "output good" signals from various logic blocks. So, an ALU just has a "the output has settled" output that goes to the "read from ALU" input on the register file, etc...

    If you've ever cobbled something together from individual logic IC's, and dealt with the glitch issues, you've pretty much already mastered asynchronous design.

    These designs aren't going to actually eliminate clocks for the places where they're needed (parallel busses, for example), they just decentralize them, so that 20% of your transistors aren't being used to de-skew, regenerate, divide, delay, and otherwise manipulate a central clock.

  67. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    Americans trying to teach the world English lessons. What next? Will they teach us how look for Weapons of Mass Destruction as well? Or how to decide an election result when votes don't get counted due to cheating in Florida? Somebody please mod everybody to blivion so we can end this destructive conflict

    Umm, fuckwit, the person promoting "your team are" is clearly anti-American, just like you. The original accusation was that "Intel is" was a typically "American" mistake. Someone then responded (correctly) that a composite entity is still treated as singular. The original moron is the parent of your post trying to explain how proper British and non-American English should use "Your team are." All this thread has proven is that there is no correlation between command of grammar and America bashing.

    You Eurasian/African xenophobic idiots think you are somehow better than your xenophobic American counterparts. The fact is that based on what little mental ability you have you share mostly everything in common, save for living on different sides of the drink.

  68. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    Yeah, I left Australia out of that list, unintentionally. The fact is that fuckwits manage to inhabit and reproduce in every corner of the globe.

  69. Re:Let's take a non-human group by Anonymous Coward · · Score: 0

    I'm sick of hearing about "single-quote" and "double-quote". One is an "apostrophe", the other is a "quote". I can only assume that the originators of computer languages which use apostrophes as quotes were illiterate.

    You are typical of so many humans. Thousands of computer languages have been developed by all different humans, with many different levels of training and brilliance (a greater intelligence than yours is probably all they share in common (yes, even the JCL and VB guys)), and your first assumption is to think that they must all be idiots, because of some assumption you have. You never skip a beat to think that you might not be quite correct, or there is a gray area, or some more complex yet plausible explanation.

    Ironically, based on assertion, in plain old ASCII (developed by those "illiterate" originators), the ' character is simply an "apostrophe" and the " is a "quotation mark". In general, though, it is all based on usage. Linguistically, the single quote and the apostrophe are two completely distinct characters. The former used for contractions and possession in English, and the latter used as...wait for it... quotations. The single quote is especially useful when you want a quote within a quote.
    In addition, in some typefaces the right-hand single quotation mark and the apostrophe are two completely different glyphs (mapping to those two distinct characters). In otherwords, the apostrophe and single quote don't even look the same (so even you should understand why calling them the same thing would be confusing).
    Codesets that are richer than ASCII, like UNICODE, have provisions for all these variations.

    BTW, UNICODE was not developed to satisfy the needs of "illterate" computer language originators. If there is one segment that needs UNICODE or an equivalent the most it is computer typesetting (whether that be on paper or the screen).

    Two small angle brackets > are also used as quotation marks and are called as such: "double angle quotation marks" Just because they look kinda like "much greater than" and "much less than" doesn't mean that they are.

    I hope this hasn't blown your small mind.

  70. I worked at Philips for a while. by rew · · Score: 1

    When I was a student, I did my internship at Philips. They were working on this back then. In 1990. "Almost ready". "expect results on the market in a year or two". ... Yeah right.