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IBM Claims World's Smallest SRAM Memory Cell
nokiator writes "IBM issued a press release today claiming that it has built an SRAM memory cell that is ten times smaller than those currently available.
My interpretation of the PRese in this release is that IBM will be able to build 256Mb or 512Mb SRAM chips or integrate 32MB or more SRAM into processor dies for cache applications in the future. Of course, showing some SRAM cell prototypes is a long ways from being able to manufacture this technology in a cost effective way.
There is no information in this PR about the speed or power consumption of SRAM blocks that can be built with this new cell technology. This is not likely to be a potential DRAM replacement for mainstream applications as DRAM already offers more than ten times density compared to SRAM at much better cost."
...they can only store zeros. They are working feverishly on scaling them up to store ones.
And people keep asking me why we don't buy servers from Dell. Maybe I'm old-fashioned in thinking that a company that continuously innovates the technology and not the distribution or marketing channel is whom I should get my technology from...
They say a combination involving E-beam. That do not smell like mass production.
IBM will be able to build 256Mb or 512Mb SRAM chips
One thing I've never really known is what does this type of figure translate to in terms of real amount of RAM on a memory module that I would stick in my computer?
Its always hard to tell because there is such a long time between companies saying that they have made X Mb fit on a chip to the time that they make a 512MB dimm.
This is not likely to be a potential DRAM replacement for mainstream applications as DRAM already offers more than ten times density compared to SRAM at much better cost."
I thought the PR implied "Although not as dense, SRAM is many times faster than dynamic random access memory (DRAM).", density is like a also-run.
Rock that crushes, Paper & Scissors that don't matter.
They say 50.000 at the end of a human hair. Do anybody know the actual size of this cell?
There's so many things wrong with this post...
a) the 64-bit CPUs that exist today have 32-bit instructions.
2) just because the width of the registers is 64-bit does not mean that all data that is processed is now 64-bit wide, 64-bit CPUs are certainly capable of processing 32-bit values.
D) somehow having a value stored as 64-bits doesn't mean you can use it for twice as many things as the same value stored as 32-bits (assuming it fits) or somehow all of your programs/algorithms can use the value twice as much as before (implying twice the work)
That is not true at all. The size of instructions is still 32-bits for all 64-bit RISC CPUs and the instruction size is the same in x86-64 as that of regular x86 (CISC). Now 64-bit CPUs give you the *option* to use 64-bit data/pointers, but you are free to continue using 32/16/8 bit data as you deem appropriate. Code/data size doesn't automatically increase.
Also, you may not necessarily be doing twice the work with a 64-bit CPU - it again depends on your compiler. In theory you *can* do two 32-bit operations in parallel using a 64-bit EX/FP unit if the ISA provides for packed operations (also known as SIMD instructions).
While I think this is great news, I just wonder how much longer it will be until a physical size problems emerges. I know that crosstalk and heat affect current processor designs, so do these issues also occur with memory as well?
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Of course, showing some SRAM cell prototypes is a long ways from being able to manufacture this technology in a cost effective way.
Well, were still talking about IBM here? Do you really think that a few hundred dollars more would even get noticed at clients that buy a server in the 100K range?
The main advantage of buying high-end gear from IBM, Cisco and the like isn't that you get cheap hardware ('cause you simply don't). You buy the gear from that company because you get 10 years in-house service including remote failure detection if you pay for it. That means, THEY call YOU before you even notice one of your tripple-redunant drives has problems. At this point in time, the technician is probably already on the way up to your office.
Sure, it's very expensive. But you save quite a lot by not having any significant downtime...
Seen in that context, 500 bucks more for RAM is IMHO just irrelevant to even think of...
Look, this thing is totally safe! Built it myself, you know. You just press that button like this and then turn that lev
However, I wonder if the additional implementation requirements justify the benefits. Static typing is only found in certain computer languages, and programmers have come to rely on dynamic memory allocation offered by malloc() or similar routines. I suspect with careful design one could fully exploit the advantages present -- with software being cheaper than hardware, it could easily be well worth it in embedded or pre-fabricated devices.
The type of implementor that uses (dynamic) extreme programming methodologies may be left out in the cold, although I would like to suggest that would occur anyway to a person working without a blueprint. Regardless, it will be exciting to see how this develops from the embedded perspective...
Try not. Do or do not, there is no try.
-- Dr. Spock, stardate 2822-3.
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The problem with E-beam is that it is a serial process. In effect you have to draw every single transistor using a megnetic field to move the electron beam.
What makes IC manufacturing in general manufacturable is the fact that you are using photo lithography with an optical mask through which you expose the wafer. This is a parallel process whereas E-beam, which can be good for engineering samples, sucks for manufacturability.
Huh? What you say makes little sense. While it is true that smaller caches with less associativity respond faster, there is no "search through them more quickly" as it is all done in parallel. What makes it faster/slower is the depth of match logic required when you have many way set associativity (all the way up to fully associative which is the most expensive).
Secondly, why in the *world* would you not want to cache more data if you could? Ideally, all of your main memory would be just a large one-way set associative cache for best performance. (Compaq once made a 386 machine that had all SRAM as its main memory. No wait states at all and it was *fast* *fast* but it was also *expensive* *expensive* and upgrades for the memory were incredibly expensive.)
I'm thinking that this post must have been a failed attempt at humor.
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Intel released a press release four years ago claiming to have built SRAM memory cells which (to my calculation) work out about three times as small as IBM's. IBM are clearly claiming to have invented the smallest commercially viable memory cells, but not the smallest outside of that context. Maybe /. should try to keep up a bit more.
I remmber back in the days of the release of the original Macintosh II, a lot of articles (In Byte, MacUser, etc.) about the new 68020 architecture stated that main memory in the Mac would eventually be transitioned to SRAM because of SRAM's speed and power-consumption advantages. Cheap and dense SRAM was coming, "real soon", so that extra wait states or caches would not have to be implemented when the 68020 was scaled past 25 MHz.
Then the original Mac Portable came out, with 1 MB of zero-wait-state SRAM as main memory. It cost $7300 with a 40 MB hard disk, and pretty much sucked in every imaginable way.
My sense is the poster wants to get a rise seeing his post be moderated informative. The first clues is where it states that SRAM is smaller than DRAM which false.
Every few months or so, new smaller stuff always comes out. I never see much that takes advantage of the stuff, though. That's unfortunate. Maybe it's just used in non-popular, expensive products for big corporations.
I guess this kind of stuff won't matter to the average user for another 10 years, if ever.
Excuse me, but isn't the cost of any feature directly related to its size, making the above statement self-redundant?
I mean, a wafer-start is a fixed cost, divided by the number of processors it yields. That makes the area of the processor die directly relate to its cost, and the size of any feature relates to its subcost portion of the overall processor cost.
Or in simple terms: Smaller features should always cost less because you get more of them per fixed cost wafer.
Am I missing something major here?
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
In the good old times calling a CPU 16-bit meant that its data size was 16-bit. Whether they offered 16-bit (TMS9900), 20-bit (8086/88), 24-bit (68000), or 32-bit address space was something completely different which is why people kept talking m-bit address and n-bit data size.
Personally, I blame it on the PC market which never cared much for existing definitions. Suddenly, an "n-bit processor" was a processor having an 2^n address space, not one which was capable of natively processing n-bit data. (As another example, wavetable synthesis described plain sample playback and not wavetable scanning as with PPG, Wavestation, Microwave etc.).
That's why you now can't tell whether "64-bit" means 64-bit address space, 64-bit data size, or 64-bit instructions...
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If you can shrink SRAM down to a size equivalent to DRAM, then it CAN serve as an effective replacement, and here is why:
1) No fancy control logic. DRAM needs to be refreshed on a regular basis. SRAM is a straight "chip select, read/write" type of ram.
2) low power. Because it is not being constantly refreshed, it can hold those bits with far less power. Thats why you see NVSRAM and don't see NVDRAM. Imagine having 1 gig of RAM that is battery backed up?
3) One can argue that without the control logic, it will be theoretically faster.
The OP is mistaken when they say that it will never serve as an effective replacement to DRAM. On the contrary, it will be an awesome repleacement.
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Just like the 'Turbo-Grafx16', 'Nintendo 64', and the '64-bit Atari Jaguar'.
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you should say - "they can only store value-challenged bits"!
The Raven
I'd be happy to design a circuit that will store an unlimited both ones and zeros in 19 sq nanometers for free.
If you want to read them back, well that's gonna cost you.
myke
Mimetics Inc. Twitter
You, sir, are the man.
You convinced at least five posters that you were serious while simultaneously spouting an illogical collection of computer-related jargon and utterly false statements. I expect to see you here again on April 1st.
Mod me down and I will become more powerful than you can possibly imagine!
Actually, it used to be based solely on the width of the general purpose registers in the CPU, implying that the CPU could process data in those sizes with one ALU operation (the ALU was as wide as the general purpose registers).
The 68000 you mention was considered a 32-bit CPU, or at least a 32/16 (32-bit internally, 16-bit data bus) as was the 68010 and it wasn't until the 68020 when it had a 32-bit data bus as well. There was even a variant that was the 68008 that was identically equivalent to the 68000 except it had an 8-bit external data bus. I have occassionally seen the 68000 referred to as a 16-bit processor, but the vast majority of times I've seen it discussed call it a 32-bit CPU.
As far as I remember, no processor has ever been 'named' relative to the address bus width. Even in the PC world I can't remember any time when the CPUs were 'named' relative to the address bus. Many 32-bit CPUs didn't have the full 32-bit address bus externally accessible. I can't think of any 64-bit CPU that has the full 64-bit address bus externally accessible.
As far as cache storage of data, the data formats are independent of the pointer size. The blanket statement that a 64-bit CPU effectivly 'halves the cache' is not true. If you have a program that deals only with pointers, then you'd have a point but 'int' on a 64-bit CPU is the same as 'int' on a 32-bit CPU (both being 4 bytes or 32-bits). It *is* true that a program compiled for 64-bit ISA will use *some* more cache, but that is entirely dependent upon the program itself. Again, a program that uses pointers a lot may use more cache than the same code on a 32-bit architecture, but a program that uses few pointers may not use much more (if any more) than the 32-bit counterpart, depending upon the datatypes used.
I've already patented that!
Let S_n = {nst+us+vt : s,t in Z \ {0}, u,v in {-1,1}}. For all n in Z where |n| > 2, Z \ S_n is infinite... right?
And how would you differentiate between two zeros and a one? If all you can store are zeros, then you are limited to a unary system which requires exponentially more room than a binary system.
Ben Hocking
Need a professional organizer?
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And explain: What are you saying you like, Dell, or IBM? Because I can't figure it out.
- It's not the Macs I hate. It's Digg users. -
Probarly a descendant from the Sony/IBM jointventure research for their Cell Processor. As i recall, the cell processor needed a relatively large ondie cache.
Hivemind harvest in progress..
Static RAM is a GREAT idea. Now if they can figure out how to make the rest of the components in the machine run off of static (CPU, hard drive, etc.) then we can throw away our power supplies altogether!
The blanket statement that a 64-bit CPU effectivly 'halves the cache' is not true. If you have a program that deals only with pointers, then you'd have a point but 'int' on a 64-bit CPU is the same as 'int' on a 32-bit CPU (both being 4 bytes or 32-bits).
In Sun's Java architecture, everything is either a primitive or a pointer. Implementations that do not choose to restrict themselves to 4 GB of heap must use a load of 64-bit pointers.
that is ten times smaller than
Um... doesn't ten times smaller sound rather oxymoron-ish? Wouldn't 1/10th the size be better?
--- Asking inconvenient questions for over 30 years...
Ones are physically smaller aren't they?
Engineering is the art of compromise.
IBM makes quite a few breakthoughs in the lab but they never seem to generate much successful product. Sure they make (or made) RAM chips, microprocessors etc, but they soon get overtaken by other manufacturers. I doubt they ever make money on the silicon they sell. Perhaps they make money when they license their patents etc.
Engineering is the art of compromise.
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a)
2)
D)
Urk?
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- - You can't take something off the Internet! That's like trying to take pee out of a swimming pool.
FPGAs are based (mostly) based upon SRAM. Doesn't this offer the potential of drastically increasing the size/complexity of FPGAs?
Seems to me that it does.
- Hawkeye
"...The smart and lazy ones I make my commanders." - Erwin Rommel
heh... from Home Alone, that older bully kid used it somewhere, I thought it was funny, and it stuck ;)
Hell ya! The major bottle neck in all 3D cards has been RAM. Sure, you can goes DDR2 and just make the path wider but the cost goes up dramatically. Using SRAM on video cards could allow the GPU to fetch and raster the data at a much..much faster rate.
Life is not for the lazy.
"as DRAM already offers more than ten times density compared to SRAM at much better cost"
It is the density that generates the cost benefit. For the same chip area and technology generation DRAMs are considerable more expensive than SRAMs.
It is the cost per cell not the cost per area that is less for DRAMs.
Was it only me that I misread SRAM as SPAM?
How can you have A long WAYS?
Maybe they've been reading too much Robert Jordan.
Found it, the cell is 0.143um2 and made in 32nm node. So your 0.157um2 was very close!!!