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ARM Offers First Clockless Processor Core
Sam Haine '95 writes "EETimes is reporting that ARM Holdings have developed an asynchronous processor based on the ARM9 core. The ARM996HS is thought to be the world's first commercial clockless processor. ARM announced they were developing the processor back in October 2004, along with an unnamed lead customer, which it appears could be Philips. The processor is especially suitable for automotive, medical and deeply embedded control applications. Although reduced power consumption, due to the lack of clock circuitry, is one benefit the clockless design also produces a low electromagnetic signature because of the diffuse nature of digital transitions within the chip. Because clockless processors consume zero dynamic power when there is no activity, they can significantly extend battery life compared with clocked equivalents."
Soooo... How many mHz does it run at?
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Can a processor like this do things like play sounds? If it doesn't have a clock I don't think it could measure time accurately so it could reproduce the samples. What other drawbacks are there?
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I read the summary and cringed. (1) Don't call them clockless -- they're called a-synchronous, because (unlike a synchronus processor, one with a clock), all the parts of the processor aren't constantly starting and stopping at the same time. A typical synchronus processor can only run at a maximum frequency inversely proportional to the longest length in the critical path - so if it takes up to 5 nanoseconds for information to propagate from one part of the chip to the other, the clock cannot tick any faster than once every 5 nanoseconds. (2) One very serious problem in modern processors is clock skew - if you have one central clock, the parts closest to the clock get the 'tick' signal faster than the parts farhther away, so the processor doesn't run perfectly synchronously.
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Nope. All the pre-Mac Apple machines were based upon the MCS6502 and its derivatives. All were clocked, the original Apple ][ Standard at 1 Mhz. The Apple ///'s selling point was that it had a hardware real time clock, which was removed in later revisions because of quality issues.
The higher the technology, the sharper that two-edged sword.
ARM, followd by PowerPC, are the most common cores for embedded Linux and embedded Linux boxes far outnumber servers and desktops (where x86 rule).
Engineering is the art of compromise.
The fact that the CPU itself has no master clock is absolutely irrelevant to timing applications. You can bet your bottom dollar that the processor will sink interrupts, and that there will be a timer/counter component to the chip. Timing won't be a problem.
The higher the technology, the sharper that two-edged sword.
oh wait....
I worked for ARM for four years.
Truely wonderful and very special company for the first two of those years, then it slowly and surely went downhill - these days, it's just another company. ARM's culture didn't manage to survive its rapid growth in those few years from less than two hundred to more than seven hundred.
Many current CPUs don't have built in clocks, but still need them. This architecture is very different. It doesn't need a clock at all. All the timing is based on the propagation delay through the gates. This is extremely difficult to do right.
Maybe the first commercial micro-processor. DECs VAX-8600 was asynchronous. And it smoked for the day. I worked on some of the multi-variant multi-source clock skew calculations for the simulator used to model the processor, among other duties. Very slick hardware for the time. External syncronous contexts are maintained of course for syncronous busses but the internal processor speed is quicker in theory and cheaper power since you have fewer switching transitions. Think of the fun in ECL logic back then. :)
- Tjp
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Those were the guys that fought the CORE, right?
"Waste not one watt!" - CZ
Sun exhorts people to make clockless chips
This is my sig.
It theoretically should make a good chip for PDAs and cellphones. I think initially it will be used as a controller for automobiles though. Asynchronous chips are currently not that fast because the tools used to design them are incredibly new, but they are already very low power. I predict we'll have them all over the place in a couple years is all. Intel and AMD might already be considering (or may already have) used asynchronous logic in parts of their processors or support chipsets.
Basically a good asynchronous chip would draw almost no power while it's waiting for something (like I/O events from network, keyboard, timers, etc). And it would instantly ramp up and handle the event as fast as it possible could. The speed is generally a factor of voltage and temprature. It's how fast the gates can switch and perform interlocks under current conditions, rather than what rate a clock is driving everything.
It's going to be interesting to see what performance metric is used on these "clockless" chips by the industry and by the marketing/sales types. MIPS? FLOPS? SPECmark? not that MHz was ever a good benchmark, but things like MIPS is a lot easier to manipulate to make your product appear faster than your competitors.
“Common sense is not so common.” — Voltaire
So in short, your next smart clock may as well have a CPU without a clock.
Those damn young'uns and their newfangled clockless clocks.
But your assertion about critical path is slightly off. Asynch processors still have a critical path. If you immagine the components as a bucket-bregade and the data the buckets, then they may not all be heaving the buckets at exactly the same time anymore, but they will still be slowed down by the slowest man in the line. The difference is that critical path is now dynamic. You don't have to time everything to the static, worst-case component on your chip. If you consistenly don't use the slowest components (say, the multiply unit), then you will get a faster IPT (instruction per time) on average.
And yes, you don't have clock skew any more which is nice, but you now have to handshake data back-and-forth across the chip. Of course putting decoupling circuitry in can help.
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Responsiveness of a CPU is never really a problem, humans generally precieve anything that happens in less than 1/10th of a second as happening instantaniously. The only real problem with using this chip in a PDA is it isn't very fast, the article says the chip is comparable to a 77Mhz ARM9 which is several times slower than anything you'd find in a PDA today. I would love to see a Palm-OS PDA based around this chip because of it's EXTREMELY low power consumption; we could be looking at the same kind of battery life as the original Palms.
One of the neatest things about asynch processors is their ability to run in a large range of voltages. You don't have to worry that lowering the voltage will make you miss gate setup timing since the thing just slows down. Increasing voltage increases rise time/propegation and speeds the thing up. The grad students had a great demo where they powered one of their CPUs using a potato with some nails in it (like from elementary school science class.) They called it the 'potato chip'.
"You saved 1968." - Ms. Valerie Pringle to the crew of Apollo 8
Is there a chance these things will cook themselves?
Current processors are clocked at whatever speed they can safely run at and many of them automatically underclock themselves if they overheat.
Without a clock, what keeps the speed at a safe level?
You missed OMGPonies!!!Speed.
Is it just my observation, or are there way too many stupid people in the world?
"What time is it?" "Shut! The! Fuck! Up! I'm saving energy here!"
Gads. Now that I'm "overqualified" to write software (i.e., employers don't seem to think experience is worth paying any extra for), the geek world has completely forgotten that it even has a history.
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Not to belittle the energy savings, but how fast is it compared to a clocked CPU with a similar instruction set? To me, speed the most interesting quality of a new chip design other than reliability. The problem with a clock is that clock speed is dictated by the slowest instruction. Since a clockless CPU does not have to wait for a clock signal to begin processing the next instruction in a sequence, it should be significantly faster than a conventional CPU. Why is this not being touted as the most important feature of this processor?
This seems to be a good overview of clockless chips. I can't vouch for its accuracy (not my area), but the source - IEEE Computer Magazine - should be good. The article was published March 2005.
(warning: PDF)0 18.pdf
http://csdl2.computer.org/comp/mags/co/2005/03/r3
This is extremely difficult to do right.
No kidding. When I took a digital systems lab class, we had to do one simple asynchronous circuit. The corresponding state machine only had four states (compared to a computer processor, which might have a hundred states or more), but it was probably the most difficult circuit to design. Basically, you have to make sure that as you're transitioning between states, you always end up in the correct one, no matter where you may be in between.
What did I miss? I remember the hype, the early diagrams of how it was all supposed to weave through without the need for a clock. Would someone care to elaborate on the post-mortem of what was supposed to be the first clockless processor, 4 years ago?
I can't wait to get my hands on one of these and over-asynch the hell out of it. Imagine running it under dry ice - I bet it could run up to 50% more clockless over its default clocklessnes.
I know typing this out will be useless, and it will get overlooked by the mods, but I might as well say this. Asynchronous designs have several advantages :
:). (Yes I know busses are clocked, before you start, but if they were not.... )
1. It will give good power consumption characteristics i.e. low power consumed, not just because of the built in power down mode, but also because of the voltage the chips will be running at. By pulling the voltage lower than a synchronous equivalent, it will be simpler to have greater power savings. This becomes possible if you are willing to sacrifice speed. and in async devices, speed of switching can be dynamically altered as each block will wait till the previous one is done, not until some outside clock has ticked.
2. Security: Async designs give security against side channel power analysis attacks. As all gates must switch (standard async design usually uses a dual rail design, so most gates means all gates along both +ve & -ve switch), differential power attacks become much harder. Thus async designs are perfect for crypto chips (hardware AES anyone?)
3. elegance of solution:the world is generally async. Key presses are, memory accesses are. so why not the processor
But they have several points of disadvantage:
1. They are hard to do. Especially using the synchronous design flow that most of the world uses. Synchronous tools assume, especially in RTL, that the world is combinational, and that sequential bits are simply registers that occur once a clock cycle (not true for full custom designs like intel and amd, but for slightly lower level : esp ASIC design)
2. The tools that exist now, are either able to do good implementation using only a few gates ie small functions or bad implementations, that are in worst case as slow as synchronous equivalents but are larger functions. Tools exist like http://www.lsi.upc.edu/~jordicf/petrify/ Petrify , but these become unusable for circuits with more than ~50 gates.
3. Async designs are usually large. This is not always true, but standard async designs are usually implemented as dual rail or using 1-of-M encoding on the wires. But the main overhead comes from the handshaking circuitry. For really fine grain pipeling, the output of each stage must be acknowledged to the previous stage. This adds a massive overhead, as it necessitates the use of a device called the Muller C Element, that sets the output to the output, only if the inputs are the same, or retains the previous value, if not. Many copies of this element are usually required, and its this that adds space, for example, a simple 1 bit OR gate, that would usually have 4 transistors, has 16 transistors for the dual rail async implementation.
For the time being, I think they will find a lot of use in low power applications - such as embedded microcontrollers/processors, in things like wireless sesnor networks, and security processors. However I believe that full processor design is very far off.
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Async work is very annoying when the whole system is one state machine.
Hence, large-scale async work is often based on every data transfer between modules being sent along with a PULSE or READY signal. Of course, every module has to be designed so that its output is ready when it propagates the pulse... otherwise there's bogus output into the next module. Basically, one module having the propagation delay timed incorrectly can kill the whole system. BUT, with fast logic, your system will simply run as fast as the hardware can handle...
Commercial async processors have been around for AGES -- but modern logic IC-based processors are rarely build and sold on a large scale, being mostly experimental designs.
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They come in 4 models: fast faster fastest OMGspeed
I thought they came in Light Speed, Ridiculous Speed and LUDICROUS SPEED!
So I take it you can't overclock it? :D
Unfortunately, self-clocked design (like the reported ARM uses) is also sometimes called "asynchronous" logic design; however, this is a completely different kind of thing than the "asynchronous" combinatorial logic used in clock-based design. Self-clocked design also does combinatorial logic in latched stages, but uses a self-timed asynchronous protocol to run the latches instead of a synchronous clock. Basically, the combinatorial logic figures out when it's finished, and tells both the next stage ("data's ready, latch it") and the input latch from the previous stage ("I'm done; gimme some more data").
To close the loop, each stage can wait until there's new data ready at its inputs, and space to put the output data. Thus, in absence of some bottleneck, your chip will simply run as fast as it can.
To overclock a self-timed design, you simply increase the voltage. No need to screw around with clock multipliers; as long as your oxide holds up, your traces don't migrate, and the chip doesn't melt...
ARM made a clockless chip in 1994 for cellphones. Couldn't find an amazing reference, but a quick google turned up http://www1.cs.columbia.edu/async/misc/technologyr eview_oct_01_2001.html where they briefly mention it... The last time I heard of this stuff being used was in 2001-- I actually wrote an English paper about it purely to see if I could bore my professor :-p
It's a regressive step if you look at the speed at which it can push things across. These days, the power consumed is as important an issue. Active research is going on in the area of Globally Asynchronous, Locally Synchronous (GALS, it's called ;) processors, where each module (like, say, the caches, execution units, reservation stations etc.) run their own clock (and hence its synchronous within the module), and communicate between each other using asynchronous protocols (known as delay insensitive protocols). Such a design greatly reduces the need for clock wiring which would greatly reduce area, reduce clock wiring, save power etc. (at the cost of some processing speed, of course). Google for Globally Asynchronous.. if interested.
I heard it would cost an ARM and a LEG...
Between the VCR, Microwave, etc. I changed 16 clocks since we went over to DST.
I will be happy to have CPU without one.
Spoon not. Fork, or fork not. There is no spoon.
On the PIC series of microcontrollers, you can time any code simply by adding up the clock cycles taken by each instruction and figuring in your clock rate. There's even a nice tool to do this for you. This is often handy for simple delays; sometimes you're using all the timers or you don't want to stick stuff into a bunch of configuration registers just to slow down a loop. I don't see this sort of timing being as easy when there's no such thing as a clock cycle.
ARM was never like that. Unlike their parent company, Acorn, it was both a company of brilliant engineers and was always highly profitable. In later days, Acorn's share in ARM was all that kept it from going under.
I don't like trolls and mod against me if you like, but I'd prefer if you'd reply.
You obviously haven't read up on the ARM, have you. You should, if only to learn what a truly elegant instruction set looks like. The ARM3 was a thing of pure beauty...
I don't like trolls and mod against me if you like, but I'd prefer if you'd reply.
AHA! Found it. It was the 65CE02 which had an on chip clock which you could send a trigger to stop, causing the MP to go into a suspended but wake-able state (and from 5v to 1.5v consumption). When the clock resumed via external trigger, so did the MP without having to go through its full start up cycle. They never did much with it oddly.
/. for?
:) Hey I'm amazed I even remembered it :P
When I read the article what popped into mind was low consumption while doing nothing, which is what made me think of it. So now I've shown my age and made quite the ass of myself, but what else is
So not the same thing. Sorry for the ruccus
You probably can't hook up a 10 Ghz oscillator to it
Of course you can. The question is: What will remain of the CPU?
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ARM and Intel are operating in very different market areas these days (sad actually as ARM processors fly). ARM are targetting the embedded and PDA type market (Alot Pocket PC's use StrongARM) and given all their embedded processors stuck in cars, washing machines etc I'd imagine in their target market space they've got more than 50% market share.
Can people please remember the computer industry does not start and stop with the latest bit of kit for playing DOOM3 or surfing the ruddy internet....
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Most digital logic has at least one repeating signal called a clock, which is used to sequence the logical changes (e.g. from 1 to 0) in the circuit. By limiting changes of state to a periodic time, you can simplify a digital design. One of the major challenges in digital design (besides errors in logic) is dealing with timing related issues such as race conditions. Race conditions occur when a logical operation uses the results of earlier operations. Because of the finite speed of signals inside a chip, sometimes a signal arrives too late for a proper operation to occur. Such an error considered to be a race condition.
Clocks help by allowing the designer to effectively freeze the state of the logical circuit on a regular basis. This way, all the signals in a chip can propagate to where they are supposed to go, then the logical operations occur. This process repeats on every clock pulse.
The problems with using clocks are pretty significant, however. First, you need to add a lot of additional circuitry to implement a clock. Another problem is that generally, A LOT of changes happen on every clock tick, which means a large spike in electical current (because you need to use the electrical current to actually change the state of all of the digital circuits). This spike also causes what is known as noise in electronics, and with higher frequency circuits, the noise can actually cause interference with other unconnected electronics (this is known as EMI). And another problem with a clock is that you generally need to keep it running all of the time for it to be useful, which means using electrical power even when no changes are occurring.
So, the asynchronous CPU is a significant engineering feat. It is very difficult to design, but it is probably much smaller and more efficient than any equivalent clocked ARM core. That said, I wonder how do you actually evaluate the performance? With synchronous CPUs, it is a simply a function of the clock speed and architecture. In addition, all of these devices need to be tested so that they are guaranteed to work - I wonder how they do that.
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There's no easy answer. On a traditional clocked processor, each instruction takes a certain number of clock cycles. In the async case, everything just takes however long it takes. In fact, some arithmetic operations might take variable amounts of time depending on the value of the operands.
Given an equivalent process, layout technology, and number of transistors, an async design will be at least somewhat faster and vastly more power-efficient than a clocked design.
But none of those things are going to be equivalent in the real world - except possibly the process that ARM designs to. So comparisons will be difficult.
In English please? Thanks.
Dear Poseur nerd;
Your Slashdot post has been audited by a nerd committee and has been found to be lacking in both quality and substance. Normally this would only result in downward moderation. However, in this instance it grossly lacks nerdly appreciation of the subject matter presented, indicating that you are not a true nerd. If you were a true nerd, you would have instead made a post about where one of the said clockless processors might be obtained, or maybe indicate how it might be useful for an linux ogg player, which you have failed to do. You also probably have a girlfriend and have your own place.
Therefore we hereby revoke your standing as a nerd, and must ask that you turn in your nerd card at the door as you leave the premises.
Sincerely,
the Slashdot phony nerd patroll
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At least you learnt something today ;-)
You just got troll'd!
Most (all?) commodity motherboards are completely synchronous. In fact, even the buses running at different speeds are actually clocked at rational fractions of the One True System Clock. (Letting them run at different clocks would require extra latency for the synchronization stages, to keep metastability from eating the data alive.)
The original 6502 had dynamic register storage (using capacitors, similar to dynamic RAM) that would lose information if the clock was held off for very long. So the CPU clock had to be run at a certain minimum frequency (a few hundred kilohertz IIRC) and though it could be stopped briefly, more than a few microseconds would cause the CPU to crash hard.
ARM is actually building this chip with Handshake Solutions, a Philips incubator. The work stems from Philips Research as early as in 1986 (yes that's 20 years from research to product), and has matured very much over the years. We used to have courses at our university explaining the basics behind these asynchronous designs. All in all I'm excited to see this technology finally in a product, and hope it will make my pda last yet a little bit longer.
Sun has clockless chips up and running (real silicon, not sims) and they have done some interesting things, but they don't have a complete system that's ready to ship. And there are other components out there that use the clockless philosophy to do certain things, but they're not CPUs in any sense. To give credit where credit is due, as the parent post points out, ARM beat Sun out the door with a clockless CPU that is a drop-in replacement (to some degree, anyway -- not clear how much) for an existing, established architecture. But that wasn't/isn't Suns goal (although perhaps it should be...). They're pushing in new directions, not using this to reimplement current architectures.
Am I part of the core demographic for Swedish Fish?
WTF? Why not just have an external chip pumping syncs in? Not everything has to be done from the CPU you know...
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> So basically, when it was a startup, you enjoyed your nerf tournaments, but then
> their investors eventually demanded that they make a profit. Was that about the time
> when you left?
Your view in this matter is utterly unlike the reality of events.
ARM was exceedingly hard working and to begin with something like half the staff had PhDs. What (IMHO) happened was that with rapid growth the quality of lower and middle management in particular was diluted and also politics, the rot of all companies, set in; more and more decisions were made because of *politics* rather than good sense.
When that happens, the inevitable happens.
It's NetBSD that requires gcc and a paged MMU.
Linux is more portable. Linux runs on the original 68000. Linux was just ported to the Blackfin DSP. There seem to be about a dozen crappy little no-MMU processors that can run Linux.
Linux requires a gcc-like compiler, but not necessarily gcc. IBM and Intel have both produced non-gcc compilers that are able to compile Linux.
A clock is a timer, as measured in Hz (oscellations per second). Generally the actions within each device, such as your processor or video card, operate on their own clock (this is the GHz number), while devices communicate with each other using the bus at the speed of the bus (more distance, mismatched components, and possibility for interference causes slower speeds, closer to 800MHz-1GHz these days).
Essentially (as an example), when a processor wants to copy something from a register to memory, it puts a signal on a control bus to tell the memory controller to charge a specific address of memory. The memory controller is reading this, and starts the action, knowing that it takes a fixed number of clock cycles to do this (think the timings of memory). After that time has passed, the processor routes the data in question to the bus. So the signal is being produced, the memory controller has it attached to the memory and charged properly, and the processor keeps it there long enough to write to the memory. That signal needs to be there as long as the memory is attached and set to write.
Now- imagine this type of situation (which applies to all devices, and within the processor's internal actions) should the timing be slightly off between all devices. Not very effective is it? The memory controller may still be reading while the processor stops writing, leading to corrupt data. Essentially, it syncs up the talking, listening, and computing.
This is true within each device as well, such as making sure that all elements of a function are performed at the same time and you don't end up with half of your answer after you actually need it.
Aync means that there's no clock, but rather, the timing of it is established before communication, using a few control signals and regularly adjusting accordingly.
-M
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