Intel's 45nm Patch Machinery Exposed
Roboticles writes "Tweakers.net paid a visit to Intel's laboratories in the California town of Folsom, the birthplace of the 45nm CPU. We spoke to lead architect Stephen Fisher about the development of the Penryn chip and the day the first A0 version arrived. We were shown the machinery used to test and patch the 45nm processor, which is currently being manufactured in Arizona for release next month."
You need a magnifying glass to view the machinary, its REALLY small.
liqbase
I thought the "TickTock" process of developing a technology two different ways was a really neat innovation. Few businesses would dare double their research just to reduce their risks. I wonder if a similar method is used in other industries.
:)
Imagine if Microsoft did it? Maybe we wouldn't end up with things like ME or Vista
I wonder if there's a competitive spirit between the teams.
So, its 45 nanometers? does that mean its 45 Ipod Nano's thick? Or would that be 4.5 Ipod Nanos thick? GAH! its too early to do this crap.
"Some men just want to watch the world burn..."
Yeah, it only conquered the world. :)
"The fight for freedom has only just begun." - Geert Wilders
In non-benchmarks, it's a win because it's a compression for executable code.
Intel's laboratories in the California town of Folsom, the birthplace of the 45nm CPU
So that's what they make those software CEO's do in prison after back-dating stock options...
No more making license plates I guess!
"If you think you have things under control, you're not going fast enough." --Mario Andretti
If you would like to troll on the failings of x86, there are well documented options for you. You must earn your troll-fu, young grasshoppa.
We at slashdot are scientists, specialists and kernel hackers. Your FUD will be found out.
It's only a win if your execution is bottlenecked by instruction bus bandwidth. That only happens if you're thrashing your L1 instruction cache, and THAT only happens with horribly bloated software and/or horribly small L1 caches.
While it's a good compression of executable code, it's good compression of x86 code. Other ISAs manage to pack way more into their instructions in the first place. Plus, the random alignment of x86 instructions means that the pipeline is elongated by a couple of stages just to find the start of them!
Sorry, but x86 being a nice compression is a half-truth. Other ISAs manage just fine being, for example, fixed 32 bits per instruction and massively benefit from the simpler design. They also tend to be roughly as compact as x86. If you really want to see a properly compressed ISA take a look at Thumb-2.
On all the x86 architectures I know, if you use any instruction which gets microcoded, you end up with a huge performance hit. You basically run single pipelined until the microcode ends. These days, both Intel and AMD datasheets highly recommend you use simple form instructions as much as possible.
Yes, there comes a point where instruction cache locality matters more than instructions per clock. Your average bloated GUI app would benefit more from optimise-for-size than optimise-for-speed, for example (and I wish people would realise that). Anything which pumps large amounts of data would be screwed if you did that, though.
In any case, the point is that other architectures CAN perform far better than x86 without the variable opcode length, prefixing and other nonsense. They don't produce large amounts of executable either.
In any case, the point is that other architectures CAN perform far better than x86 without the variable opcode length, prefixing and other nonsense. They don't produce large amounts of executable either.
... or run MSFT OSes ...
How many of them can natively run code written for the 16-bit variant of their line that was produced 30 years ago?
While most would claim that native 8086 and heck even 32-bit pmode support really isn't needed in the day and age of "long mode," dropping them would be a huge pain and at that point you might as well just go straight to a new ISA.
However, that said, it's still kinda cool that you can boot something as primitive as DOS on a box made today. Not that I have install media around
Tom
Someday, I'll have a real sig.
Wow. This all sounded very cool, and gave me a lot more faith in Intel. Until I realised that they hadn't once mentioned testing on Linux. Do they really ignore every real OS except windows (and probably Mac, I guess?)? :/
Oh stop it. The Grandparent Troll is right. The "CISC instructions running from the instruction cache into a RISC core runs really really fast" crowd always conveniently neglects to mention that the half-assed, non-orthagonal, non aligned instructions required a bus cycle to do the instruction fetch. All those pipeline stages are there to cover for the lame instructin set.
No folly is more costly than the folly of intolerant idealism. - Winston Churchill
IMHO, the title should read something like "Intel's Stephen Fisher speaks" or something vague like TFA.
The game.
I'm not saying it always works. I'm not saying it is a good thing. If I had the free option, I would be using Alpha or Itanium.
:P
Instruction length is, of course, only one factor, and I am guessing a minor factor, considering memory bandwidth, data cache associativity, floating point performance, and performance and flexibility of VM management seem to be more serious problems with current x86 implementations.
Not that any of it is really on topic
We at slashdot are scientists, specialists and kernel hackers. Your FUD will be found out.
I'm not saying it is good. I'm saying he is wrong. I'm all for a healthy bashing of x86, but lets keep our facts straight, please.
And besides, there is no level playing field for comparison when that RISC core is so lame, anyway. The quality example of that being that 800MHz Alpha's used to wipe the floor with 2 GHz Pentium IV's on floating point.
We at slashdot are scientists, specialists and kernel hackers. Your FUD will be found out.
> Merom team, that had managed to boot Windows on the A0 version of the Core 2 Duo in under thirty minutes ... Penryn worked, but it took six hours to get Windows to boot properly on it
Quite obviously a software problem. Now if they had used Linux...
I don't think there's an architecture out there that deals with unaligned instructions effectively. It's hardly a problem that solely exists with x86. The "encouraged to be used" instructions, however, do run very very fast and really, if the compiler is written to favor them, what's the problem?
Until I realised that they hadn't once mentioned testing on Linux.
Just because one article or press release was light on details, doesn't mean that it didn't happen. Here is what you seek. Intel did mention testing on Linux and some other operating systems.
http://enthusiast.hardocp.com/article.html?art=MTI2OCwxLCxoZW50aHVzaWFzdA==
"During a press briefing earlier today, Intel stated that the very first 45nm processor was already up and running and used by the Intel validation team to successfully boot a test system into Windows Vista, Windows XP, Mac OS X and Linux."
You are welcome.
The truth shall set you free!
Most people who visit the Californian town of Folsom, which lies at a two hour drive to the northeast of San Francisco, go there because it is situated close to the beautiful Lake Tahoe and some of the skiing areas in the Sierra Nevada mountain range.
Maybe it looks close if your home is in the Netherlands, but not in actual fact. No one goes to Folsom for the lake or the snow skiing (water skiing is another story). Folsom is almost at sea level, Lake Tahoe is at 6220 something, and 120 miles away.
Infuriate left and right
"I once overclocked a CPU / just to watch it die..."
--- The American Way of Life is not a birthright. Hell, it's not even sustainable.
I'm extremely tickled that there was an advert for AMD on this article when I first looked at it.
Honestly, while it's interesting to see how they are developing this chip, I am so much more interested to see how it's going to stack up to AMD's new chip in the works. Especially seeing as intel is running the 45nm and AMD is still developing on the 65nm. I'm wondering if AMD's product could actually give them the boost they need to jump out from the depths of the AM2 debacle.
There's a lot of fucked up shit on the internet. And I've downloaded it all.
Are you people still carrying on about this? RISC lost. Get over it.
Didn't know there was an Arizona in China.
You ever wonder, when you read a post like this, if some disgruntled IT worker in some company or another really /did/ do as they claim?
...license agreements!
ASML in Veldhoven, the Netherlands, holds about 80% of the market and has been manufacturing 45 um wafersteppers for some time already news article 2005. Intel is one of their customers, so actually Veldhoven is the birthplace of the 45nm processors... At the moment they are down to 32 nm already...
Last 2 years, I've heard about fantastic speed increases.
However my new PC is still slow as hell and it doesn't feel any faster than the old one.
I hear the CPU coming, it's rolling off the press
And I ain't seen this performance since the 90nm process.
I'm stuck in Folsom Labs, and the clocks keep running faster,
But that deadline keeps on coming, from that Santa Clara.
When I was just a junior, my mentor told me, "Look,
Always be a good engineer, don't ever push your clock"
But I overclocked a CPU just to watch it die.
When I heard that core blowing, I hung my head and cried.
I bet those folks at AMD in their fancy die package
Are probably overclocking 'till it's smoking wreckage
Well, I know I'm ticking and tocking, I'm building two or three,
But those specs just keep on moving, and thats what tortures me.
If they freed me from the deadline, if that assembly line was mine
I'd take that 90nm process and make it smaller, more refined
Boss of Folsom Labs, that's where I want to be.
And I'd let that CPU clockspeed grow exponentially.
"Fisher has been on Intel's payroll for quite some time: he worked on the 486 cpu, the definition of mmx and sse instructions, and also on the Pentium III. The previous product that Fisher worked on was codenamed 'Tejas'. It was to be a 65nm version of the Pentium 4 with an extremely long pipeline of 40 to 50 steps, in order to achieve clock speeds of 7GHz or even higher." Wow, up to 50 stages in the pipeline, and they were close to tapeout! Sheesh, someone needs to secretly tape it out and put that thing on ebay with a tank of liquid helium.