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Samsung '3D' Memory Coming, 50% Denser
CWmike writes "Samsung on Tuesday announced a new 8GB dual inline memory module (DIMM) that stacks memory chips on top of each other, which increases the density of the memory by 50% compared with conventional DIMM technology. Samsung's new registered or buffered (RDIMM) product is based on its current Green DDR3 DRAM and 40 nanometer (nm)-sized circuitry. The new memory module is aimed at the server and enterprise storage markets. The three-dimensional (3D) chip stacking process is referred to in the memory industry as Through Silicon Via (TSV). Samsung said the TSV process saves up to 40% of the power consumed by a conventional RDIMM. Using the TSV technology will greatly improve chip density in next-generation server systems, Samsung said, making it attractive for high-density, high-performance systems."
Does ram really use that much power.
Now 40% power savings on the latest 3D accelerator would be awesome. Probably help with heat issue.
Core memory is static in the true sense of the word. I've got core memory that hasn't changed a bit in 60 years. Punks !! You don't know memory.
It'll fit right in with my ex's computer. Stupid P.O.S. Gateway.
*takes a deep breath...* NOW WHEN SHE TYPES IN ALL CAPS and overuses LOL ON FOXNEWS.COM and adds a thousand!!!!!!!!!!!!!!! EXCLAMATION POINTS... her memory can be just as dense as she is.
There's a spot in User Info for World of Warcraft account names? Really?
Anything that reduces the cooling load and the power bill will be welcome.
This is great for the big business side of things, but how soon will we see this on the consumer level? I mean, we keep seeing all these really high spec systems being used for the governments and large operations, but nothing for the little guys? TFA gives no hints.
We've added another dimension, and got 50% denser. Sounds like we didn't do our jobs very well.
3D geometries have serious issues with line saturation and heat dissipation. This is because of thermal noise, and the increased voltage needed to overcome it. (which in turn, creates more heat.)
We are already at the point where high performance RAM chips need heat spreaders, and that is with 2D chip geometries that can eliminate heat reasonably efficiently.
When you start stacking multiple silicon fab layers together, heat builds up in the layers, requiring more voltage to overcome thermal noise, which produces more heat...... You get the idea.
Without separating the layers with some kind of highly thermally conductive intermediate to pipe the heat out, the insides of the chips become little easy bake ovens, and estimated service life drops radically, as does performance metrics.
I could see them going 2 levels deep in the geometry, with a special package with heat spreaders on both sides (of the package itself that is- not the DIMM) or something crazy like that-- but I really can't see a big "solid 3D block" of silicon getting plugged anywhere. IF such a technology were to come into being, it would need to be made from something that is damned near to being a room temperature superconductor to keep from being unreliable/a fire hazard from thermal noise.
Alternatively, it could be done in a photonic computing approach, using optical transistors and optical interconnects... that would solve the heat problem too, but would make servicing the system substantially more difficult.
I've always wondered if there was a reason why manufacturers didn't use both sides of the silicon for lower powered chips, like memory. Seems like a win-win... twice the component count for the same silicon investment. Yeah, handling might be tricky, but not a showstopper.
There are patents going back a decade pertaining to using microfluidic ducts as a heat transfer mechanism. Every few months now, there's another article on slashdot about one of the chip giants testing out such manufacturing techniques. Just a few links from a quick googling...
http://www.xbitlabs.com/news/coolers/display/20031008155430.html
http://www.electronics-cooling.com/2002/11/electroosmotic-microchannel-cooling-system-for-microprocessors/
http://www.frostytech.com/articleview.cfm?articleid=2424&page=11
http://www.w7forums.com/nanotechnology-delivers-revolutionary-pumpless-water-cooling-t6658.html
Despite the summary, I don't think they're literally talking about 'stacked chips' in the sense of 2 separate packages here. I have (seriously) a 64KB expansion card for the original IBM PC (1982) that achieves its incredible memory density with stacked chips. A quick look at the link to 'Through Silicon Via" suggests something more like two wafers inside a single plastic package, with vertical traces connecting them together inside the package.
RETURN without GOSUB in line 1050
they're talking about stacking the dice, not the devices. You know what dice are? They're the little chips of silicon that are then packaged to make the IC's that you typically see and use. Unless you can precisely align and drill little tiny microscopic holes in the dice and electrically connect the one on top to the one on bottom, then you haven't been doing what they're doing. Not even close.
The closest anyone has ever got to this is stacking small dice on a larger die and wire bonding the pads of one to the other.
me. --a by-product of public education
As long as I don't have to wear those stupid glasses, I'm all for this 3D memory.
You see? You see? Your stupid minds! Stupid! Stupid!
Except for the fact that this development is absolutely nothing like what you describe. But hey, who let anything like logic stand in the way of a "I used to do X back in the day" post?
My blog. Good stuff (when I remember to update it). Read it.