Intel Announces Xeon E5 and Knights Corner HPC Chip
MojoKid writes "At the supercomputing conference SC2011 yesterday, Intel announced its new Xeon E5 processors and demoed their new Knights Corner many integrated core (MIC) solution. The new Xeons won't be broadly available until the first half of 2012, but Intel has been shipping the new chips to a small number of cloud and HPC customers since September. The new E5 family is based on the same core as the Core i7-3960X Intel launched Monday. The E5, while important to Intel's overall server lineup, isn't as interesting as the public debut of Knights Corner. Recall that Intel's canceled GPU (codenamed Larrabee) found new life as the prototype device for future HPC accelerators and complementary products. According to Intel, Knights Corner packs 50 x86 processor cores into a single die built on 22nm technology. The chip is capable of delivering up to 1TFlop of sustained performance in double-precision floating point code and operates at 1 — 1.2GHz. NVIDIA's current high-end M2090 Tesla GPU, in contrast, is capable of just 665 DP GFlops."
4chan is still down? Maybe we should lend them a hand.
Faster! Faster! Faster would be better!
I mostly understand the figures this post states, but it sounds like engineering dialog from 'Star Trek: Voyager'. But, all this means to me is that the chips from last year are now cheaper that they've been out-classed.
When they said nobody needed multicore processors
[citation needed]
More than likely, there's 64 cores but only 50 are activated because they can't get a decent yield of perfect chips. That also means that you might be able to get samples of 25 core chips that didn't even make the 50 core cutoff. (One core might also be dedicated for book keeping purposes)
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Odds are... they have it lined up such that... they are in a 5x10 grid. Or a 5x5 Grid front/back.
Just because it's a computer doesn't mean it's bound by the power of two. Boards are rectangular. Chips laid out aren't necessarily in binary distribution.
This would be a +1 if you werent posting as AC.
Your average consumer doesn't need 50 cores. For HPC which this was designed for, multiple cores are essential. As for the number of cores, I would guess die size was a factor. There also might be redundancy. It's a RAID 50 CPU. ;)
Well, there's spam egg sausage and spam, that's not got much spam in it.
I'm guessing there would have to be glue logic to get all these processors to share the memory space as well as read/write access. From the promotional pictures of other multi-core chip dies, each core is usually surrounded by a band of interface logic as well as a hefty large block of cache memory. That seems to be the biggest change in the evolution of CPU's. It seems easier to just create larger caches or more cores than anything low level.
Maybe they accept one or more non-functional cores in exchange for increased yields. Those cores that don't function correctly could simply be disabled.
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Intel's period of dismissive attitude toward advanced features(multiple cores, 64-bit support on x86, something that sucked less than FSB) was never really serious. Back when they still thought that they had a chance of making IA64 the 'serious' platform and gradually letting x86(and AMD) sink into the bargain bin, they did some tactical rubbishing of what "normal users" needed in order to justify restricting those features to the high-end SKUs; but they worked on them.
Once it became clear that that particular plan wasn't a happening thing, and that AMD was delivering serious server parts and knockdown prices, and Nvidia was doing interesting things with GPUs, and ARM licensees were pumping out increasingly zippy low-end chips, they stopped fucking around. These days they'll still charge as hard as they can for the features provided; but their hopes of sandbagging x86s in order to sell IA64s are dead
Who said nobody needed multicore processors? That seems like a pretty unlikely claim, particularly from intel who were very much into selling multi-cpu systems to the high-end long before multicore became the norm. I had a dual-socket pentium II consumer grade system ages ago. That we were headed to multicore was obvious even then.
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Your average consumer doesn't need 50 cores.
Sure they do. What do you think a GPU is? History has shown over and over that we can never have enough computing power. Now that we're at the physical limits of clock speeds, parallelism is going mainstream.
"Your average consumer doesn't need 50 cores [yet]"
Games are getting pretty good at using my 1536 core GPU, which is just a co-processor
Pfffft! My prosthetic horse cock penis can deliver 500 OPH (orgasms per hour)
"DP" is double precision in this case, not the other one;)
What natural phenomenon would require that the number of course on a chip be a power of 2? I can't think of any.
I wonder if Intel is taking a page from IBM's playbook.
Upper end POWER7 CPUs have the ability to have half their cores turned off. The cores that are on can then use the disabled neighbor's caches, and run at a higher clock speed. For some things, this switch actually speeds up some tasks that can't be evenly broken up into balanced threads.
I can see Intel doing this where some cores are disabled due to manufacturing defects (which happen to all dies), and having the operable cores use nearby caching which would otherwise go to waste.
A 50 core chip at 1GHz is going to need to perform 20 double precision floating point ops per cycle per core to achieve 1Tflop performance. OK, so 1.2GHz cuts that down to 16flops/clock. Since when can anything Intel Architecture achieve that many flops per cycle? Two 4-element dot products is only 14 flops. I suppose if they did two vector-scaler multiply-adds that would get 16 flops per cycle. So I just answered my own question. But can they really keep the FP unit running continuously at that rate? On all 50 cores?
Now that we're at the physical limits of clock speeds,
Since when? You can easily overclock most modern chips to 4ghz and with enough cooling to 5 or 6+ ghz. The i7 sandy bridge chips for example have been overclocked past 6ghz. So exactly what supposed "physical limit" do you mean?
Reminds me that I have a dual Deschutes 350 in the attic somewhere. Served me faithfully from 1998 to 2004. If it wern't for the 128MB of memory and the price of electricity - I might still have it do..... uhm something. Trouble is it's still hard to do multithreading, and our programming languages are still inherently single thread, maybe with some thread primitives glued on.
Run with the lemmings, and you'll get your feet wet.
Your average consumer doesn't need the 80386. There's hardly any software compiled to take advantage of its features anyway. I can see maybe someone using them for servers, but that's a pretty small niche.
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Today I can go to the store and buy the Nvidia board that they mention. When can I buy a system with a Knight's Corner chip? What about a PCI-E board? The answer is never. It will only be sold to Intel's partners in labs and research environments for special projects. It means very little to most of us.
At 6Ghz, you are very close to the speed of light in copper, so unless you can break the speed of light... its a "physics limit".
Below this point you have the problem of energy efficiency, i.e. whats the point of spending more energy on cooling than on actually powering the thing?
Intel's 3d-transistors are HUGE because of this, they can push higher clock speed more easily.
Because computers count in binary, which is powers of two. And, I'll assume you meant cores.
Historically such things have been powers of two to make the addressing simpler without having extra magic or control lines left over. So, 1, 2, 4, 8, 16, 32 and 64 all make sense in terms of being expressable in a fixed number of bits ... 50 to some of us seems like a fairly arbitrary choice. Since you use an unusual combination of wiring, it might as well be 37 or 51 since it's not a number that 'naturally' lends itself to computers. The device is likely wired in such a way that it could count to 64 ... or they're doing things in a slightly odd way.
Anyway, that's why some of us find it to be a little odd. And it's also why the hard-drive makers deciding "1 GIG" is "1,000,000,000 bytes" is irksome ... with all of those extra powers of two, it should be "1 073 741 824 bytes". Which means you lose about 72MB/GIG ... so my 2TB drive isn't.
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Addressing.
Let's say you've set aside 6 bits in every data structure that deals with core administration. You can grow to 2^6, or 64 cores without re-architecting your data structures.
As long as we are using binary in computers, making everything 2^N will make the most efficient use of space.
Of course, space isn't always the limiting factor, so sometimes for cost or speed reasons, we see objects that number 2^N-M.
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I remember almost exactly that quote in PC Magazine back in the day. I think at the time it was the 80486, but same thing. they probably said the same thing about the '386 too.
Of course, I have a quad-core machine sitting on my desk at home with 8GB of RAM, and running at a clock speed two orders of magnitude higher than my '486 did. :-P
So, obviously consumer needs for CPU speed is growing far faster than anyone would have predicted in the late 80's/early 90's. I still remember the first time I saw a PC with a 1GB hard-drive ... a bunch of us stood around it thinking "WTF will we ever do with that much disk space?".
Lost at C:>. Found at C.
Tilera's 100-core processor is built like this. It's a 10x10 grid of cores.
So, are you always an asshole, or just on Slashdot?
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Indeed, cores. And I still don't see any reason, and AMD has 3 core processors. I can have 3G of memory. I can have 9G of memory. Binary numbers are not pervasive by mandate in all areas of computing.
Though I do agree base-10 usage for hard drives is ridiculous.
Nah. That extra bit you lose isn't going to cause anyone any heartburn. And nobody's using 6 bits for anything. It's a specious argument.
Well, since I own 3 iPods and an iPad ... you'd think I'd be the one being accused of being an asshole by that logic.
I'm going to go with self-righteous prick who feels entitled to be an ass on the internet because he's got a 5-digit Slashdot ID and therefore considers himself to be l337.
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Wonder if they'll produce a consumer version.
I use an ATI card as my main video card, wouldn't mind sticking a physics card in the other PCI-E slot. The thing is that if I put in an Nvidia card it won't work as a physics card since Nvidia has written the drivers in such a way that if you have a non-Nvida video card as your primary video card Nvidia will not allow you to use their cards just for physics.
So my hope is that if Intel puts out a consumer version then either I'll be able to buy an Intel board just for physics or Nvidia will drop their stupid restriction.
Either way if Intel puts out a consumer physics card I win.
Don't know something? Look it up. Still don't know? Then ask.
We may yet see high-end Intel discrete graphics cards in the future.
Knights Corner sounds like it is basically a high-end GPU without the actual graphics output. This lets Intel position it as a professional product for HPC and supercomputing, and squeeze out as much profit as possible from the early models. Then, once the R&D cost has been amortized and the fab technology is advanced further, they can add a HDMI output, dedicated RAM, and glue logic, and write appropriate drivers to make it a full-fledged graphics card. Of course this may lack some features of the professional Knights Corner (ECC support?) so it won't cannibalize the high-end market. But it has the potential to be much more power-efficient than AMD and nVidia enthusiast products.
Well, in fairness, on the memory side, you do that with some combination of memory modules which are addressable by powers of two. (eg. 2GB + 1GB, or 4GB + 4GB + 1GB), each of which is discrete from the others. I don't believe you can buy a 3GB or 9GB memory module.
Nope, absolutely not. Not saying that ... just saying that traditionally such things have been architected to use powers of two because it was most efficient.
Obviously, for other reasons, Intel decided to go with 50 cores.
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I agree generally, like AMD's bulldozer hitting 8GHz on a single core before failing to the limits of physics (even with extreme cooling). I'm assuming nobody will never be able to get more than 1 or 2 cores active (out of 8) while getting to 8GHz on that architecture.
But these days, the chips run in multiple clock domains. I believe the Intel chips are separated by a base clock, L3 Clock, Core clocks, RAM clocks, and bus clocks. The architectures are moving ever toward asynchronous operation in order to pack billion upon billion of transistors on a package without having to synchronize them all the time.
I'm at SC11 right now and just attended NIC's MIC presentation. The scaling looks fantastic according to various codes that they compiled to run on it, but what was notably absent was performance relative to traditional x86 chips. The final presenter even said that now that the technology has been demonstrated to work (with minimal porting effort required) the next step will be to optimize and improve performance. The take away is that relative to Intel's other chips, MIC performance wasn't impressive enough to include in the presentation. That's fine in my book because it's an ambitious project, but it sounds like there is still some work to do.
Certain models of Xeon processor have three memory controllers. Which, when configuring for maximum memory bandwidth, leads to memory being measured in terms of three times powers of two (3 x 2^30.)
I'm guessing 5x10, if you look at their Intel Core i7 3960X the cores are about twice as wide as they are high.
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Ah, the disaster that is the move from real to protected mode.
Summary: First fiasco was that in year 1982 MS ignored the announcement of the 286 around the time and proceeds to develop a real-mode multitasking version of DOS, and only in around 1985 when IBM refused to license it that it was realized it was a mistake. And while the resulting OS/2 1.x sucked and lost it's chance with Windows 3.x (which was incompatible and both designed for 16-bit protected mode), second fiasco was when MS broke the JDA with IBM in year 1991 before the 32-bit OS/2 2.0 (which had been developing since year 1989) was even given a chance. Then later on MS attacked OS/2, particularly in the Wrap era when MS resorted to tactics like astroturfing (look up "OS/2 Microsoft Munchkins" for example). Imagine if MS embraced OS/2 instead. Both fiascos delayed the move to protected mode by years, not to mention MS's attacks on DR-DOS as OS/2 did not depend on DOS.
It's not storing 6 bits in a data structure. It's running traces (if that's even what they're called in IC design) throughout the die connecting these things together. At that level adding two extra traces to carry those two bits is an expense you might want to forgo. However once you've got six wires/bits out there, the only reasons I can think of to not use 64 whatevers is the previously mentioned heat management and die yield issues.
Just shows you the progress in CPU power: ASCI Red was the first supercomputer to go over 1TFlop, and was massive, now we have this with just one chip!
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Still bitter?
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In 32-bit color, only 24 bits are actually used. It's just more efficient to process one pixel in a 32-bit register than have to screw around with ANDs and shifts to get the data you want. The leftover eight bits are usually zeroed, sometimes used to store alpha or depth information.
Since when?
Since the point we reached the ability to handle the power and heat dissipation requirements economically. Engineering is about tradeoffs. Until we get better materials, multicore is more cost-effective than push the clock beyond the reasonable cost envelope.
except for that pesky 8-bit alpha channel, which clearly isn't used.
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Yea, I know it is too late. The good news is that the x64 transition went much better.
No, light travels 5cm in one 6 GHz clock cycle, in a vacuum. Speed of light limitations have been a consideration for years. The Cray1 was designed in the early 70s and its physical design allowed for the propagation speed of electricity in copper. It only ran at 80MHz. It's not just about cycle time - what's the duration of your edges? What other latencies are there in the electronics? In 2004, IBM's POWER5 MCM was 9.5cm wide and the CPUs ran at ~2GHz. Not sure what speed the interconnect ran at.
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Or it's 64 cores with an average usable yield of 50 "good" ones.
Log in or piss off.
A beowolf cluster of these! but seriously even one wouldn't be efficient enough to be worth it yet even in top-of-the-line OS's. We need a whole new paradigm of algorithms and maybe even a new language to do this right.
If video games influenced behavior the Pac Man generation would be eating pills and running away from their problems.
Well, in fairness, on the memory side, you do that with some combination of memory modules which are addressable by powers of two. (eg. 2GB + 1GB, or 4GB + 4GB + 1GB), each of which is discrete from the others. I don't believe you can buy a 3GB or 9GB memory module.
However certain intel processors do use interleaved triple channel memory so there must be a division by 3 going on in the memory addressing system somewhere.
note: i'm known as plugwash most places but i screwd up registering that here somehow in the past and now can't register
http://techresearch.intel.com/spaw2/uploads/files/FASTsort_CPUsGPUs_IntelMICarchitectures.pdf
With cores it's a little bit different than RAM in that you're physically limited by how many you can squeeze in a certain size.
So the addressing may be limited to 16, 32, 64, whatever cores, but physically you may not quite be able to get 16 in that space so they might say max out at 14 and then get a few dead ones here and there so end up selling 8, 10's and 12's with the rare perfect 14's being used for some special customers.
Now with the 50 cores, you might actually have 53 or so actually WORKING cores but the extra 3 are turned off just so they sell a nice pretty round number like 50 and not 51.
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The SI prefixes are specifically base-10 units, and have been so since the 1800's, with the metric system, and later adapted into the SI system. The fact that computer scientists and programmers misused the units and disregarded an established standard of communications and data encapsulation, and the fact that people STILL do it, is what's vexing, not the fact that the storage manufacturers have taken to use the proper approach.
Everyone seems to be defining High Performance Computing as CISC/RISC chips with multi-core processors utilizing Instruction Level Parallelism and Thread-Level Parallelism with extremely fast multi-level Caching. HPC High Availability computing is a synergy of CISC/RISC chips combined with Application, Integrated Instruction, Facility, Graphic and Cryptography assisted processor technologies supplemented with Integrated Coupling facilities. These processors must share access to large amounts of fast Dynamic Random-Access Memory and be integrated into fast I/O bus architectures for a variety of High Performance connectivity with networking equipment, data storage, and other peripheral devices. All this hardware must work in concert with a variety of firmware, hyper-visors, and operating systems supporting telecommunications, storage management, databases, application run-time environments, application servers, web servers, online transaction servers, redundancy, security, applications, fail-over, backup, recovery, archival, and administration management. IBM has been doing HPC/HA for quite a while now. Hewlett-Packard, Oracle Sun Microsystems, Microsoft, Intel, EMC, and Cisco seem to be still chasing the dream.
Amazing what a liquid nitrogen jacket with a liquid helium center can do when overclocking.
"I still remember the first time I saw a PC with a 1GB hard-drive ... a bunch of us stood around it thinking "WTF will we ever do with that much disk space?"."
Now we're like "Damn 2GB texture pack."