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Intel's 128MB L4 Cache May Be Coming To Broadwell and Other Future CPUs
MojoKid writes "When Intel debuted Haswell this year, it launched its first mobile processor with a massive 128MB L4 cache. Dubbed "Crystal Well," this on-package (not on-die) pool of memory wasn't just a graphics frame buffer, but a giant pool of RAM for the entire core to utilize. The performance impact from doing so is significant, though the Haswell processors that utilize the L4 cache don't appear to account for very much of Intel's total CPU volume. Right now, the L4 cache pool is only available on mobile parts, but that could change next year. Apparently Broadwell-K will change that. The 14nm desktop chips aren't due until the tail end of next year but we should see a desktop refresh in the spring with a second-generation Haswell part. Still, it's a sign that Intel intends to integrate the large L4 as standard on a wider range of parts. Using EDRAM instead of SRAM allows Intel's architecture to dedicate just one transistor per cell instead of the 6T configurations commonly used for L1 or L2 cache. That means the memory isn't quite as fast but it saves an enormous amount of die space. At 1.6GHz, L4 latencies are 50-60ns which is significantly higher than the L3 but just half the speed of main memory."
. . .that Broadwell broad, well, is a broad well into which you could throw your entire career.
Just say no, David.
Get thee glass eyes, and, like a scurvy politician, seem to see things thou dost not.--King Lear
"At 1.6GHz, L4 latencies are 50-60ns which is significantly higher than the L3 but just half the speed of main memory."
WTF? The correct would be, I think, half the latency of main memory...
Seems other users have a bigger cache than yours...
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At 1.6GHz, L4 latencies are 50-60ns which is significantly higher than the L3 but just half the speed of main memory.
Hmmm. L4 cache runs at half the speed of main memory? That doesn't seem right Why bother reading these summaries? The people posting them certainly don't
The only benchmarks I have found is from SiSoftware. http://www.sisoftware.co.uk/?d=qa&f=mem_hsw
But how is this going to effect Firefox, Photoshop, or video conversion?
Does it have an effect on battery life?
On laptops? Perhaps it could, I suspect that an eDRAM cache+slower main memory could have lower total power consumption at the same performance level than a faster main memory, especially if you have more of it. I believe that the major power usage component for main memory DRAMs is actually using the memory (as in, transferring the data).
Ezekiel 23:20
Broadwell represents a miniaturization step from 22 to 14 nm structures. Why do they keep the capacity of the Crystalwell L4 cache at 128 MB? They could put twice that memory onto a die with the same area as the 22 nm Crystalwell version. Is the Crystalwell die for the Haswell CPUs so large and expensive that they have to reduce its size?
At least as marketed, the main advantage is allowing the GPU some RAM that isn't DDR3 stolen from the main system a couple of hops away (which has traditionally been one of the things that make integrated graphics really suck, and cheap discrete parts that use DDR instead of GDDR, and/or an excessively narrow or slow memory bus kind of suck).
Given that even intel's marketing optimists don't say much about CPU performance (and also given that it's a mobile-only feature, you can't even buy an non-BGA part expensive enough to have it, which would be unusual if it actually improved CPU performance enough to get enthusiasts worked up; but is downright sensible if the target market is laptops sufficiently size/power constrained not to have discrete GPUs; but where pure shared memory was dragging GPU performance down.)
With this 128MB cache, shouldn't this CPU be able to run an OS like Win95 of an older Linux without additional memory?
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Photoshop? Considering that the adobe rgb or other color spaces combined with the file sizes of some of the larger images coming out of cameras, your gains in latency would really depend on Photoshop and the OS being able to handle the L4 cache and keep the right part of the image in the cache. Video editing, with file sizes into the gigabyte range would probably see no gains at all. Video conversion, with a program that keeps a reasonably sized buffer, should see a good performance gain; but it would require code that knows the L4 is available or the OS to predict that L4 is a good place to put a 10-50-100MB buffer. The real gain will be in common things: playing a video, browsing the web (seen how much memory a bit of javascript or the JRE can eat up lately? Or Silverlight/Flash?) and email clients (cache all your email in L4 for faster searching).
As for battery life, I have no idea. It might use more power, since DRAM requires constant power to refresh data where SRAM is pretty stable; but the lower leakage of using a single transistor instead of 6 might prove to be a benefit. It would take a good bit of time and some pretty good test code to figure the difference, I suspect.
I knew I should have waited for 129mb cache
rewriting history since 2109
Let's see, the tiny amount of L1/2/3 cache currently is dictated by the energy budget of the CPU. Looking at the energy budget of the 4900MQ and the 4960HQ chips, you can take some wild arse guessing to get that the 2 megs of L3 cache sacrificed got back enough to power the 128 megs of L4. Then consider that there is only 64K (yes, kilobytes) of L1 or 256K L2 per core on the Haswell chips, and at 3.9GHz desktop chips you are looking at 84 watts of power dissipated . . . you can start to work out how much of that is due to leakage current from the 6 transistor L1/2/3 cache design.
Let's face it, SRAM isn't tiny, it leaks amps like a sieve at the tiny process size that everything is done at now days, and it's main advantage is that it doesn't take a controller to access and it's bloody fast and the bandwidth can be pretty sizable. A gig of SRAM on die would, I suspect, heat a small room; that much DRAM per core would slow the cores down due to the inherent latency of accessing DRAM.
So, sure, DRAM chips may be cheap, but putting them on the CPU die would be horrid. And SRAM still isn't cheap; either in die space, energy budget, or dollars!
Cache performance impact is very heavily dependant upon application characteristics. Specifically, active memory.
Best case, when you're working with an active set that's larger than L3 but under L4 - around 100MB or so - and you're accessing it on a repeating pattern, and the compiler hasn't found any tweaks to help, and you're not multitasking, and the OS isn't swapping you out every slice, and the stars are aligned in your favor... the theoretical maximum performance gain can be up to 2x. It's very rare you'll find a program that benefits that much, though. Closest I can think of is image processing.
So in the real world, anywhere from 'no benefit' to 'double the speed' depending on application.
It's in the same package, but not made in the same silicon or process. The package contains several pieces of silicon. Look at it as a miniature circuit board with several individual chips on it.
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This is making me feel old as I recall how happy I was to have once maxed a board with 32 MB of RAM, a previous one with 8 MB, another with 4 MB and so on. I love that about technology, it pretty much always gets better until DRM and politics get into the mix...
128MB L4 cache. [...] on-package (not on-die) pool of memory
what this means is the memory is not on the same piece of silicon as the CPU, just stuffed in the same chip package. this means they have to be connected by a lot of tiny wires instead of being integrated directly. the downside to this is that there is bandwidth between the L4 memory and the CPU is very limited and it uses more power. like AMD's first APUs where just two ICs on the same chip, i dont not think this will result in a drastic performance improvement but i'm unsure of the power savings. If AMD gets wise, they will beat Intel to the punch but then again. though if AMD is really smart, they would put out ARMv8 chips not just for servers(/desktops?) but for smartphones/tablets and laptops.
Anons need not reply. Questions end with a question mark.
I'm not an expert by a long shot, but I'm pretty sure that modern day applications don't go anywhere near that low a level and instead leave memory management up to the system.
+1 IDisagreeSoHeMustBeATrollOrAnAstroturferOrAShill
Obviously, what we need is some XRAM.
+1 IDisagreeSoHeMustBeATrollOrAnAstroturferOrAShill
All my algorithm development so far assumes small local caches.
Now I can start over again.
Aaaahhh!!!
Even if the whole files take up more than the cache, the filters and algorithms running on them may need to access only a part of the image/video (e.g. a access a frame of the video multiple times). The benefit of caching is highly dependent on the algorithms used
I may not not get the speed out the caches but when you consider how much RAM is utilized in your laptop, smartphone, etc., this is actually a smart move. More room means means a better way to utilize the RAM allowing other opportunities to exist..
At 1.6GHz, L4 latencies are 50-60ns which is significantly higher than the L3 but just half the speed of main memory.
Don't you mean "but less than half the latency of main memory?"
So as soon as i get one of these, i won't need any DRAM anymore, since 128MB is way more than my typical memory footprint (including kernel and X11)
I do look forward to this.
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CPUs have had streaming instructions for a long time that can tell the CPU to load data directly from main memory to L1 cache and not use L2/L3/L# cache at all. This reduce cache eviction for data that is transient.
128MB of L4 cache and Transactional Memory instructions will make it great for routers.
100mhz DDR3 isn't that much faster for latency than EDO 66mhz, but it does have more bits to charge up and takes a bit longer to find the correct bits. The external bus is a lot faster, but the internal processing speed is not.
POWER8, anyone? With actual SMT instead of flakey HT, and lots more threads, and so on, and so forth.
Too bad they're unobtanium and if not cost too much. But otherwise... anything intel does has basically been done better before. Except process. That is the only thing they really lead with. The rest isn't half as interesting as most of the world makes it out to be.
Even the 6MB of L3 that modern processors have is larger than the entire system memory of our parents' first computers.
A 6 MB L3 cache is bigger than the RAM in the PlayStation, Nintendo 64, or Nintendo DS. A 128 MB L4 cache would surpass the RAM in a PlayStation 2 and an original Xbox combined. You don't need a lot of DDR to play DDR, even if you live in the former DDR.
0.128 bits does tend to be smaller than most caches.
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Formerly, L4 cache was main memory, a cache for the L5 (disk) and L6 (network). This new L4 cache pushes main memory, disk, and network out to L5, L6, and L7 respectively.
Round trip time for an old school EDO DIMM is not the same thing as the burst cycle time of a synchronous dram. It take about the same time to get going, but the data bursts faster and wider.
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Interesting that the gigabit Ethernet controller on the latest Apple Mac's have 512MiB of DDR3. Any idea what this is for?
No idea. I was under the impression that most NICs have just enough onboard memory to buffer potential bursts of data, but otherwise write to system memory via DMA and interrupt the CPU to notify it when the data is ready. 512MB sounds like a lot of buffer for just a 1gb NIC.
Did your 128 MB laptop continue to run Windows XP well even after having installed the service packs that increased how much RAM it uses? Even under Windows 2000, printing certain documents filled RAM on my old 128 MB desktop PC.
With Intel's 14nm so close, and 10nm production in another year or so, they need to use all that chip area for something that doesn't necessarily generate a ton of heat. RAM is the perfect thing. Not only is the power consumption relatively disconnected from the size and density of the cache, but not having to go off-chip for a majority of memory operations means that the external dynamic ram can probably go into power savings mode for most of its life, reducing the overall power consumption of the device.
-Matt
Closest I can think of is image processing.
What you've quoted sounds more like a case for random accesses. Trees, graphs (!), and other complicated data structures, I'd guess. I believe that image processing can take care of itself most of the time by simple prefetching.
Ezekiel 23:20
No one ever needs more than 640KB. :P
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All these are cheap and worthless improvements! We need faster CPUs - 8GHz for single-core this year and 16GHz next year!
eDRAM may be many things, but cheap isnt one of them.
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Let's face it, SRAM isn't tiny, it leaks amps like a sieve at the tiny process size that everything is done at now days, and it's main advantage is that it doesn't take a controller to access and it's bloody fast and the bandwidth can be pretty sizable.
Then perhaps MoSys had the right idea: make a bunch of small, independent DRAM blocks and a front-end controller with as much SRAM as one block to hold cached results while waiting for the corresponding DRAM row to refresh.
Actually, that amount on a NIC would be a great boon in keeping all network processing on the NIC instead of having to CPU/system memory-offload, especially when you turn on the bells and whistles like jumbo frames, etc. I can also see it helping out quite a bit when processing HD video packets when streaming video where it's pretty important to get them processed as quickly and efficiently as possible before passing them off to the main system. These packets tend to have a decent amount of overhead, etc and being able to process quite a bit of them at once due to increased RAM on the NIC should help quite a bit smoothing out the entire process.
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Yes and no. Applications can't typically "put things into the cache", but algorithms can (and often are, when it comes to image processing) tuned to suit a particular cache size. Processing the image in an appropriate order, breaking the image into cache-sized chunks, and so on can all be effective strategies which pay off big-time in terms of performance.
I have a Retina MacBook Pro with this Crystal Well processor. What advantages does it really bring?
Unsure of any real world benchmarks compared to standard Haswell processors.
I've written papers on the effect however I am unable to share them here. The bottom line is the application should be exposed to reduced minor page faulting and, if all goes well, improved context switching, all dependent on the way the CPU scheduler is configured - of course.
IMHO an L4 cache will alleviate the cache miss penalty when the CPU Scheduler looks for data in L1-3 however any increase in the penalty due to a cache miss will be highly dependent on the application and the way the CPU scheduler is configured.
The idea is to try and keep the L1-3 Cache as hot as possible, really it's because as programmers, many of us still have a long way to go to writing code that scales to parallel processing well (in the 21st century!!!) plus there is a lot of code out there already.
For Linux and Apple based systems (I can examine the code of these CPU Schedulers - just not the Microsoft as it is proprietary) this should mean that the amount of time the CPU spends on application tasks, as opposed to O.S tasks is increased, essentially boiling down to reduced application latency and improved "responsiveness". I don't mean to use such wishy-washy terms however at this level cpu instructions are carried out in the nano-femto second range and the duration imposed by a cache miss penalty and a context switch will also be dependent on the ram installed - which is another factor in the duration of a minor page fault.
Assuming that the schedulers, in a "fair and balanced" configuration I expect the following. For code that scales to parallelism you should see improvements because a task will exist on multiple cores well and not incur penalties for hogging CPU resulting in the L1-3 caches staying hot with application data longer (ideally, with threads running on multiple cores). For code that doesn't I expect it to hog a core, get pushed back to ram by the scheduler and be exposed to all of the performance penalties that come as a result.
Personally I have always thought it's a contest between Cycles and Cache - not a direct effect on battery life or power consumption however if the CPU is spending more time on application than OS then you are closer what the original Amdahl's law sought to show - if your application allows it.
My ism, it's full of beliefs.
I don't doubt that it either does or will have uses beyond graphics, I just find Intel's marketing, labelling, and packaging choices utterly inscrutable if non-graphics uses are actually ready for prime time.
The only sign, unless you delve into the part numbering alphabet soup, that you even have it, is a change in the designation of the graphics "Iris Pro 5200" vs "Iris Pro 5100", and it's only available in the highest-price laptop parts. I have no reason to suspect that it'll hurt performance on the CPU side; but if that is what "Intel touting the advantages of giant L4 cache for demanding CPU Workloads!" looks like, they certainly are low key about it.
I'll be interested to see if Xeons eventually get some, or if the stuff starts showing up on Intel NICs or anything; but the current generation just doesn't look like a very enthusiastic push beyond pure graphics uses.