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Will 7nm and 5nm CPU Process Tech Really Happen?
An anonymous reader writes "This article provides a technical look at the challenges in scaling chip production ever downward in the semiconductor industry. Chips based on a 22nm process are running in consumer devices around the world, and 14nm development is well underway. But as we approach 10nm, 7nm, and 5nm, the low-hanging fruit disappears, and several fundamental components need huge technological advancement to be built. Quoting: "In the near term, the leading-edge chip roadmap looks clear. Chips based on today's finFETs and planar FDSOI technologies will scale to 10nm. Then, the gate starts losing control over the channel at 7nm, prompting the need for a new transistor architecture. ... The industry faces some manufacturing challenges beyond 10nm. The biggest hurdle is lithography. To reduce patterning costs, Imec's CMOS partners hope to insert extreme ultraviolet (EUV) lithography by 7nm. But EUV has missed several market windows and remains delayed, due to issues with the power source. ... By 7nm, the industry may require both EUV and multiple patterning. 'At 7nm, we need layers down to a pitch of about 21nm,' said Adam Brand, senior director of the Transistor Technology Group at Applied Materials. 'That's already below the pitch of EUV by itself. To do a layer like the fin at 21nm, it's going to take EUV plus double patterning to round out of the gate. So clearly, the future of the industry is a combination of these technologies.'"
Could someone explain to me why further refinement of fabrication process is the only way to progress? With a car analogy?
Silicon atoms are 0.2nm wide. We're getting into "why aren't you just directly pushing the atoms around with atomic force microscopy?" territory.
Clearly e-beam has some serious issues (throughput, to name one...), but progress is being made on that front. For instance, http://www.mapperlithography.c... ( http://nl.wikipedia.org/wiki/M... -- though it appears there's only a Dutch entry...).
The answer is yes.
This seems highly technical which is great. I would say at best these issues are 5 years out. Plus, stacking processors + making them larger is always an option. The margins on processors can be slim at the low end, to many fold at the top. The manufacturers will have to learn to live on leaner margins all round.
By the time awareness filters down to the semi-technical press like /., it's pretty much old news. Lithography has been running into bigger and bigger challenges and that has been behind architectural changes like multi-core systems, the re-emergence of specialized co-processors (e.g. GPGPU, FPGA ), and, most recently, embedding of FPGAs on Xeons from Intel. There's been some speculative talk about directly providing some configurable logic (basically a FPGA) merged into the processor to allow creation of custom instructions on the fly.
The future is hardware; learn a HDL today.
Last time it was leakage would prevent us from breaking 65nm. Before that it was lithography wouldn't get us below 120nm. Something will happen like it always does.
i remember in the 90's everyone swore it was impossible to go under 90nm how 1GHz was the maximum speed you could get
I'd say the low-hanging fruit disappeared a few decades ago. Continuing down the feature size curve has for many years required a whole slew of every-more-complicated tricks and techniques.
That said: yes, going forward is going to be increasingly difficult. You will eventually reach an insurmountable limit that no amount of trickery or technology will be able to overcome. I predict it'll be somewhere around the 0 nm process node.
I worry about the reliability with tinyer and tinyer CPU feature size. ...how will those CPUs be doing, reliability-wise, 10yrs later?
When I buy something 'expensive', I expect it to last at least 10yrs, and CPUs are kinda expensive, to me.
(I still have an Athlon Thunderbird 700MHz Debian workstation that I use, for example, and it's still reliable.)
Uh, Linux geek since 1999.
That's just not good enough. Let's cut to the chase and use straight-up gamma rays. Then we can complain that atoms are too fat.
Why don't we use smaller architecture in larger dies, so that we have higher densities, and higher speeds? Also that wouldn't that allow room for more cores and cache.
Because whatever you do in the computing world, you are affected by processing power and cost. Growth in these regions drives both new hardware and new software to go with it, and any hit to growth will mean loss of jobs.
Software (what most of us here create) usually gets created for one of two reasons:
1. Software is created because nobody is filling a need. Companies may build their own version if they want to compete, or a company may contract a customized version if they can see increased efficiency or just have a process they want to stick to. There used to be a lot of unfulfilled need out there, but this demand is much sated in the 21st century.
2. Software is created because a company desires increased performance/new features (basic need is filled, this is a WANT). Once a new processor/feature becomes available, you either wedge it into existing code. Or, if it's a massive enough of an improvement, you create entirely new software enabled by the new level of performance-per-dollar.
Without continued growth, the industry is in danger of cratering because there's only so much processor architecture optimization you can do in the same process node, and the same goes for optimized libraries on the software side. In addition, brand-new industries enabled by cost reductions (e.g. digital FMV explosion in the 1990s, or the movement to track your every move in the 2000s) will no-longer be so common, and that will again force people to look elsewhere for employment.
Software engineers won't disappear, but they will be culled. The industry has not had to deal with that yet in it's entire history, so it will be painful. I'm hoping they can hod this off for as long as possible!
Man is the animal that laughs.
And occasionally whores for Karma.
There are a number of factors that affect the value of technology scaling. One major one is the increase in power density due to the end of supply and threshold voltage scaling. But one factor that some people miss is process variation (random dopant fluctuation, gate length and wire width variability, etc.).
Using some data from ITRS and some of my own extrapoliations from historical data, I tried to work out when process variation alone would make further scaling ineffective. Basically, when you scale down, you get a speed and power advantage (per gate), but process variation makes circuit delay less predictable, so we have to add a guard band. At what point will the decrease in average delay become equal to the increase in guard band?
It turns out to be at exactly 5nm. The “disappointing” aspect of this (for me) is that 5nm was already believed to be the end of CMOS scaling before I did the calculation. :)
Incidentally, if you multiply out the guard bands already applied for process variation, supply voltage variation, aging, and temperature variation, we find that for an Ivy Bridge processor, about 70% of the energy going in is “wasted” on guard bands. In other words, if we could eliminate those safety margins, the processor would use 1/3.5 as much energy for the same performance or run 2.5 times faster in the same power envelope. Of course, we can’t eliminate all of them, but some factors, like temperature, change so slowly that you can shrink the safety margin by making it dynamic.
Given how long it's taken TSMC to get past the 28nm node, I'd be surprised if we even make it into the teens. The main problem seems to be heat dissipation. Fabricating the chips is a solvable problem that I think we will be able to overcome quite readily. Making these chips stable, viable, faster than what we have now, and cheaper or at least the same price, is an entirely different proposition altogether.
Guard bands sound like sloppy design.
An interesting article here discribes the horrendiously difficult challenges that face EUV:
https://www.semiwiki.com/forum...
The problem is that memristance effects begin to manifest below 5nm
Thus, start using memristors to build IMP-FALSE logic circuits.
I'd say the low-hanging fruit disappeared a few decades ago
In an absolute sense, yes. In a relative sense, some fruit will always be lower than others.
That that is is that that that that is not is not.
More miniturization equals greater reliability, because smaller components always do better at surviving shock and vibration than larger components.
That that is is that that that that is not is not.