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New Intel 8-way Chipset
VJ writes "Intel just announced their new 8 way SMP chipset for use with PentiumIII-Xeons. A summary of features: 3X100 buses (2 for CPU's, and 1 for I/O. (The chipset appears to function to some degree as a crossbar switch, between the three buses) Cache coherencey features allow better utilization of L2 cache, other stuff too..) We'll have to wait and see, but this might be a relatively cheap way to get raw CPU for enterprise environments.. (Relative to Sun or HP or SGI)"
WHat's wrong with using 64 bit pointers? And why would you have to recompile? Isn't it possible for the kernel to recognize both kinds and translate them accordingly?
I do agree that the segment stuff is a big and horrible hack rather then a real solution.
___
If you think big enough, you'll never have to do it.
They could use OS/2 Warp Server.
It is available NOW and can handle up to 64-CPU and claims to be optimized for 8-CPU.
The scaling is terrific. Just a bit below 1:1 linear beyond 2 and 4 CPU.
Actually, you are right on the money. The EV6 architecture uses a 100MHz clock, but sends data on both the rise and fall if the line signal.
:)
What this really accomplishes is the ability to send twice the amount of information of a "standard" 100MHz BUS. The 200MHz name is technically wrong with regards to clock signal, but right with regards to data transfer speed.
Bottom line is that regardless of what it's called, it's still faster than my PIII-450 bus and I want one
Never underestimate the power of stupidity in large groups
LOAD "SIG",8,1
LOADING...
READY.
RUN
Unless they've changed recently, Intel's always seemed to use Unixware for their past SPEC runs. I see no reason they'ed switch to Linux for this (given the 8 processors of the system).
Actually, the EV6 bus is currently running at ~333mb/s/pin in most current 21264 based systems. AMD is currently only running it at 200mb/s/pin in their current designs. So AMD is actually running the bus below spec so to say even.
I think that by looking at the results on intels page you can see that it's not going to be the great performance increase everyone (at least myself) was expecting. I mean with four Pentium III Xeon processors at 500MHz they were getting 25,065 transactions per minute (tpmC)and using eight Intel Pentium III Xeon processors running at 550MHz they got 40,013.3 tpmC which is nearly a 1.6x gain in performance. This was taken from intels website at http://www.intel.com/tech/work/server/eight.htm?ii d=mail+tw27& Now if I buy twice as many processors I want at LEAST twice the performance. No??? Or I am I just confused???
Yes. 100 mhz double pumped = 200mb/s And yes... like I said, they should be able to go up to around 200 mhz double pumped = 400mb/s Didn't realize though that the limit was more like 333mb/s. I'll have to check that out.
Actually, DDR Sdram has nothing to do with the speed of AMD's implementation of the Eve6 bus. They are two seperate things. =)
"NT will do it; Linus (and therefore Linux) won't." Go read the linux-kernel mailing list and find the thread on Andrea Arcangelli's (and some other guy from Siemens [I think] who's name I can't remember; SGI has been working on similar stuff, too) bigmem patch. It's not such a hideous hack, and it looks like Linus (and therefore Linux) will use it.
this may be good for vmware. Imagine being able to tell vmware that each OS has 2 processors, and then running win NT and Solaris on top of Linux. 2 procesors for sun 2 for NT and the rest for Linux :-). Ahh to be able to surf the web, use the webcam, and have other OS'es working for you in the background :-) oh the power if nothing else just to have that kind of computing power at home. :-) drool
Only 'flamers' flame!
Well, two avis, but you're got a point. Perhaps some info about the two movies. They are 29 fps with sound and Indeo5 encoding. Be's Indeo decoder is most likely straight c or c++, so of course it's a bit slower than it could be.
:)
The previous reply is right too. Unused cpus are wasted cash.. but then, that's what rc5 is for right?
You would too... transmission lines are hard to deal with. AMD is smart enough to understand that:
If you build it, they will come. (But only if it's cheap)
The engineers at digital understand this (sorta), but their principal target is not the $2000 machine.
... recently released not too long ago.
The Athlon is an impressive chip. Let us wait till the end of October to decide which company (Intel, AMD) has the bigger balls and better staying power!
By then, AMD will have their Server and Enterprise Editions (smells like Win2K) and their motherboards with SMP and all that mess.
Keep also in mind that the baddest motherboard makers (Tyan, ABit, AOpen, etc.) will be releasing motherboards for the Athlon.
If Tyan made a board for the Athlon that is similiar to their Thunderbolt for Intel... [official drool]
ChozSun [e-mail]
ChozSun
ChozSun.com
It meant Intel compared to HP Sun etc.
No it can't support celeron (its slot2)... and it shouldn't. Anyone who needs 8-way proccessing (1)can afford the damn xeons and (2)would never stand for celerons. The point of the xeon is (1)big-ass cache and (2)error correcting/reliability. A celeron system (esp. overclocked) is nowhere near as reliable as a xeon and never will be (it's just not meant to serve). No, having the 8-way set be for xeon only is wise.
There comes a time in every man's life when he must say, "No mother! I do not want any more Jell-O!"
I think Intel uses some Solaris x86 internally. I think this is probably one of the few x86 OSs out there ready to scale to 8 or more.
> If only AMD could get their disk I/O chipesets et. al. in better shape...
it doesn't sound too bad to me... supports UDMA/66...
OS/2 scales very well to 8 CPU's - way better than NT or Linux do. For years, OS/2 has been able to scale well to 16 CPU's.
Linux will run well, if your aren't using all 8 processors to drive I/O and the machine/memory interface can keep the CPUs fed. Assuming the machine supports SMP, then Linux will do a wonderful job with user space applications. If you need to drive 4 100Mbit Ethernet cards, such as Microsoft seems to think runs the world, then Linux 2.2 may not use all 8 CPUs. Bottom line, SMP is hardware's answer to an application problem. Just like integer, floating point, and video performance. Linux plays a part, your application play a part. Those that can use 8 CPUs wisely know who they are.
I can just see the big fat price tag to go with machines based on this chipset/board..
I mean, you'd be better off adding more machines and designing your apps to balance the load across machines.
I believe it's called DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory Now We Can Really Make A Case For Using Acronyms). Also, I was under the impression that EV6 had variable clock speed and simply referred to a particular design. Is this incorrect?
This is not meant to be critical of the wonderful people who have contributed to making Linux what it is today, but... I am skeptical that Linux, under its current development model, will be able to scale for use on large SMP systems.
Consider that the big boys Sun, HP, IBM, SGI (for now) all build large smp systems themselves, hardware and software are developed in house with careful communication between hardware and software designers.
These companies have multi-million dollar labs with dedicated staff that analyze the performance of their machines and incorporate improvements. Hooks are built into the software and hardware that allow engineers to peer into the inner workings of the OS, cache, memory bus, and IO while the systems are under load.
The fact is that Linux is a superior operating sytem for small systems because the inner workings of these (small) systems are well understood and Linux has nicely incorporated many of the best ideas. In contrast, the inner workings of large smp systems are chaotic and poorly understood. All the elegent design theories and clean coding are not substitute for oscilloscopes, software tracing and continual prototyping. While underestimating Linux has been the downfall of many a pundit, I believe this is one case where the doubters may be right.
...imagine how fast that would be ..it would SCREAM!
So, expect to be buying those big cache Xeon chips. A Xenon, 500, 2MB = $4000
$32,000 in chips.
all most of you seem interested in doing is trashing microsoft.
can't you even bother to go to TPC and look up the facts?
click here to read the summary report
The corollary people were doing 8 way multi-processing back in teh days of the 386 processor.
Intel bought them out almost 3 years ago.
Good to see their knowledge is still being used.
This stuff has been in the pipe for a long long
time. It appears that large corporate customers have been testing it since February - and they did not test it as
a file and print server. We are talking serious stuff here, no funny small web server, but SAP R/3 and the like. The stuff you run a large company on.
Do you really believe a Company like Compaq would
come up with an Intel box with TPC-C numbers as high as these as an answer to some AMD pre-release info?
Getting these numbers means squeezing these boxes
to the limit, and that takes weeks, and a lot of
nightshifts... would be a rather large effort. Believe me, this is a serious architecture, and not at all comparable to the PentiumPro 8way
(not scaling at all) that used to be around a year ago.
And yes, you are absolutely right on the bandwidth
issue, but keep in mind: The core of this technology is not the single bus, it is the high-speed crossbar switch (Profusion) that sits in the middle of the architecture. read the specs: It actually has ten unidirectional ports that appear as five bi-directional ports. With the 100-MHz buses attached, there is a peak throughput on each port of 800 MB/s. With all five ports, the crossbar switch allows a maximum peak throughput of 4.0 GB/s. Ok, that's theoretical - as is the EV6 stuff.
Wrong actually you can't even expect at MAX double. I'll have to look up my parrallelism courses to give you an equation, but even if you rewrite every single app to use the processors you'll NEVER get linear increases.
This is correct. Intel seems to have made a half-hearted switch to a crossbar bus system, with the result that their bus can still be easily saturated. Programs that aren't memory-intensive will still benefit from the SMP. Programs that are memory-intensive will saturate the bus and leave many of the processors idle.
It'll be good for Quake III, but I suspect anyone in the know will probably stick with a RISC design.
Memory performance has nothing to do with whether the processor is RISC or CISC. Memory bus design is the only thing that matters here. Point-to-point implemented on a crossbar bus beats a shared bus no matter what chips are used.
Getting back to the Holy War, most modern implementations of CISC are almost as efficient as RISC (look at the guts of the K7 design for an example). You wind up with an extra stage in your pipeline for decoding, and that's about it. RISC is generally favoured because there's no real reason to use CISC any more (higher code density isn't as vital), and removing CISC support simplifies chip design and optimization.
The main problem with Intel chips is that they've been repeatedly extending a design that wasn't designed to be extensible, in a rather kludgy manner. They're still stuck with it, because if they switch to a completely new architecture they lose their installed base of customers. This is why the Merced still supports x86 modes.
been there, done that, installed RH 5.2 on it, got nearly 4k bogomips.
the joys of working with pre-release product.
der dee der.
I want more info though...
Just because you disagree doesn't make it offtopic or flamebait.
Its an Intel Corollary ("Profusion") chipset using Intel chips. Compaq et al are shipping them starting this week: http://www.compaq.com/products/servers/technology/ 8way/index.html
AMD SMP? INTEL SMP? Which one, why them, how much, or is this just really good PR?
In a word: BeOS!
how long before linux can run (well) on such an architecture?
Synergies are basically awesome, and they're even better when you leverage them. -PA
Any idea how Linux will use this much main memory?
A large ram disk for databases?
A larger virtual address space?
or better yet, a _huge_ addition for my "Little Computer People" house. =^]
if you can't keep it fed. A single PIII can saturate a 100MHz bus, putting 4 of them on a single bus is going to kill performance of any sort of memory-bound applications. The big boys usually know what they are doing, HP, Decpaq/Alpha and SGI all know how to keep their processors fed.
The EV6 bus used by Ahtlon and Alpha CPU:s is probably much better for SMP than Intel's bus.
To begin with, the EV6 bus is clocked at 200 MHz whereas the Intel bus is clocked at 100 MHz.
The EV6 bus is also a point to point architecture, not really a bus in fact. The drawback is that the motherboard is more difficult to design.
I was unable to find any mention of what OS was used for these benchmarks. Realistically, only SCO or Linux seems probable (since the application in question is Oracle8), and I do not know whether more recent in-house tuning has allowed Linux to scale past 4 CPUs on x86 machines. But as of a few months ago, NT and Linux both went from near-linear scaling to a near-plateau beyond 4 CPUs, so I am wondering if they didn't use SCO.
Regardless, it's odd that they don't say.
Remember that what's inside of you doesn't matter because nobody can see it.
Here are a couple of screenshots:
http://www.isk.kth.se/~eb99jolu/
There isn't really a way to reprogram the cpu to act like a new cpu. Other than the chipset, socket layout, power supply and software issues, the instruction decoder only understands the instruction set for one chip type, the microcode can be done differently depending on how the chip works, eg: AMD v Intel, but it can't make the x86 instruction set look like the sparc instruction set. Even if you turned off all of the non-essential instructions it still wouldn't be RISC, it would be CISC with a lot of wasted space. RISC is designed from the ground up with smaller arithemtic/logic units to run at higher clock rates. It also uses the higher speeds of internal cache to avoid "slower" ram intensive operations.
The intel assembly language is horrible to program in. I've had an easier time writing assembly code for a Vax than trying to get anything to run on x86. Its basicaly the 10th generation of new stuff slapped onto old stuff with backwards compatability. The segment registers are all worthless with a 32 bit adressing register. The lack of a large number of register such as on an r6000 or ultraSparc make the chip very memory intensive, it can't page registers after a context switch. So intel just spends most of its time waiting for the memory bus to get back with the data instead of doing actual calculation.
The best way to squeeze out more calculations per clock cycle are by overclocking or redesigning the chip, trying to one-up Intel's microcode, assuming you could even get access to it and had the ability to reprogram it, would most likely just make it run slower because you don't understand the system as well as they do.
A computer doing 8 times as much nothing as before is still doing nothing. BeOS. Give me a break. Why not develop for Amiga M68k, they've got more users and more apps.
I would like to add that Celerons can't do 8 way and 4 way for that matter .. the most you'll get out of that PII core is dual..
Same goes for "real" PII and PIII chips, they can do dual at most..
Xeons and PPo's can 4 way and up..
But I'm not sure if going "intel" is such a good idea if you need that many cpus, SGI, Sun, and Digital/Compaq seem much further along in that area..
There aren't any so far as I know. Are there quad athlons available? How about dual? What about an Athlon single CPU machine? They don't exist.
They will, sure, but corporates trust Intel, just as they trust Microsoft and they used to trust IBM. It's going to take more than just a flash in the pan to jump over to Athlon servers... Show successive generations widening the performance gap vs. Intel, and IT departments will bite. Until then, you'll probably see them drop them by power-user desktops asking them to check them out and let them know if there's anything funky about them.
I know I'm going way off topic here, but bringing AMD into this does them a great disservice, being that they're not equipped at this point to take on this market segment.
What part of raw CPU is it that implies need for >32GB memory? Or >4GB, for that matter? ;)
There are plenty of tasks that require lots of CPU but will do quite fine on a 32 bit platform. Like, say, compiling kernels.
So where are people supposed to get eight-way (or four-way or two-way) Athlong motherboards and systems? The Profusion is out now, Athlon SMP is expected to debut on the market next year, from what I've seen.
What good is a massive power server if the protocols for sharing/managing it aren't there?
- bridgette
Why pay $100,000 US for an 8 way Intel system when one can get a Sun Box with the possibility of more CPU's, a proper bus, and just as many applications. When I say applications, I mean the kind (High end db, video. .. )that people with this kind of money and need use.
:)
my 2cents
---- aut viam inveniam aut faciam
that is, 50% improved performance on an online transaction processing benchmark when growing the number of processors by 100%:
/MSSQL7.0) 26,560.40 /MSSQL7.0) 40,013.30
Compaq ProLiant 8000-550-2M (Pentium III Xeon 4 CPU 550 MHz 2 MB cache NT4SP4
Compaq ProLiant 8000-550-2M (Pentium III Xeon 8 CPU 550 MHz 2 MB cache NT4SP4
Of course with TPC-C, systems are obscenely expensive since they configure them with so much disk that the system won't be I/O bound. But this looks likely to be an NT marketing bullet. Prepare your responses now!
--LinuxParanoid
(Hey, just because we're paranoid of Microsoft doesn't mean they're not out to get us...)
Call me crazy, but won't this actually be slower? I mean, putting that many chips on the same bus ... even if you do sync in the manner they're talking about, that doesn't help much when you're working with large volumes of data, or multiple programs requiring large volumes of data. What do I think? It'll be good for Quake III, but I suspect anyone in the know will probably stick with a RISC design. Incidentally, anyone know why intel chose to go with a mode-bit, instead of adding an MMX coprocessor? I've been looking over the R3000+ processors for the first time, and I'm starting to get the impression that intel chip design is really messy. Come to think of it, (and sorry to get so off topic, but..) is it possible to re-code the micro-ops in a CPU? Ie; the AMD K6-3 uses micro-ops to simulate the original intel commandset. Is it possible to reprogram them to simulate other CPUs? And even if it were possible, could you squeeze any more cycles out of the CPU that way, or would you only end up with a reduced instruction set? James -- http://chat.carleton.ca/~jhelfert
'seems the 8-way is the sweet spot that AMD has been pusing in their pre-release info.
'Intel pull this off now so AMD has some competition?
Anyway, if the hype of the EV6 bus and its multiprocessor capabilities for the Athlon are true, Intel's 8-way systems probably won't keep up. The data bandwith just isn't there. If only AMD could get their disk I/O chipesets et. al. in better shape...
My question is can it use slocketed celerons? I'm looking to piece together one cheap server, and 8 celeron 366's is probably a better investment than one xeon. Especially with the overclocking possibility. This seems obviously to just be a "We're better than AMD again!" ploy anyway, because it just pieces together 2 weak busses in a sorry attempt to roll out the next generation before anyone else. (But two 100 mhz busses would be well utilized by 8 66mhz bus chips.)
Crawl back in your grave, troll.
So when will we be able to order 8-way systems with this chipset from our favorite Linux hardware vendors?
Penguin has been offering 8-way systems for a while using another chipset solution, but the price for those systems is over $100,000, while 4-way systems are more like $12,000, last I checked.
We'll have to wait and see, but this might be a relatively cheap way to get raw CPU for enterprise environments.. (Relative to Sun or HP or SGI)"
Silly writer. Those machines have 64bit CPU's. This chipset isn't for the upcoming merced.
You can boot off the serveRAID thing. We did. Contact bdragoo@thomasaquinas.edu for more information about booting off the Netfinity's serveRAID.
Fellowship 9/11
I could cluster my home PCs to run Beowulf. But that doesn't matter because I've nothing to run on it.
Have you?
Beowulf is neat, but I've yet to see a killer app for the home user or hobbyist. (Those were never the targets, but...)
Just wondering because everyone seems to regard Beowulf as the greatest thing since armpit hair, and I'm sure not everyone has an app for it.
Just wondering because everyone seems to regard Beowulf as the greatest thing since armpit hair, and I'm sure not everyone has an app for it.
If armpit hair was a great thing.. or a bad thing.. or something to compare Beowulf clusters to. (and no, I'm not being one of those people that you're speaking of that regards "Beowulf as the greatest thing since..."). I'm just saying that, hmm, body hair and hard ware.. interesting mix.
Insert mind here.
OK, so run MOSIX so processes will the automatically scattered across the cluster.
When I was assembling 7000 M10's a little while ago, there was a special program where for a few bucks you could upgrade your machine to 8 way when the new board came out.
My problem with Linux under the Netfinity was that ther serverRAID adapter would not work (I believe that they have release a driver now, but it's not bootable)
I'm kinda curious how 8 processors fit into the new assembly - Are the voltage regulators gone?
Hitachi has been shipping a Profusion-based eight-way server for more than six months (they were an original Corollary partner). They do plan Linux support. They also have an improved implementation, with faster memory transfer (1.6GB/s vs. 1.3GB/s). Take a look at http://www.hds.com/
What the hell?
Hey, I know AMD doesn't have a lilly white past, but this is ridiculous. If any company wants decent SMP performance at a 'relatively' cheap price ( again, compared to the -=real=- heavy chips ) then Athlon is the only choice. Any corporation that would choose Intel over the Athlon High End series either has a special deal with Intel, or an uninformed IT department.
"I could float off the floor if I wished to. But I do not wish to because the Party does not wish me to." - Abridged,
wouldn't you have to store that kind of system in a meatlocker to keep it from burning up?
---Got Coffee?---
You should visit it after you post..maybe reload the page you got "first post" on. then perhaps you'd see you didnt even get first post. and you just wasted the effort and bandwidth.