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Socket Athlons by early next year?
webslacker writes "That's what it looks like, according to the private eyes over at Sharky Extreme. The Athlon Select series, as it will be called, will be aimed at the low end and will use a new ZIF standard called Socket 423 (the number of pins). Oh, and get this... plans are being laid to integrate an 8MB L2 cache. "
yup, i've got a Athlon 600mhz with a MSI motherboard, and it sure kicks ass! i live in sweden and there was no problems getting one, i ordered it the same week it was released, took about a week and then i was in heaven.... although, i don't know how the situation is overseas or if you can get on over here anymore, i just know i'm one of the lucky guys who have one.... ;)
i read some previous post about someone who were afraid of upgrading due to compability issues and i just wanna say go for it! don't wait, there's no such things as incompability, show AMD your support right away! demand motherboards from manufactors! this is AMD's first and also final chance to stand up against intel, and we all need this competition as consumers.....
/Rikard
Is anyone actually running on an Athlon? I've heard that it's difficult to get one.. (This is not FUD mongering, just an honest question).
OK, admittedly it's been a few years since my last computer architecture class, but isn't 8 MB drastic overkill? Most performance boost is achieved with the first few KB. The old "knee" in the curve was 8 KB. We're way beyond that now, but what kind of application would get much benefit from an 8 MB cache over one of 1 MB?
No, Socket 370 and Socket 423 in this context only refer to the physical connector, not the signals that pass through it.
Once Intel and AMD are using the same socket type, it would be theoretically possible for a mothboard to support both Intel's bus and EV6, but I personally doubt it will be practical.
- A.P.
--
"One World, one Web, one Program" - Microsoft promotional ad
"Remember when the U.S. had a drug problem, and then we declared a War On Drugs, and now you can't buy drugs anymore?"
CPUs are commodity items nowadays; your arguement might have been more true 2 years ago.
- A.P.
--
"One World, one Web, one Program" - Microsoft promotional ad
"Remember when the U.S. had a drug problem, and then we declared a War On Drugs, and now you can't buy drugs anymore?"
Supporting different electrical characteristics could be done with the chipset, i.e. minimal extra production cost. Supporting two different sockets is a whole other story
I think they mean "integral" as in "it's inside the cartridge somewhere", not "it's on the die".
-lee
I think your fears are unfounded....but that's just my opinion.
Werd.
Is there any good reason why they couldn't use the same socket as the Celerons? Are the busses too different to allow them to work on a Celeron 433-compatible board? I don't like the concept of buying a motherboard which locks you into a specific processor. I think that both companies and definitely the board manufacturers would be better off if AMD / Intel / Transmeta / Joe's Chip Manufacture could all use the same set of sockets.
Just what we need to fragment the market a little further...another bloody CPU mounting standard.
Can't the DoJ do something useful like limiting Intel's ability to define a standard CPU connector, then deny other manufacturers the ability to use it?
And anyway, if the Intel CPUs work in either a Slot1 or Socket370, why is it that the AMD Socket version of SlotA (which is physically identical to the Slot1) needs 423?
And another thing (hic)...
This sig left unintentionally blank.
The PPro was 0.35um, but the level 2 cache wasn't on-die. There were two dies in the PPro package. On the other hand the L2 was on a single die (just not the same die as the processor), so it's quite impressive. At that price they didn't have to get a very good yield.
The jump from Socket 370 to Socket 423 will only occur after 733mhz.
Am I right or does this article imply that Intel will migrate away from their own architecture, and begin to manufacture chips which will run on socket 423? This must be some kind of mistake. This means that AMD or Alpha failed to legally lock-down their bus from Intel... either that or the article is just wrong.
Oh well, if it is right, then it will be nice to have both chips running on the same motherboards again.
If money is not a problem, you can design a computer without cache. That is, where the whole main memory is already made of the fastest memory available (done in some Cray computers, iirc).
A rule of thumb for a good hit rate is to get a cache size of 1/32 of the size of the main memory, so it is normal that cpus come with bigger caches since main memory sizes are expanding exponentially...
I'm just guessing here, but maybe some of those top-o-the-line Sparq stations ;`)
Wow!
... why spend $10G CDN when I don't have to?
Now with a fast bus ( EV6 ) and a fast chip ( Athlon ) with a nice, large L2 ( 8MB! ), the future looks as though there might be little difference between "Workstation" class machines and "PeeCees".
I was considering buying an Ultra 5, but with this news, I may wait
The x86 is dead! Long live the x86!
The fact that no one understands you doesn't mean you're an artist.
For Intel, the reason for changing socket / slot is anyone's guess :)
...
... or a PowerPC ... or a MIPS ... or a StrongArm ... ?
But for AMD, I believe that they CAN'T use the same technology as Intel, since they have a couple important patents on the technology. APIC comes to mind
So if you want to be able to run your Athlon in multi-cpu configurations, you won't be able to do so in an Intel motherboard.
Besides, if you wanted to buy an UltraSparc, you'd have to get a new motherboard
There comes a time when an "upgrade" really isn't worth it. Do you "Really" need that 1-2% increase in performance?
The fact that no one understands you doesn't mean you're an artist.
I have seen (a couple of years ago) a serious article in some technical journal suggesting that it would be better to treat the very fast static RAM technology now used for highest-level cache as main memory and treat the dynamic RAM as a first-level paging device.
This would require some technical changes to allow [suitably priveleged] software to control cache behaviour -- for example locking key kernel pages in cache, but might gain performance thereby. One example of a possible gain would be allowing SMP systems to avoid cache coherence where it's not actually needed, another would be pre-loading pages that a task is known to be likely to need.
You aren't the only one so predisposed.
I refuse to buy any processor that can be confused with a Super NES (a friend of mine says Colecovision) cartridge!
--Ben (real happy k6-3 owner) August
--Ben
It's odd, but I hate CPUs in slot-based cartidges vehemently, and will not buy one. I rationalize this to myself occasionally, but I don't find the reasons I give particularly convincing --- I expect that I'm just emotionally tied to the idea that a CPU is meant to live entirely on a single chip (despite the lessons of history), and "I don't want no crappy chunk of plastic". Yeah, I know, it's illogical.
Still, if AMD or Intel want my custom (and I can't be the only one so oddly predisposed), they'd better crank out ZIF-socketed CPUs. I'm currently on multiple 500MHz socket-370 Celerons, so it was great to hear that AMD will be offering me an upgrade path in the form of socket-423 Athlons. Hooray.
"The question of whether machines can think is no more interesting than [] whether submarines can swim" - Dijkstra
That rumour was started right here on /. iirc. So far the evidence seems to be a sighting of a Transmeta logo at an Amiga presentation, and the fact that one of Transmeta's founders is known to know a lot about chips...
/.
If they hadn't hired Linus, I'm sure the name would not even have been mentioned yet on
Imnsho it would be a good idea to stop mentioning it until there is some real news.
The Good News:
Athlon at warp speeds, with 8MB L2 cache - mmmm, tasty... Since the Athlon bus already runs at 200 MHz, it won't have the "kick in the teeth" impact that the same amount of cache on x86 would have, but it's still nice indeedy.
The Bad News:
The Socket Wars show no sign of abating, as we now get YANDRMD (Yet Another Darned Reference Motherboard Design) to go with:
Socket 7
Slot 1
Slot 2
Socket 370
Slot A
The poor Taiwanese mobo makers must be going nuts! We need Intel to license the bus specs for the P2 architecture, pronto. Scratch that... I don't want to slow down the Athlons to _mere_ P2 speeds! Hah!
- -Josh Turiel
-- Josh Turiel
"2. Do not eat iPod Shuffle."
Some of the new Pentium III instructions can be used to preload the cache with sections of memory. However, I don't remember offhand whether they were 'commands' or a 'hints'...
But for AMD, I believe that they CAN'T use the same technology as Intel, since they have a couple important patents on the technology. APIC comes to mind ...
this is because of the EV6 architecture they borrowed from Alpha - that and in my opinion, slot # is weak... but that's my opinion. blorg.
So if you want to be able to run your Athlon in multi-cpu configurations, you won't be able to do so in an Intel motherboard.
since the above is true - this point is ... well ... pointless. The Point to Point architecture of the K7 is going to make multiprocessing awesome.
Besides, if you wanted to buy an UltraSparc, you'd have to get a new motherboard ... or a PowerPC ... or a MIPS ... or a StrongArm ... ?
Different architecture, different motherboard... it just makes sense after a while.
--onyx--
The high prices of Xeon chips are not due to patents! Fast on die memory cost beaucoup $$s. Also the market - "high-end" servers can cost a ton without people flinching, unlike the desktop market.
Scuttlemonkey is a troll
I use AMD chips for everything. I would never use an Intel chip in any box, even production boxes. The AMD chip gives my the best preformance for price, and the Intel chips don't get close to that same ratio.
The only time I recommend an Intel chip is if someone wants to overclock, and then it's a Celeron. But perhaps in time AMD will have good overclockable chips too, and be "supportive" of the practice.
Anyways, I used a few Cyrix chips, but AMD is the best. Try it a few times, each time you will be more and more convinced.
-Brent--
Hmmm... the via chiposets do have some oddities when it comes to agp (basically if you don't install their agp minidriver your performance either sucks or does not work at all), however under nt with roughly the same config I had no problems after installing sp3 on it. Without service pack 3, agp support in nt does not exist.
I could use a pair of those 600Mhz for my next SMP workstation. It would allow me to run multiple vmware sessions and set up my own virtual lan wiht no slowdowsn on the system as a whole. I'd also be able to do some awesoime graphics and video.
Only 'flamers' flame!
If you re-read the original article, they do state that the low end will use socket 423 and the high end processors will have the 8MB of Level 2 cache. It's not explicitly said that the high end 8MB L2 will still be slot A, but it is clearly implied through boolean logic (you can't be high-end and low-end at the same time). The Slashdot summary is where that difference was lost.
Laissez lire, et laissez danser; ces deux amusements ne feront jamais de mal au monde. - Voltaire
I have been running AMD's exclusively in my machines for over a year now. (Roughly four machines) I love the chips, and I really cna't wait to pick up an Athlon and build myself another machine, but I am sick an tired of one thing. I haven't touched an Athlon yet so I really don't know what the problems I will have with it, but with my K6 2's and 3's I just can't get enough hardware to co-operate.
Latest problem. I bought a ATI Rage Fury. Love the card. I bought it because I used it on a friend's PII. Great frame rate, great textures, but on an AMD that is not the case. Anyone who has K6-2 try this experiment out. Pop a Rage Fury onto your board and load up the latest Q3 test. Good luck. If you are lucky enough to get into a battle map, don't get too happy. Your screen should lock up in the next few seconds. I have tried each and every updated drive that ATI can throw out at me. I already know the simple answer to this. Buy a TNT2. I will be doing that soon, but I don't want to be forced into doing that. Plus I hate the wasting 200 bucks on buying the card when it first came out. OK enough rambling for now.
It is a great chip and I may have to try the socket version once it pops out. AMD does socket well. Plus that 8meg cache is very promissing.
If any hardware developement companies are reading this and haven't fallen asleep yet, please listen to my demand.
Make your hardware with AMD in mind. I'm sure alot of geeks out there will love you for life.
Technology's a battle between companies producing more idiot-proof systems and nature producing bigger and better idiots
Maybe I'm missing something, but why is it better than nothing, if it's not electrically compatible? Unless, of course, you assemble motherboards to sell to yuppies as art to hang on their walls....
Have you ever heard of QNX (http://www.qnx.com)?. They make a kernel for real time systems that is so small that it fits in the CPU's first level cache. The idea behind it is that in real time systems you need responses as fast as possible.
this APIC patent for example, it's the APIC protocol itself that is patented. Yet another case where the US patent system prevents competition and causes inflated prices. (just check out how much a Xeon CPU costs - ridiculous.)
--Coke
8 MB is a misprint, its very difficult to add cache onto a chip and 8 MB would be crazy.
Too bad in a couple of months Intel will be dropping the slot ones infavor of socket 370 PIII. You're method will only really work through the Katmai generation and then your stuck getting another motherboard anyway.
For the price of a 500Mhz G4 you can get a bi-proc 600 mhz PIII.... with a (much) faster card like a tnt2 .... .... *CRUNCH*)
No, I can't spell!
-"Run to that wall until I tell you to stop"
(tagadum,tagadum,tagadum
-"stop...."
Ok, first, this is talk about SOCKET K7s. The current crop are attachet to the MB by a single line of connectors along the side of a board that has the CPU, and L2 cache attached to it. A socket board would be like the socket7 architecture that has served the low end PC world so well. It would be pysicaly similar to the Super7 boards, and the Celeron slotA boards, though there are reasons that they are not compatable. One, is that the overall board architecture that is used is very different. First, there is the 200mhz FSB speed, and then the possibility of 8mb of L2 cache (yummy!), and various more basic differences. Then there is the fact that the connector for the CPU is different. And no, there is no way to change that, aside from re-enginering the chip itself, WHICH WE DON'T WANT AMD TO DO! This would take inordinate amounts of time and money, both for AMD, and more money from you. That said, back to your normally scedualed nonsence.
How about an alpha box running linux?
Ale.
Please ignore.
-- Truth suffers from too much analysis.
This depends on how you implement the cache, fully associative, set associative or what's the other one again?
Direct mapped. But all of them are essentially set-associative, the only difference is the associativity if you think about what 1-way set associativity and N-way set associativity means (where you have N blocks in the main memory).
Overall, a cache will complete it's lookup in one clock cycle no matter how large it is.
Umm, not really. Single cycle access is feasible for the L1 cache for some architectures, but there is no single generalization for that; there are many architectures where cache accesses take anywhere from 2 to 8 clock cycles. Remember they are on a different bus, though.
Zigbee Central: A Zigbee weblog
A cache is not a fix: The cache mechanism relies on the fact that no matter how fast your bus architecture or memory is, there will ALWAYS be a faster memory entity that can be placed closer to the CPU. You might have a 10Gb/s memory bus, but having that kind of technology almost always means you should be able to have an even faster bus if you place it closer to the CPU, simplify the protocol, etc.; and use faster memory.
The current 'bible' of comp. architecture (there are equally good books, but it is the most popular); Hennessy & Patterson's book suggests the following analogy (or similar): When you're working in the library, getting the books that you expect to use from the shelves and putting them on your desk as a "cache" for fast access will be more efficient than walking to the shelves every time you need the books. You suggest that this is a "fix" because you can not walk/run to the shelves fast enough. Then again, even if you can run to the shelves at the speed of sound (or light, for that matter); you will always have a faster access time if you place the books to a place closer than the shelves.
Caches will most likely always be around unless someone comes up with a memory technology where access time is independent of the physical distance from the CPU, and cost is irrelevant (zero). Not very likely to happen in the near future. Actually, we will even see larger caches, check out exciting new architectures like Alpha 21364, Sun MAJC, IBM Power4 etc..
Zigbee Central: A Zigbee weblog
There are a number of applications that don't require any more then the o/s in memory (consider a router/firewall box, or a file server). For these applications having the entire O/S cached would be just the ticket. And as you say, is eminately doable. A good idea, IMHO as someone who does a lot of router/firewall boxen.
On the whole, I find that I prefer Slashdot posts to twitter ones because I don't get limited to 140 chars before
Not in desktop machines... You'd have to buy something seriously expensive, topping 10 Thou probably. The G4 is a beastly processor, badass enough to be restricted from overseas distribution. Linux PPC on a G4 would be sweet....
If MacOS didn't blow shit I'd be using a Mac.
Kintanon
Check out JoshJitsu.info for Brazilian Ji
The article states that Intel plan to migrate from Socket 370 to Socket 423 in the future. Of course, you're still not gonna be electrically compatible, but its better than nothing.
G
were your bad experiences with Cyrix chips? Being a casual reader of some game review sites, I've noticed that a noticable number of games supposedly exhibit problems with Cyrix chips, which require patches to be applied (?)..
I've never heard of that with recent AMD chips. I'm running a K6/166 and have never had any compatibility problems, and this machine runs at a similar speed to a friend's Intel Pentium 200 (non-MMX)
Has anyone seen/had any K6 compatibility problems? I'd be interested to know if they have.
This depends on how you implement the cache, fully associative, set associative or what's the other one again?
Typically (memory) caches in PC's are set associative, therefore making the cache larger wouldn't have an adverse effect. Same number of sets, just a larger associative lookup for that set. All it means is more transistors -> more expensive. Even if you increase the number of sets there is no negative effect, since a cache calculates the area of cache to be checked using the memory address.
Overall, a cache will complete it's lookup in one clock cycle no matter how large it is.
No matter what it looks like, there isn't a
No matter what it looks like, there isn't a
But AFAIK no one has said anything about even 2 so far. ANy more info out there I don't know about?
According to AMD you can expect to see them sometime next spring or summer. At least that was the word about a month ago...
In my book AMD has proved themselves worthy many times over, sure, some of their first chips were a bit sketchy, but even their 486 Dx4 120 chips were pretty nice, and I used linux on them because they were a cheap way to upgrade, I've built many production machines with AMD chips and the only problem I had was when a whole batch of chips (we bought them in quantities of 50) was bad, but this turned out to be because the person we bought them from was out -trying- to screw people over with a collection of bad chips (they werent all from the same batch out of AMD, ie, they were mixed)
Either way, AMD has just as much respect from me as Intel does, maybe more =)
Just because you disagree doesn't make it offtopic or flamebait.
An integral 8MB L2 cache? Doesn't that cause a few problems such as die size? I thought one of the major problems that Intel had with the Pentium Pro was the yield due to L2 cache, and that was with 256k/512k. An 8MB integral cache is going to push the transistor count incredibly high, and thus the yield will plummet and the price will soar. I thought the idea was for a 8MB slot version (external L2) and a low-end socket version (none->small L2) and a few things in between.
Just my Tu'pence.
Without the adapter, i have no upgrade path (other than another celeron). So this keeps me upgradable until something i can't buy yet is the standard.
I just bought a new play server and want the price performance of a celeron but want to be able to move to a PIII if I need it.
So after a little searching I found that some smart guy has made a slot 1 board with a socket 370 mount on it. So i pop the celeron on that and then use my PIII compatible motherboard.
Hopefully someone will do the same for this new AMD socket 423, because if all the reports I see are correct, the Athlon screams.
BTW, those sneaky people who made the converter, Asus. ASUS S370 "Slocket" CPUConverter
A year ago I went out and set myself up with a nice k62 350 with a mb with a via chipset. I had heard it was one of the best, but they claimed no NT support, and I had endless problems running an agp vid card with nt. pci was fine, as was agp on 98, but I had to run nt for cold fusion so I was forced to take it back and spend 400 more on a p2 that was almost as fast... I've read of lots of chipset problems with the k6-2, I pray the k7 chipsets are better, because it sure smokes the p3!
"hard work often pays off over time, but laziness always pays off now."
Personally, I think I'd wait quite some time before going with a non-intel x86 architecture. Probably due to the fact that I've been burned by so called "compatible" chips in the past. But competition is a good thing, and it will surely make intel deflate their heavily inflated margins at for higher end chips (they're already feeling the pressue at the lower end, and the frequent intel price cuts are evidence of this).
Perhaps after AMD proves themselves a bit more, others like myself will give them some consideration. They're definately on the right track.
Absolutely a win situation for the consumer, no matter how you look at it.
What I'd like to know is what ever happened to those polymer memory cubes I heard about many years ago.
Supposedly some type of 3 dimensional storage that withstood shocks well, had nearly the access time of RAM (for the time, around 150ms I believe), and was non-volatile. It was also said to be extremely cheap to produce and targetted as a replacement for RAM as well as disk based storage.
And then, I never heard another word about it.
I decided to upgrade that silly BSD Cyrix386 box I had running today, and considering the strong favorable comments posted here, I went with an AMD chip.
:)
So now my gateway testbed is running a K6-2/333, and I do admit its speedy. I'll just have to see how stable it is
Actually, that would probably make your system slower, since that would keep app. code which might benefit from the cache from being stored.
Still, it might be an interesting idea if processors allowed the operating system to "lock" certain bits of memory in the cache, in case there were some services which got used infrequently but needed low latencies (real-time services, etc).
I'm not sure that running an OS *entirely* out of cache is always a good idea. The point of cache is to hold the last amount of instructions/data that the processor used such that, on the odds that it will be needed again soon, it's there.
Cache needs to be dynamicly updated to deal with what the processor is doing *now*. For example, if you're browsing the web, would you rather keep your printer driver in your fast memory, or the netscape rendering code?
Also, the larger that you make a cache, the more expensive a cache miss is (as you had to look through your cache to see that it wasn't there).
I'm not saying that putting the OS into fast memory/cache is a bad idea, but I don't believe that putting the ENTIRE OS there won't create more problems that it will solve.
-Rob
WRCT Pittsburgh, 88.3FM
Sorry but 8 Mbyte is too much on chip cache to be credible. The 1.5 Mbyte cache in the 0.25 um PA-8500 takes up over 300 mm2. Even in 0.18 um an 8 Mbyte cache would take up ~900 mm2 or two times bigger than can fit on a stepper. The source might have meant an 8 Mbit L2 cache. Adding that size L2 to the K7 cache and shrinking it to 0.18 um would still produce a big chip for mainstream PCs but at least it is in the realm of possibility.
You might think that integrated DRAM wouldn't be fast enough for cache, but there are many advantages to integration that are not always obvious. While DRAM does have much worse latency than SRAM (normally used for cache), the external SRAM that they are using now takes 8 L2 external cycles (that's 25ns @ 600Mhrz) to transmit the data, excluding latency. Integration would cut data transmission time down to less than 5ns. Joined with additional savings from not having to drive the external address lines and not having to deal with the DRAM row registers so much might actually make internal DRAM faster than external SRAM.
(I've been wishing they'd integrate DRAM onto processors for a long time now, if you can't tell from my advocation speech)
I look at this from a rather different perspective - not as a quick hack to make up the difference in speeds of the processor and the external memory, but rather as an intermediate stage in the gradual integration of memory onto processors, those being the two things that have to communicate the most in your whole system.
If you are doing highly 3-D stuff (ie Quake 3 or 3DMAX), Anand reports that a single Athlon 600 outscores a Dual PIII 600 on NT (With the native support for the Graphics card disabled!) http://www.anandtech.com/html/review_display.cfm?d ocument=1029&pagenum=32 Also see the overclocking comparison, AMD Athlon 650 at 750Mhz seems to be more reliable than PIII 600 at 650Mhz. http://www.tomshardware.com/cpu/99q3/990823/athlon _pentiumiii-01.html
The Register is reporting a rumor that AMD has hired a top Alpha engineer to guide the development of the 64bit K8 which may be demo'd as soon as the Microprocessor Forum early next month in San Jose.
SUN sells workstations that will beat the G4 handily except for Altivec stuff, which probably is faster. But they also have the Enterprise 10000 can be equipped with up to 64 processors, which means it will leave a G4 in the dust.
SGI sells Onyx2 InfiniteReality2, which will beat probably anything else on heavy-duty visualisation stuff, and can be equipped with up to 128 processors.
HP makes the J-5000 workstation, which will also beat a G4 on most tasks, as well as big-ass servers with up to 128 processors.
IBM makes RS/6000 workstations and servers, which can scale up to 128 processors.
Compaq sells XP1000 workstations with a 667MHz Alpha 21264 processor, which will beat the G4 on anything that can't make very good use of Altivec, and there are places that sell dual 667MHz 21264 workstations. Compaq also has the AlphaServer GS line, which can take up to 14 21264's, probably beating the G4 on anything.
Furthermore, the Athlon probably beats the G4 on stuff that doesn't parallellise well, and an 8-way Xeon should be faster for most, if not all, things.
Unfortunately all the systems here, except the Athlon, are far, far more expensive than a G4. But you can get faster systems if you're willing to pay the price. Oh, and all of those run some Unix variant, as well as Windows NT for Alpha and Athlon/PIII.
Also, when it comes to the speed of the G4, it all depends on how useful Altivec is for your app. If it isn't useful, the G4 isn't that impressive. If it is, the G4 should be very good value for money, if Altivec is anywhere near as good as the hype claims it is.
This is incorrect. The Athlon die, coupled with 8mb of L2 cache would simply be enormous, even on a .18um process. Also, Sharky Extreme misreported this information. The socketed version of the Athlon is the Athlon Select, but this version is the low-end one. Only the high-end version, the Athlon Professional, will have these cache sizes. The Athlon Professional will also be in the Slot B (that's the current Alpha standard) format. Sharky Extreme is about as unreliable as The Register when it comes to processor information. For a better explanation of some of the problems with Sharky Extreme, take a look at http://www.jc-news.com/pc/.
Now, what I'd like to see is someone running an operating system *entirely* out of cache. 8Mb should easily be enough to run a cut-down Linux, and definitely enough for the earlier MS operating systems...
Question is, is it possible? I suppose if you're never getting any cache misses then it won't have to access any external memory, but I'd imagine that there's a whole load of problems to do with memory mapped I/O and booting...
anybody with a little more technical knowledge care to comment?
On a related note: The Register has a story about the K8 (note the register appears to be down right now, but the link is on the main page). Not very much information, but interesting never the less.
Another plus of the new architecture? Each CPU maker will use the technology they know how to use best. I wouldn't expect it any other way. I wouldn't force an artist who uses oil paints to move over to anything else if that is what he knows best.
sporty
---
Use the force lunk!
-
ping -f 255.255.255.255 # if only
this APIC patent for example, it's the APIC protocol itself is patented. Yet another case where the US patent system prevents competition and causes inflated prices. (just check out how much a Xeon CPU costs - ridiculous.)
--Coke
Cache is not something you get to control directly in code.
...read the rest of the cache line. Assuming your code is well optimized for cache performance, the next things you read should already be in the cache.
It can be, in a lot of newer architectures. Prefetching instructions area available in instruction sets of many RISC, and even x86 processors. The main problem is that most optimizing compilers can not do a good job of cache prefetching since there is no corresponding construct in high-level languages, i.e. you do not have a C structure which says "get this memory chunk in the cache". However, for bold people who like to play with assembly language, the instructions are there. Operating systems generally do not like these instructions, though.
Embedded system programmers, particularly those lucky enough to use modern CPUs with cache controllers, can use these tricks.
Of course, you have the assumption that the optimization mentioned here is simply making sure that the current working set fits in the cache line-that's not usually the case with modern software, and you will always have a lot of conflict misses.
IMHO, the previous poster makes a valid point and using the prefetching techniques, it might be possible to get the whole OS into the cache. This might be interesting to play with, but then I'm not sure if it will have any significant advantages-you might be better of loading the application and its working set into the cache rather than the OS. (unless all you do in your application is a bunch of system calls..)
Zigbee Central: A Zigbee weblog
Don't get me wrong, I'm all for competition in the processor market, and 8MB of cache sounds like the chip would fly!
But why do AMD and Intel insist on this "war" about the socket architecture? One of the best things about the Super Socket 7 was that you could buy a mother board, and then slap a Cyrix chip, a standard pentium, a K6/2 or a K6/3. This gave people on a low budget a nice clear upgrade route from a cheap processor to something more worthwhile.
All this customising of sockets is good for performace, but why don't they take the cost / upgrading of systems into account? Not everybody can afford to shell out for a new processor every 6 months, let alone a new processor AND motherboard.
Manic.
If you ever drop your keys into a river of molten lava, let'em go, because, man, they're gone.
8mb, hmm.
Remember that cache is a fix, it makes up for the shortfall in the speed of memory and the bus architecture. I think this just indicates how far behind the rest of the x86 system is falling behind processor developement. I'd much rather have faster main memory and a better bus architecture than masses more cache. Cache is expensive and doesn't always give the benifits you would think. Remember the Celeron had only half the cache of the comparative PII but could equal it in performance because it's cache ran at full processor speed.
Its not size that matters, its how you use it and what you put around it that counts
Cache is not something you get to control directly in code.
When you read a dword from main memory (i.e. not already in the cache) and then do operations on it, the cache controller takes advantage of a free memory bus to go ahead and read the rest of the cache line. Assuming your code is well optimized for cache performance, the next things you read should already be in the cache.
If you're doing a lot of kernel stuff, large chunks of the kernel will be in the cache, as you would want. And if you're running Quake 3, Quake 3 will be in the cache. It's exactly what you want.
There are just so many to choose from :-)
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Seriously:
"Socket 7"
Gee, for all you with Pentuim 1s, Pentuin w/ MMXes, and older K6s. Super 7 (just a minor mod) for K6-2 and -3. I expect the genuine socket 7s are dead now, with the Super 7s gone by next year.
"Slot 1"
It's already dieing because the Pentuim IIs/IIIs are outrageously expensive, compared to their performance (especially those damned PIIIs with their serial number ickyness). Celeron is in the cheaper Socket 370, and you know people love those things
"Slot 2"
If you think a PIII is too cheap, buy a Xeon PIII and one of these babies. Considering Intel's SMP design forces the CPUs to share the same bus, Xeons with 4mb of cache will not scale well past 4 or so CPUs, so why bother with the expense when Athlons are cheaper? This spec can die like the "Socket 8" of the PPro.
"Socket 370"
Perhas usefull, but the Celerons are ludicrously locked at a 66Mhz front side bus. I mean, Intel is embarrassing enough because their first-string proccessors (PIIs/IIIs) have a half-clocked L2 cache. Pathetic! They've hobbled the Celerons, and are just trying to prove they control the customer's demands.
"Slot A"
Well, seems OK. I mean, you can plug in an Alpha proccessor package of an Athlon package in the same Slot A, and you do get the benefits of fast bus speed, at chipspeed L2 cache, etc.
"Socket 423"
I guess this was inevitable. I doubt you'll be able to plug an Alpha into this, but the PGA format is a bit cheaper to make than ye olde cartidge (can you say SNES cartridge looking?) CPU packages. They are probably cheaper, and I know they're probably easier to stick into one of those wonderful Kyrotech units
Anyways, I know I'll be buying more AMD. I love that company
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