valintino rossi is possibly the best motorcycle racer ever (many would argue). he has dominated motogp. he won almost every race last year, on honda's v5. this year he switched to yamaha, and won (iirc) the first four races. in the history of motogp, no rider has ever won the first race after switching teams.
he tested (secretly, but it got out) ferrari's f1 car, months back. he was only a few seconds off pace, and it was the first time he had ever driven an f1 car.
considering racing on two wheels is much harder than four, i would expect him to out drive any f1 driver, if given the chance. he's said he's more interested in world rally (which he's tried before).
the problem is that reiserfs only recently got data=ordered support. i, too, lost a couple files (corrupt, partially swapped contents) due to a kernel lockup. ever since then, i've used data=ordered (just recently added to 2.6). if you used ext3 with data=writeback, you'd have the same problems.
Yeah but the torque to horsepower ratio sucks on sportbikes and the rpms are way too high
so? they're geared for it. i bet 3-6krpm, a busa will pull harder than 90% of the cars out there. and after that, hold on for your life! and try a liter twin, if you want power down low. keep in mind few cars can keep up with even a 600. to make a car keep up with a one liter i4 sportbike, you'll have to spend at least 10 times more on the car (i'm not exagerating).
you don't feel torque, btw. when most people say "torque" (like on those stupid vw commerials) they really mean low end power. in low gears, the t
go look at what the latest one liter sportbikes are putting out. the zx-10r is 158bhp, iirc. that's NA, btw, no turbo needed! then there's the 1.3l busas. i've forgotten what their hp is.
wasn't there recenly an article here on/. about how, due to the unreliability of mechanical/magnetic drives, it was cheaper (and faster, of course) for them to use solid state drives? i know i read that about some company. i couldn't find the article, though.
The NX flag is dealt with by the memory controller
no, it's handled by the mmu, which is on chip (and has been for many years on many different chips). the memory ctrler does nothing but access the ram chips.
if you want to goto mars, start a nonprofit or something. stop taking money out of my pockets! too many tens (of not hundreds) of billions of dollars have already been wasted on the space station and silly space shuttle experiments. the enormous burden of supporting space exploration should not be forced upon everyone. can you name ONE good thing that came out of the space program, that couldn't have been created without, and for less money?
Thats the idea. It sets a flag and says, hey... this code isn't in the instruction cache, you shouldn't execute it. It is up to the OS in most cases to go "wow, thanks for catching that..." and close the application without delay.
it isn't quite that simple. code on ANY split cache cpu MUST be in the icache. that is the only way it can be executed.
what happens is this: some mal. code is written into a data segment (elf segment, i mean, not just x86 segmentation crap). now, the cpu jumps to that code. this is easy on x86, cuz the i and d caches are coherent (they aren't on ppc and other risc archs).
when the fetch for the jump target is executing, the cpu will fault on the itlb fault. either the hardware or software (on some riscs) will load the itlb. either at tlb insertion or after insertion, when the fetch is attempted, it will fault on the no-exec flag. that's if you have a decent cpu and a decent os. if not, then the l1 icache faults on the load and looks to the (usually) unified l2. (in the risc case, you must flush the writes down to the unified cache somehow.) if it's an inclusive cache, and the cache is synced at this point, the l1i will load a line from the jump target and feed the pipeline.
there are some things broken by the no-exec bit. gcc tampolines. i'm not familiar with them, though.
Wait, are you saying that pages don't *already* have an execution-enable bit?
yes, this is one of the wonderful misfeatures of x86. i don't know what this article is all about. amd64 ALREADY has an execute bit in each pte, when it's in long (64bit) mode. this is nothing new; it's been in amd's manuals for while. i'd bet it was one of the first x86 problems they planned to fix.
i have raynaud's and something like this would allow me to stay outside much longer. my hands (especially) and feet always limit my time. also, when i'm on my sportbike, if it's about 55F out, my fingers go numb.
i would definetly buy them and so would other bikers. they could replace heated hand grips, if they were cheap enough.
to play with solaris. i have solaris 9 and debian on it. java is 2-3 times faster on this thing than compaq's horrible 1.3 jvm on my dual 833 alpha running linux. it's as fast as my year old dell demension l1000r at work running win98 + hotspot.
to get decent preformance:
get a 333mhz/2meg cpu module (either with the machine, or buy a 270mhz/256k box and buy the 333mhz by itself). the cache makes a big difference.
take the ata drive and rip it out. go buy a symbios uw scsi card and a newer generation 10k cheetah. solaris's ufs will thrash like crazy on anything slower. it is unusably slow with the stock drive.
you should be able to get all that off of ebay for around $200.
sorry, this country expects people to work for things. if you're disabled, there's social security. however, if you're a bum who refuses to work, why should anyone pay for that person's well being?
unfortunetly, the reps and dems both like to take money from citizens and giving it away to certain people. at least, so far, socialist medicine hasn't been enacted.
i have been looking into learning c++ or java (i've known c for about 5 years). the unclutteredness (from what i've gathered) of java had me leaning towards it.
until i tried it.
i have a dual 833 alpha, and even compaq's 1.3.1 jdk makes it run like a 386. part of this is compaq's fault (my 333mhz ultra5 running solaris runs netbeans faster - and compaq's jvm is buggy). the other part is inherent (no pun intended;) with java. java apps are only as portible as the jvm is ported. netbeans is unusable on my alpha (running linux, btw). i tried kaffe, but it's even slower - it only uses one thread per java app!
my other problem, of course, is hp's ignoring linux/alpha. there is no (and i doubt will ever be) a 1.4.1 jvm. not that i blame them a whole lot, since alpha is dieing.
back to c++. it's more portable than java(!) and way faster on alpha. not to mention, java seems to be adding more and more c++ features.
to conclude, java may be more ideal than c++, but at least c++ is usable! java has had plenty of time to mature, and is disappointing (at least to me). i doubt.net/mono will be much different.
328 *physical* registers, not logical (ISA accessible). with 128 context switches will hurt big time ia64. yet another bad design decision of the itanic.
The theory has NOT been proven bullshit. For example: the alpha 21264 is faster than any cisc chip. Calling a cisc cpu minus its microcode a "risc core" is just silly word play. cisc cpus have ALWAYS decoded instructions into micro-ops; that's what cisc IS! The big downside to cisc ISAs isn't just the silicon for the microcode, it's also the complexity of the ISA (eg, x86). x86 is MUCH more complicated than any risc ISA.
what about voodoo day?! i'm tired of being left out! why can't anyone wish my a happy voodoo day? i can't even get anyone to help me bleed this chicken!
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both hfs+ and ntfs are both journaled. ntfs has been for a while.
the knocking was most likely caused by carbon build up (it glows and causes hot spots that start burning too early).
what prevents a bioterrorist from grabbing a sample of regular wheat and making a virus for it? where is the new vulnerability?
valintino rossi is possibly the best motorcycle racer ever (many would argue). he has dominated motogp. he won almost every race last year, on honda's v5. this year he switched to yamaha, and won (iirc) the first four races. in the history of motogp, no rider has ever won the first race after switching teams.
he tested (secretly, but it got out) ferrari's f1 car, months back. he was only a few seconds off pace, and it was the first time he had ever driven an f1 car.
considering racing on two wheels is much harder than four, i would expect him to out drive any f1 driver, if given the chance. he's said he's more interested in world rally (which he's tried before).
wipe.sf.net
the problem is that reiserfs only recently got data=ordered support. i, too, lost a couple files (corrupt, partially swapped contents) due to a kernel lockup. ever since then, i've used data=ordered (just recently added to 2.6). if you used ext3 with data=writeback, you'd have the same problems.
so? they're geared for it. i bet 3-6krpm, a busa will pull harder than 90% of the cars out there. and after that, hold on for your life! and try a liter twin, if you want power down low. keep in mind few cars can keep up with even a 600. to make a car keep up with a one liter i4 sportbike, you'll have to spend at least 10 times more on the car (i'm not exagerating).
you don't feel torque, btw. when most people say "torque" (like on those stupid vw commerials) they really mean low end power. in low gears, the t
go look at what the latest one liter sportbikes are putting out. the zx-10r is 158bhp, iirc. that's NA, btw, no turbo needed! then there's the 1.3l busas. i've forgotten what their hp is.
wasn't there recenly an article here on /. about how, due to the unreliability of mechanical/magnetic drives, it was cheaper (and faster, of course) for them to use solid state drives? i know i read that about some company. i couldn't find the article, though.
no, it's handled by the mmu, which is on chip (and has been for many years on many different chips). the memory ctrler does nothing but access the ram chips.
if you want to goto mars, start a nonprofit or something. stop taking money out of my pockets! too many tens (of not hundreds) of billions of dollars have already been wasted on the space station and silly space shuttle experiments. the enormous burden of supporting space exploration should not be forced upon everyone. can you name ONE good thing that came out of the space program, that couldn't have been created without, and for less money?
it isn't quite that simple. code on ANY split cache cpu MUST be in the icache. that is the only way it can be executed.
what happens is this: some mal. code is written into a data segment (elf segment, i mean, not just x86 segmentation crap). now, the cpu jumps to that code. this is easy on x86, cuz the i and d caches are coherent (they aren't on ppc and other risc archs).
when the fetch for the jump target is executing, the cpu will fault on the itlb fault. either the hardware or software (on some riscs) will load the itlb. either at tlb insertion or after insertion, when the fetch is attempted, it will fault on the no-exec flag. that's if you have a decent cpu and a decent os. if not, then the l1 icache faults on the load and looks to the (usually) unified l2. (in the risc case, you must flush the writes down to the unified cache somehow.) if it's an inclusive cache, and the cache is synced at this point, the l1i will load a line from the jump target and feed the pipeline.
there are some things broken by the no-exec bit. gcc tampolines. i'm not familiar with them, though.
yes, this is one of the wonderful misfeatures of x86. i don't know what this article is all about. amd64 ALREADY has an execute bit in each pte, when it's in long (64bit) mode. this is nothing new; it's been in amd's manuals for while. i'd bet it was one of the first x86 problems they planned to fix.
i have raynaud's and something like this would allow me to stay outside much longer. my hands (especially) and feet always limit my time. also, when i'm on my sportbike, if it's about 55F out, my fingers go numb.
i would definetly buy them and so would other bikers. they could replace heated hand grips, if they were cheap enough.
to play with solaris. i have solaris 9 and debian on it. java is 2-3 times faster on this thing than compaq's horrible 1.3 jvm on my dual 833 alpha running linux. it's as fast as my year old dell demension l1000r at work running win98 + hotspot.
to get decent preformance:
get a 333mhz/2meg cpu module (either with the machine, or buy a 270mhz/256k box and buy the 333mhz by itself). the cache makes a big difference.
take the ata drive and rip it out. go buy a symbios uw scsi card and a newer generation 10k cheetah. solaris's ufs will thrash like crazy on anything slower. it is unusably slow with the stock drive.
you should be able to get all that off of ebay for around $200.
the drive's controller filling cache definetly does not cause interrupts to the host. a drive with cache segments >= one track is ideal.
solaris is good at managing interrupt latencies (so the disk's cache won't empty under heavy loads)
huh? this makes no sense. intr latency has nothing to do with drive cache.
no, these days the candlestick industry would just lobby for tariffs and other protections against competition.
sorry, this country expects people to work for things. if you're disabled, there's social security. however, if you're a bum who refuses to work, why should anyone pay for that person's well being?
unfortunetly, the reps and dems both like to take money from citizens and giving it away to certain people. at least, so far, socialist medicine hasn't been enacted.
btw, some people don't need or want it!
i have been looking into learning c++ or java (i've known c for about 5 years). the unclutteredness (from what i've gathered) of java had me leaning towards it.
;) with java. java apps are only as portible as the jvm is ported. netbeans is unusable on my alpha (running linux, btw). i tried kaffe, but it's even slower - it only uses one thread per java app!
.net/mono will be much different.
until i tried it.
i have a dual 833 alpha, and even compaq's 1.3.1 jdk makes it run like a 386. part of this is compaq's fault (my 333mhz ultra5 running solaris runs netbeans faster - and compaq's jvm is buggy). the other part is inherent (no pun intended
my other problem, of course, is hp's ignoring linux/alpha. there is no (and i doubt will ever be) a 1.4.1 jvm. not that i blame them a whole lot, since alpha is dieing.
back to c++. it's more portable than java(!) and way faster on alpha. not to mention, java seems to be adding more and more c++ features.
to conclude, java may be more ideal than c++, but at least c++ is usable! java has had plenty of time to mature, and is disappointing (at least to me). i doubt
fast != unsafe. many people can safely ride a sportbike, even at 120. the real danger is huge, heavy suv's and trucks driven by incapable people.
328 *physical* registers, not logical (ISA accessible). with 128 context switches will hurt big time ia64. yet another bad design decision of the itanic.
the big problem with cvsup is that it's written in modula-3. the only modula-3 compiler is for x86 only.
The theory has NOT been proven bullshit. For example: the alpha 21264 is faster than any cisc chip. Calling a cisc cpu minus its microcode a "risc core" is just silly word play. cisc cpus have ALWAYS decoded instructions into micro-ops; that's what cisc IS! The big downside to cisc ISAs isn't just the silicon for the microcode, it's also the complexity of the ISA (eg, x86). x86 is MUCH more complicated than any risc ISA.
what about voodoo day?! i'm tired of being left out! why can't anyone wish my a happy voodoo day? i can't even get anyone to help me bleed this chicken!
that's almost certainly a migrain, but IANAD. go see a neurologist.