It has the performance of a 1.5GHz Cyrix C3, and in the benchmarks used, burned six watts. The TDP is higher, but the TDP is higher than the power you'd see in any normal situation anyway.
If you take a look at the benchmark suite used to come up with the performance ratings, you'll see a few highly-memory-performance-dependent benchmarks, whose results would not have scaled much with a higher clock speed.
Regarding point 1, read this. Register starvation is not a major problem. The biggest slowdown is that memory addresses have to be translated (this is the case no matter what virtual memory/paging system you use), which adds a large penalty to EVERY memory access.
Yes, but it's using segments, which are separate from regular virtual memory and paging. This will be easier for OS developers to use, and will be cross platform (at least with other architectures that support NX... sparc, etc). Segments are an x86-only feature.
Re:Phew!
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Hardened PHP
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· Score: 5, Informative
It's a way to protect against buffer overflows. You put some known data on the stack, and before returning from each function call, make sure that data hasn't been changed. Most buffer overflow exploits work by overwriting part fo the stack, and canary protection will detect that the stack has been changed, so the exploit code will not run.
Why waste all the power on a Via C3 (multiple watts) when you could use an AMD Alchemy Au1550, which consumes less than 1 watt? The development board is MUCH smaller than any uATX-like form factor.
The focused window comes up and is displayed in the normal "2d" manner. You can't even interact with windows that aren't on the 2d plane beyond dragging them around, and their window contents don't update realtime.
That doesn't matter - instructions on how to make the processor wouldn't be useful to Intel, as their architectures are radically different from AMD's, and you can't just add instructions using the same extra logic.
Moore's first law is a two-edged sword - more transistors for the same price is great for computers, but it's hell on batteries: As the processor power doubles, the power consumption also rises. The amount of computation done per watt also rises with each generation - an AMD Opteron at 500MHz would use under 10 watts, or an amount similar to an original Pentium.
But that alone won't do it. We need to improve system layouts and cooling techniques. Better cooling won't reduce power - it means you can burn MORE power without getting hotter. It doesn't help your battery life.
We must create better interconnects, reduce sloppy software code, eschew processors that are faster than necessary, and, of course, build better batteries. What is wrong with things like AMD's PowerNow!, AMD's Cool'n'Quiet, or Intel's SpeedStep? They all reduce the power consumption of a processor when it isn't heavily loaded.
Princeton did this a while ago... and it was on /.
on
Searching by Shape...
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· Score: 1
Slashdot covered the 3d search by Princeton almost two years ago. I didn't find the article too informative so I can't tell for sure if it's the same type of thing or not.
OpenBSD's "W^X" is implemented using techniques discussed here. The hardware support the story refers to is most likely the presence of an "NX" bit in the AMD64 page table, to allow per-page permissions (which, by the way, Intel is apparently not going to implement, at least in their early AMD64-compatible parts).
Re:Protected Stack hardware requirements?
on
Gates on Winsecurity
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· Score: 3, Informative
I do not believe OpenBSD has a software protected stack. However, given that OpenBSD runs on platforms which have hardware protected stacks, it does have the ability to guard against those kind of overflows. Just not on x86 hardware. Well, except maybe a version that runs on the AMD64 hardware...
From here: (NOTE: i386 and powerpc do not support W^X in 3.3; however, 3.3-current already supports it on i386, and both these processors are expected to support this change in 3.4).
You can use a little-known feature of x86 called "segments" to enforce non-executability of memory areas. It's just different from the regular paging system used to implement virtual memory, and COMPLETELY unique to x86. You can find a discussion about it here. The links in the thread have some good info.
Slashdot Mirror
Benchmarks used to determine model numbering.
All the power "used" in a CPU is turned into heat. So yes, these Geodes give off less heat (hence the lack of a fan in Geode NX cooling solutions).
It has the performance of a 1.5GHz Cyrix C3, and in the benchmarks used, burned six watts. The TDP is higher, but the TDP is higher than the power you'd see in any normal situation anyway.
Yes, in August 2003. AMD has decided to include all of its low-power x86 processors in the "Geode" brand.
If you take a look at the benchmark suite used to come up with the performance ratings, you'll see a few highly-memory-performance-dependent benchmarks, whose results would not have scaled much with a higher clock speed.
At $65 and $55, they're a LOT cheaper than the Pentium M (I can't find one for under $195), although they are aimed at different markets.
Regarding point 1, read this. Register starvation is not a major problem. The biggest slowdown is that memory addresses have to be translated (this is the case no matter what virtual memory/paging system you use), which adds a large penalty to EVERY memory access.
Yes, but it's using segments, which are separate from regular virtual memory and paging. This will be easier for OS developers to use, and will be cross platform (at least with other architectures that support NX... sparc, etc). Segments are an x86-only feature.
It's a way to protect against buffer overflows. You put some known data on the stack, and before returning from each function call, make sure that data hasn't been changed. Most buffer overflow exploits work by overwriting part fo the stack, and canary protection will detect that the stack has been changed, so the exploit code will not run.
...and yet I can be sued when a burglar hurts himself on my property.
Why waste all the power on a Via C3 (multiple watts) when you could use an AMD Alchemy Au1550, which consumes less than 1 watt? The development board is MUCH smaller than any uATX-like form factor.
I think this guy has got you beat... 23,002 traces of spy/adware!
The site is pretty thoroughly slashdotted. I grabbed it a few days ago, so... mirror. You'll want one of the sphere zips and the cgsl library.
It works with VNC... I was playing with it a few days ago and used VNC to show some people who were far away.
The focused window comes up and is displayed in the normal "2d" manner. You can't even interact with windows that aren't on the 2d plane beyond dragging them around, and their window contents don't update realtime.
You can use the mouse wheel to move windows closer/further, or to move the camera position in and out. It is in fact 3d.
How is this different from a port of User-mode Linux?
That doesn't matter - instructions on how to make the processor wouldn't be useful to Intel, as their architectures are radically different from AMD's, and you can't just add instructions using the same extra logic.
AMD has been working on going lead free for a while (apparently since 2001).
Moore's first law is a two-edged sword - more transistors for the same price is great for computers, but it's hell on batteries: As the processor power doubles, the power consumption also rises.
The amount of computation done per watt also rises with each generation - an AMD Opteron at 500MHz would use under 10 watts, or an amount similar to an original Pentium.
But that alone won't do it. We need to improve system layouts and cooling techniques.
Better cooling won't reduce power - it means you can burn MORE power without getting hotter. It doesn't help your battery life.
We must create better interconnects, reduce sloppy software code, eschew processors that are faster than necessary, and, of course, build better batteries.
What is wrong with things like AMD's PowerNow!, AMD's Cool'n'Quiet, or Intel's SpeedStep? They all reduce the power consumption of a processor when it isn't heavily loaded.
Slashdot covered the 3d search by Princeton almost two years ago. I didn't find the article too informative so I can't tell for sure if it's the same type of thing or not.
OpenBSD's "W^X" is implemented using techniques discussed here. The hardware support the story refers to is most likely the presence of an "NX" bit in the AMD64 page table, to allow per-page permissions (which, by the way, Intel is apparently not going to implement, at least in their early AMD64-compatible parts).
I do not believe OpenBSD has a software protected stack. However, given that OpenBSD runs on platforms which have hardware protected stacks, it does have the ability to guard against those kind of overflows. Just not on x86 hardware. Well, except maybe a version that runs on the AMD64 hardware...
From here:
(NOTE: i386 and powerpc do not support W^X in 3.3; however, 3.3-current already supports it on i386, and both these processors are expected to support this change in 3.4).
You can use a little-known feature of x86 called "segments" to enforce non-executability of memory areas. It's just different from the regular paging system used to implement virtual memory, and COMPLETELY unique to x86. You can find a discussion about it here. The links in the thread have some good info.
1. The site is still loading fine.
2. Isn't the point of putting stuff on the web having people see it?
This guy put a lot of thought into the "leaving a buffer" theory. His links page has some really cool links.