They have probably meant to say that the same pin drivers will be used as they are on the HT-3.0 links.
Given that it took a considerable effort to develop such superfast drivers on silicon chip and that it is now in their existing know-how it seems only reasonable to leverage it to the maximum use...
But G3MX is meant for Barcelona successors AIU, and those need not necessarily have L3.
Even if so, L4 wouldn't hurt, especially if it is much larger than smallish L3 on first Barcelonas.
Also, if there would be separate channel for peripheral DMA access, internode G3MX communication and on-chip SIMD units, extra cache could nicely decouple CPU from RAM most of the time, especially with maybe one or two extra instructions for software L4 cache prefetch...
But with FB-DIMM you get to pay high latency penalty with higher number of modules that really it doesn't matter if in theory you can do it, in practicall world latencies will kill you.
Besides that, on Optys you can always add one extra CPU with its set of 4x G3FX chips and corresponding RAM.
Sure, latencies through extra HT link will be higher, but you get extra CPU that you can useif you want to, and however you cut it, with extra memory you have to pay some extra latencies.
All things considered, this solution is not half bad.
Especially if they do it Right(TM) and incorporate similarly fast links between G3FX chips in a group and maybe throw in extra HT link and at least small L3 cache so that periphery can have big-time DMA access to the memory...
Come to think about it, some autonomous SSE-like unit in that chip could also come in very handy...
If done right, this could give new Optys considerable edge...
They are using G3MX chips as a sort of multiplexer and connecting it to the CPU though a couple of lanes with high-speed signaling.
Internal logic within HYDRA CPU will have the capability to use either conventional onboard memory controller and drive the DDR-3 RAM directly or when socketed within board with G3MX extenders, use that same lines for communication through the G3MX.
Since the load on the lines will be much smaller and constant and since all lines are unidirectional, each line will be capable of much higher signaling speed, so they will be able to use 4x as much RAM as before per CPU node.
If that is not enough, several Hydra CPUs could be connected through HT links- just like now with existing Opterons.
CPU-G3MX connection is much more direct and probably need not to use extra cycles for node addressing, unlike conventional internode communications through HT links, so time overhead could be considerably smaller...
Also, compared to FB-DIMMs, when accessing to some RAM bank here user only pays some throughput penalty (if any), but doesn't suffer much extra latency- with FB-DIMMs data hos between the modules and each hop costs one clock, so access time for 4-th module is longer than to the first one in a group.
Not to mention that GMX-3 chip could host some L3 cache if needed in some later implementation and that combined speed of all G3MX chips is probably greater than existing solution, so interesting effects could be achieved with meory interlieve.
It could very well be that such combination could have distinct speed advantage even in many workstation applications...
While Hitachi uses 5 platters for 1TB, Spinpoint F1 manages to pack that space on only 3 platters, so it should be faster, more quiet and lower power than Hitachi. Not to mention good deal cheaper.
Actually, intel has sold 0.000 QUad cores (= 4 cores on a die in a single unit)...
And if you count Q6xx0 as quad core system, then by that standard qualifies every dual socket dual core AMD system sold, since architecturally they are about equivalent, if not better ( 2x memory channels, HT links)...
I am very "convinced that performance difference will be drastic" since:
1. This is mainly what currently holds Opterons over Xeons on servers, despite superior C2D core and heap of cache.
2. I have exchanged dual Opteron boards for single socket DC 6000+. Despite HT link and dual RAM bank of existing Opterons being superior for most uses to Intel's shared FSB, there is tangible speedup just due to having really fast intercore communication path.
3. AMD has onboard memory controller even now with K8 and K10 will bring further optimisations there.
4. There are further optimisations for VT, which will bring ie. speeds of WinXP, running under VmWare on my Gentoo Linux (64 bit) much closer to native speeds...
If AMD wanted to, they could have hads Intel's style "quad core" long ago.
Hell, even two "x2 4800" dies on one substrate, connected through HT link would be an equivalent, and they could do it in a few weeks even if they would decide to go for it _today_. There is not much to it.
Opteron/AMD64 was _made_ so it could be connected it LEGO-like fashion...
1. it all depends on task at hand. With tasks with intensive intercore communications true Barcelona could be say 10x faster than anything Q6xx0 on Intel's side even without superior core.
2. If your general understanding of the problem is poor than any explanation that could be "interesting" to you is likely to be marketing bull**it, optimized for technical morons.
You can't make universally valid "X-times faster/slower than" comparisons between these kind of machines.
But on those "real life benchmarks" even old 4 socket Xeon would performe "just great" since there is minimal need for intercore communication with these tasks.
They could be executed just as efficiently with multiple machines, connected through network.
On any really intensive multicore problem existing Intel's dual-dual core solutions suck...
Testing multicore solutions on optimized Photoshop tests, video encoding and raytracing is just like buying drag-racing truck for as daily commuting vehicle...
All existing Q6xx0 solutions are dual-dual core ie two dualcores sharing same FSB - and that is _NOT_ the same as true QC as Barcelona is claimed to be.
That difference is enough to make Barcelona the main choice for many core servers even if it were made with old K8 and not the new K10 cores.
Intel should have true QC chips in a year or so...
So what ?
Who said that this piece of Kryptonite really originated from Serbia ?
It was just _found_ there.
Original post is right. The stuff is chemically speaking "the real thing"...
Final nail in the EPIA coffin is "we don't give a fu**" Linux support.
Some HW on that board has decent open source drivers and for the rest VIA doesn't care much.
Most prominent example is unichrome driver. It has "open source" version, but it is very incomplete as poor bastard who did it had to work without VIA's support.
They claim that you can get the datasheets etc, but in reality I have asked them several times and never got an response.
So, with Linux you can't utilize even what meager HW you have onboard.
VIA's answer seems to be that one should use Windoze. But those boards are not cheap as it is and with extra SW cost total prices are even higher.
C3/C7's performance and/or power consumption is not exactly stellar, so it's hard to find compelling reason to go for even the cheapset basic M-1000, let alone pico or nano-itx.
If one decides on using Linux, one can find much better, more economic and cheaper alternatives on other platforms.
Judging from published photos and descriptions of ball lightning phenomena and copy of the video on youtube, this is far from ball lighting.
These things hover over the concrete floor and look like sizzling droplets that can spray around sometimes when welding. It is not unusual to see such hovering drops as they vaporize water in the floor beneath them and so create some kind of gas cushion- hovercraft effect.
Genuine ball lightnings has been reported able to hover in the air, sometimes at considerable height and it was not always blindingly bright...
...having sanwditch of two identical LCD panels, glued one on another and driven with essentially the same signal ?
One would probably need a bit stronger backlight and maybe special mask between the panes so that ligt form one pixel on one LCD could go just through tha same position on another panel...
Slashdot Mirror
Brain was just preparing you for emptying whole magazine in the mother-in-law's infectuous smile...
Sounds about right
They have probably meant to say that the same pin drivers will be used as they are on the HT-3.0 links.
Given that it took a considerable effort to develop such superfast drivers on silicon chip and that it is now in their existing know-how it seems only reasonable to leverage it to the maximum use...
But G3MX is meant for Barcelona successors AIU, and those need not necessarily have L3.
Even if so, L4 wouldn't hurt, especially if it is much larger than smallish L3 on first Barcelonas.
Also, if there would be separate channel for peripheral DMA access, internode G3MX communication and on-chip SIMD units, extra cache could nicely decouple CPU from RAM most of the time, especially with maybe one or two extra instructions for software L4 cache prefetch...
But with FB-DIMM you get to pay high latency penalty with higher number of modules that really it doesn't matter if in theory you can do it, in practicall world latencies will kill you.
Besides that, on Optys you can always add one extra CPU with its set of 4x G3FX chips and corresponding RAM.
Sure, latencies through extra HT link will be higher, but you get extra CPU that you can useif you want to, and however you cut it, with extra memory you have to pay some extra latencies.
All things considered, this solution is not half bad.
Especially if they do it Right(TM) and incorporate similarly fast links between G3FX chips in a group and maybe throw in extra HT link and at least small L3 cache so that periphery can have big-time DMA access to the memory...
Come to think about it, some autonomous SSE-like unit in that chip could also come in very handy...
If done right, this could give new Optys considerable edge...
this concept seems quite sensible.
They are using G3MX chips as a sort of multiplexer and connecting it to the CPU though a couple of lanes with high-speed signaling.
Internal logic within HYDRA CPU will have the capability to use either conventional onboard memory controller and drive the DDR-3 RAM directly or when socketed within board with G3MX extenders, use that same lines for communication through the G3MX.
Since the load on the lines will be much smaller and constant and since all lines are unidirectional, each line will be capable of much higher signaling speed, so they will be able to use 4x as much RAM as before per CPU node.
If that is not enough, several Hydra CPUs could be connected through HT links- just like now with existing Opterons.
CPU-G3MX connection is much more direct and probably need not to use extra cycles for node addressing, unlike conventional internode communications through HT links, so time overhead could be considerably smaller...
Also, compared to FB-DIMMs, when accessing to some RAM bank here user only pays some throughput penalty (if any), but doesn't suffer much extra latency- with FB-DIMMs data hos between the modules and each hop costs one clock, so access time for 4-th module is longer than to the first one in a group.
Not to mention that GMX-3 chip could host some L3 cache if needed in some later implementation and that combined speed of all G3MX chips is probably greater than existing solution, so interesting effects could be achieved with meory interlieve.
It could very well be that such combination could have distinct speed advantage even in many workstation applications...
There is "only" one problem with that suggestion: Shuttle can't stay indefinitely in orbit.
IIRC it is rated for week or two at the most.
Quite a few stores have them.
I have ordered a few and am waiting for a delivery- should be here in a few days...
While Hitachi uses 5 platters for 1TB, Spinpoint F1 manages to pack that space on only 3 platters, so it should be faster, more quiet and lower power than Hitachi. Not to mention good deal cheaper.
Actually, intel has sold 0.000 QUad cores (= 4 cores on a die in a single unit)...
And if you count Q6xx0 as quad core system, then by that standard qualifies every dual socket dual core AMD system sold, since architecturally they are about equivalent, if not better ( 2x memory channels, HT links)...
I am very "convinced that performance difference will be drastic" since:
...
1. This is mainly what currently holds Opterons over Xeons on servers, despite superior C2D core and heap of cache.
2. I have exchanged dual Opteron boards for single socket DC 6000+.
Despite HT link and dual RAM bank of existing Opterons being superior for most uses to Intel's shared FSB, there is tangible speedup just due to having really fast intercore communication path.
3. AMD has onboard memory controller even now with K8 and K10 will bring further optimisations there.
4. There are further optimisations for VT, which will bring ie. speeds of WinXP, running under VmWare on my Gentoo Linux (64 bit) much closer to native speeds...
5
Not true.
If AMD wanted to, they could have hads Intel's style "quad core" long ago.
Hell, even two "x2 4800" dies on one substrate, connected through HT link would be an equivalent, and they could do it in a few weeks even if they would decide to go for it _today_. There is not much to it.
Opteron/AMD64 was _made_ so it could be connected it LEGO-like fashion...
1. it all depends on task at hand. With tasks with intensive intercore communications true Barcelona could be say 10x faster than anything Q6xx0 on Intel's side even without superior core.
2. If your general understanding of the problem is poor than any explanation that could be "interesting" to you is likely to be marketing bull**it, optimized for technical morons.
You can't make universally valid "X-times faster/slower than" comparisons between these kind of machines.
Results tend to be program-and-load specific...
But on those "real life benchmarks" even old 4 socket Xeon would performe "just great" since there is minimal need for intercore communication with these tasks.
They could be executed just as efficiently with multiple machines, connected through network.
On any really intensive multicore problem existing Intel's dual-dual core solutions suck...
Testing multicore solutions on optimized Photoshop tests, video encoding and raytracing is just like buying drag-racing truck for as daily commuting vehicle...
... it NEVER MADE _true_ QC CPU...
All existing Q6xx0 solutions are dual-dual core ie two dualcores sharing same FSB - and that is _NOT_ the same as true QC as Barcelona is claimed to be.
That difference is enough to make Barcelona the main choice for many core servers even if it were made with old K8 and not the new K10 cores.
Intel should have true QC chips in a year or so...
On that parallel, I appreciate your attempt to contribute informed post to "/.", but could you stop spewing diatribe now and go home ?
I don't see how such an error would get around ECC and checksums on each sector that the drive verifies and updates by itself.
Once few bits in a sectors would flip, that sector would be invalid...
So what ? Who said that this piece of Kryptonite really originated from Serbia ? It was just _found_ there. Original post is right. The stuff is chemically speaking "the real thing"...
Well, Wikipedia is WRONG. PCIe is not "bus", since it is strictly point-to-point.
... rubidium on rails.
Final nail in the EPIA coffin is "we don't give a fu**" Linux support.
Some HW on that board has decent open source drivers and for the rest VIA doesn't care much.
Most prominent example is unichrome driver. It has "open source" version, but it is very incomplete as poor bastard who did it had to work without VIA's support.
They claim that you can get the datasheets etc, but in reality I have asked them several times and never got an response.
So, with Linux you can't utilize even what meager HW you have onboard.
VIA's answer seems to be that one should use Windoze. But those boards are not cheap as it is and with extra SW cost total prices are even higher.
C3/C7's performance and/or power consumption is not exactly stellar, so it's hard to find compelling reason to go for even the cheapset basic M-1000, let alone pico or nano-itx.
If one decides on using Linux, one can find much better, more economic and cheaper alternatives on other platforms.
Judging from published photos and descriptions of ball lightning phenomena and copy of the video on youtube, this is far from ball lighting.
These things hover over the concrete floor and look like sizzling droplets that can spray around sometimes when welding. It is not unusual to see such hovering drops as they vaporize water in the floor beneath them and so create some kind of gas cushion- hovercraft effect.
Genuine ball lightnings has been reported able to hover in the air, sometimes at considerable height and it was not always blindingly bright...
... only to encourage sales of dual core 8008... ;o)
.
...having sanwditch of two identical LCD panels, glued one on another and driven with essentially the same signal ?
One would probably need a bit stronger backlight and maybe special mask between the panes so that ligt form one pixel on one LCD could go just through tha same position on another panel...
he will have the time to work on the code cosmetics and make it accepted by the kernel crowd...
That being said, I really hope that:
- he didn't marry that russian chick because she hunted for financial wellfare.
- if he didn't kill her, that she is fine.
- If he did kill her, and she deserved that, that they never prove anything...
After all republican "legal" manuevers and s*itload of corpses that resulted from them, I really couldn't care less for one more dead body...
Wrong. Intel's solution with two dualcores on the same FSB (Kentsfield) is already out.
This one has all 4 cores on the same L2 cache and shouldn't be any less effective than AMD's...