Agreed -- in addition, the "PPC is better" crowd isn't necessarily changing their tune about the superiority of that architecture in its current form, they just realize that IBM can't afford to do backflips for that 2% of the market, and Apple can't afford to subsidize PPC development specific to their needs.
I think people will slowly start to realize the broad industry alignment here (Apple->Intel, MS,Sony->PPC, IBM sells PC business) makes good business sense all around in the long run, assuming Apple and Mac developers can survive the transition.
Actually this is less dissappointing that I originally thought --
A major problem as CMOS processes get smaller and smaller is wires and wiring. Its really bad at 90nm and it looks like its going to be way worse at 65nm.
Even if optical interconnects can just be used for long intra-unit busses (think L1 cache to fetch/decode unit, and there to integer unit and float unit, etc) we could see great performance gains.
Something like when the upper metal layers in CMOS went to copper a few years ago.
Ethanol.
There are many FFVs out now (Ford Explorer, and several other popular makes that I can't recall) that can use either regular gasoline, or E85, which is 85% ethanol.
Reduces dependence on foreign oil, burns cleaner, supports US companies.
See more info
here
Why hasn't anyone brought up ethanol yet with all this talk of "running out of oil"?
Take a look at some mass-market-appeal type
vehicles.
Flexible Fuel Vehicles can use E85 (85% ethanol) or regular gasoline, just fill it up with either. some more interesting info.
If you want to do project management, etc, get an MBA.
You may also want to get a second bachelors in another field that interests you.
Consider ASIC design -- much of the coming problems at smaller technologies (sub 65nm) will be with the software tools we use. Software engineers with good chip design/methodology understanding will be in high demand.
One other example -- If they can stuff x86 desktop processors into laptops why not put them in gaming consoles?
Certainly the developer support base for x86 is so much greater, it would be a no-brainer to go with a x86 solution.
Why, then, are all the next-gen game consoles likely to be PPC based?
That having been said, if PC manufacturers can shove a desktop P4 or Athlon64 in a laptop, they could also shove it into a approximately Mini-sized computer.
True, but can they do it and still have decent specs, very little fan noise and sell it for $500?
If they put P4s in laptops then they must be able to put them in network equipment, military hardware, embedded applications, etc? Why aren't x86 desktop processors more popular in those applications?
Also, you make a good point about the utility of the form factor. One could make arguments about desk or TV console real estate, but its really just the 'cuteness' that has appeal to so many people.
It may not be a rational desire, but I bet Apple will sell a ton of them.
The Mac Mini's ridiculously small case design is only possible because of the low power consumption of the PPC74xx/G4.
Even companies other than Apple have done similar things with the G4 a loong time ago, does anyone here remember the YellowDog Linux Briq
This is not just an x86 issue, even Apple will have a hard time putting a G5 in it's current Mac Mini Case.
Its the result of deeply pipelined processor designs. More latches, more stuff to clock, more power consumption and heat dissapation.
Ah, the good old days of 4 stage processors.
Fetch, decode, execute, commit/writeback.
That was it.
I left a decent IT support position back in 1998 as they were moving away from VMS and standardizing on NT. I went back to school to finish my BSECE degree, and now I do chip design -- I make almost twice as much money and I've worked on two fantastically groundbreaking microprocessors in the last four years.
Sometimes it works out, sometimes it doesn't.
The down side? Student Loans.
This is public now, so I can talk about it--
I worked on extending the accuracy and continuity of the VMX instruction vexptefp, see the patent application
here
My understanding is that this instruction is used to
compute Phong/specular hilights, and that previous implementations of this instruction were unusable because the lack of accuracy and continuity made it visually undesirable. We were able to improve the algorithm enough to be visually indistinguishable from a fully accurate non-estimate.
Can any software developers that use this instruction comment on this?
Is Phong hilighting mostly done on GPUs now?
Don't get me wrong, this is great and all,
(see a better article at EETimes)
but to implement microprocessor-complexity devices with single nanometer technology, we need single nanometer scale wires and the technology with which to 'draw' them onto silicon.
We already have enough trouble at 90nm with wiring, and it's only getting worse at 65nm.
This looks like a great leap in device technology, but we need similar advances in lithography to really use it.
Virtual PC Should be able to run
the low-end kids games pretty well, and you can compartmentalize the windows section, keep it from accessing the net, etc.
Hey, those new $499 mini Macs look perfect for the living area.
I guess you could do the same thing with WINE as well, but I'll let someone else try to sell that idea.
This isn't really a surprise, LPAR and Hypervisor are relatively easy to add to a microprocessor. I'd guess it's mainly adding an extra supervisor mode above the existing supervisor mode. Some control logic needs to be adjusted to take a privledged interrupt if a resource isn't allowed to be accessed in hypervisor mode.
Expect multithreading to be added soon as well, It's mainly just adding a thread bit to each pipeline, some extra control logic, and more registers.
For comparison, adding this stuff to the PPC970 as it is now is much easier than, say, adding VMX/Altivec to a stripped-down Power5.
Agreed, assuming the # of EEs is fixed. But if a company has the forsight to prepare for these problems such that the rate of large improvements can be maintained, everybody wins.
The industry knows about these problems, and I don't know about other companies,
But my company is hiring.
Yes, in the US.
And not just Co-ops, new hires and H1-Bs, but
also US citizens with lots of experience.
Sure, wire delay (and wiring in general) is a big problem,
but your post seems to imply that this advancement is worthless because wire delay is always the final limiting factor of a proc's clock speed. What about designs where a designer wants to cram a 16bit adder into a cycle using standard
cells and no custom layout? I bet device speed would be the limiting factor there.
Also faster devices will help with buffering long wires.
Sombody mod the parent up. The major challenges at 65nm aren't going to be the individual device speeds, but things like wiring, noise, leakage, and even electromigration. And designs are going to get far more complex as marketing drones realize that just dividing tasks into more and more stages to increase clock speed has diminishing returns and drives up power. As the parent mentioned, this added complexity will bring massive tool headaches.
That being said, I think all of this extra work will be good for the EE job sector, no?
Strained Si methods have been around for awhile. The PowerPC 970FX uses it, for example.
This method (called DSL, or "dual stress liner", not only stretches
the NFETs, it compresses the PFETs.
See a better article here.
And with Power5 being able to run multiple OSes in different virtual partitions concurrently (via Hypervisor, etc)
One could be running Linux for Apache,
AIX for whatever that's for,
And OS X for Photoshop.
Slashdot Mirror
Agreed -- in addition, the "PPC is better" crowd isn't necessarily changing their tune about the superiority of that architecture in its current form, they just realize that IBM can't afford to do backflips for that 2% of the market, and Apple can't afford to subsidize PPC development specific to their needs.
I think people will slowly start to realize the broad industry alignment here (Apple->Intel, MS,Sony->PPC, IBM sells PC business) makes good business sense all around in the long run, assuming Apple and Mac developers can survive the transition.
What?
No A shell ??
Actually this is less dissappointing that I originally thought --
A major problem as CMOS processes get smaller and smaller is wires and wiring. Its really bad at 90nm and it looks like its going to be way worse at 65nm.
Even if optical interconnects can just be used for long intra-unit busses (think L1 cache to fetch/decode unit, and there to integer unit and float unit, etc) we could see great performance gains.
Something like when the upper metal layers in CMOS went to copper a few years ago.
Ah yes, brutal dissappointment. As I read a bit further it looks like this is not optical logic.
pfth.
IBM is working in this area also . . .
Will be interesting to see a PowerPC with the guts of the VMX unit running at 10Ghz . . .
Ethanol.
There are many FFVs out now (Ford Explorer, and several other popular makes that I can't recall) that can use either regular gasoline, or E85, which is 85% ethanol.
Reduces dependence on foreign oil, burns cleaner, supports US companies.
See more info here
Why hasn't anyone brought up ethanol yet with all this talk of "running out of oil"?
Take a look at some mass-market-appeal type vehicles. Flexible Fuel Vehicles can use E85 (85% ethanol) or regular gasoline, just fill it up with either.
some more interesting info.
If you want to do project management, etc, get an MBA.
You may also want to get a second bachelors in another field that interests you.
Consider ASIC design -- much of the coming problems at smaller technologies (sub 65nm) will be with the software tools we use. Software engineers with good chip design/methodology understanding will be in high demand.
One other example -- If they can stuff x86 desktop processors into laptops why not put them in gaming consoles?
Certainly the developer support base for x86 is so much greater, it would be a no-brainer to go with a x86 solution.
Why, then, are all the next-gen game consoles likely to be PPC based?
That having been said, if PC manufacturers can shove a desktop P4 or Athlon64 in a laptop, they could also shove it into a approximately Mini-sized computer.
True, but can they do it and still have decent specs, very little fan noise and sell it for $500?
If they put P4s in laptops then they must be able to put them in network equipment, military hardware, embedded applications, etc? Why aren't x86 desktop processors more popular in those applications?
Also, you make a good point about the utility of the form factor. One could make arguments about desk or TV console real estate, but its really just the 'cuteness' that has appeal to so many people.
It may not be a rational desire, but I bet Apple will sell a ton of them.
The Mac Mini's ridiculously small case design is only possible because of the low power consumption of the PPC74xx/G4.
Even companies other than Apple have done similar things with the G4 a loong time ago, does anyone here remember the YellowDog Linux Briq
This is not just an x86 issue, even Apple will have a hard time putting a G5 in it's current Mac Mini Case.
Its the result of deeply pipelined processor designs. More latches, more stuff to clock, more power consumption and heat dissapation.
Ah, the good old days of 4 stage processors.
Fetch, decode, execute, commit/writeback. That was it.
It's a gamble, like many other things in life.
I left a decent IT support position back in 1998 as they were moving away from VMS and standardizing on NT. I went back to school to finish my BSECE degree, and now I do chip design -- I make almost twice as much money and I've worked on two fantastically groundbreaking microprocessors in the last four years.
Sometimes it works out, sometimes it doesn't. The down side? Student Loans.
This is public now, so I can talk about it--
I worked on extending the accuracy and continuity of the VMX instruction vexptefp, see the patent application here
My understanding is that this instruction is used to compute Phong/specular hilights, and that previous implementations of this instruction were unusable because the lack of accuracy and continuity made it visually undesirable. We were able to improve the algorithm enough to be visually indistinguishable from a fully accurate non-estimate.
Can any software developers that use this instruction comment on this?
Is Phong hilighting mostly done on GPUs now?
Clearly, in this scenario,
over time OpenVMS would become the defacto standard
on all macs, and BSD would still be dead, of course.
They misspelled:
The Devil -> Fortran I
Don't get me wrong, this is great and all, (see a better article at EETimes) but to implement microprocessor-complexity devices with single nanometer technology, we need single nanometer scale wires and the technology with which to 'draw' them onto silicon.
We already have enough trouble at 90nm with wiring, and it's only getting worse at 65nm.
This looks like a great leap in device technology, but we need similar advances in lithography to really use it.
Virtual PC Should be able to run
the low-end kids games pretty well, and you can compartmentalize
the windows section, keep it from accessing the net, etc.
Hey, those new $499 mini Macs look perfect for the living area.
I guess you could do the same thing with WINE as well, but I'll let someone else try to sell that idea.
I'm talking about the relative ease of implementation on the microprocessor. Hardware, not software.
Aren't their other reasons why they would have wanted to change the implementation between p4 and p5? Say, Performance? Chip area? Power?
Yes, but it's very difficult to crash the Hypervisor.
That's why LPAR is cool.
This isn't really a surprise, LPAR and Hypervisor are relatively easy to add to a microprocessor.
I'd guess it's mainly adding an extra supervisor mode above the existing supervisor mode. Some control logic needs to be adjusted to take a privledged interrupt if a resource isn't allowed to be accessed in hypervisor mode.
Expect multithreading to be added soon as well, It's mainly just adding a thread bit to each pipeline, some extra control logic, and more registers.
For comparison, adding this stuff to the PPC970 as it is now is much easier than, say, adding VMX/Altivec to a stripped-down Power5.
Agreed, assuming the # of EEs is fixed. But if a company has the forsight to prepare for these
problems such that the rate of large
improvements can be maintained, everybody wins.
The industry knows about these problems, and I don't know about other companies,
But my company is hiring.
Yes, in the US.
And not just Co-ops, new hires and H1-Bs, but also US citizens with lots of experience.
Sure, wire delay (and wiring in general) is a big problem,
but your post seems to imply that this advancement
is worthless because wire delay is always the
final limiting factor of a proc's clock speed.
What about designs where a designer wants to
cram a 16bit adder into a cycle using standard
cells and no custom layout? I bet device speed
would be the limiting factor there.
Also faster devices will help with buffering long wires.
Sombody mod the parent up. The major challenges at
65nm aren't going to be the individual device speeds,
but things like wiring, noise, leakage, and even electromigration.
And designs are going to get far more complex as
marketing drones realize that just dividing
tasks into more and more stages to increase
clock speed has diminishing returns and drives
up power. As the parent mentioned, this
added complexity will bring massive tool
headaches.
That being said, I think all of this extra work
will be good for the EE job sector, no?
Strained Si methods have been around for awhile. The PowerPC 970FX uses it, for example.
This method (called DSL, or "dual stress liner", not only stretches
the NFETs, it compresses the PFETs.
See a better article here.
Also, IBM is awesome.
And with Power5 being able to run multiple OSes in different virtual partitions concurrently (via Hypervisor, etc)
One could be running Linux for Apache,
AIX for whatever that's for,
And OS X for Photoshop.