It refers to data bus size. It's using a single PCI-Express lane for data transfer. If devices in the future require more bandwidth, more lanes can be added without much effort (first PCI-E graphics cards, for example, will be using a 16-lane bus which works in the exact same way.. except it has 16 lanes)
I think you're just being uninformed, and on top of it, you didn't read the article that you're criticizing.
Making a quick visit to the pricewatch would show you that Radeon 9000 Pro, which is one of the cards XP4 was being compared to, can be found for $81.
That's exactly the price target XP4 is going for, and it is performing less than 50% below R9000 Pro.
The review even talks about the driver issue, and how fully optimized drivers give another 20-30% performance improvement, which still won't be enough to reach the level of the competition.
I thought the world was on the backs of four elephants then a turtle.
For those who are not familiar this is a Terry Pratchett thing.
Actually, it's an old myth that's existed in some shape or form in almost every culture. The closest one is the Hindu myth, where "we find the idea of a lotus flower growing out of Vishnu's navel. Swimming in a pool in the lotus flower is the world turtle, on whose back stand four elephants facing in the four compass directions. On their backs is balanced the flat, disc-shaped world." (The Turtle Moves)
It's this old belief that inspired Terry Pratchett to come up with Discworld, which is "a geological pizza (only without the anchovies) on the back of a starturtle, called Great A'Tuin (sex unknown). The disc itself sits on the back on 4 elephants who stand on Great A'Tuin's meteor pocked shell. Occasionally one of them has to cock its leg to allow the sun to pass." (Turtles All the Way Down)
Re:Technology similar to clippy?
on
Smart Pool Table
·
· Score: 2
They didn't say that the technology was similar to clippy, it was based on it.
If your opponent has a lot of balls left on the table, and you have sunk all of yours and then the 8-ball, then you have a high score. Simple as that.:)
Maybe you and I should play some 9-ball for money:).
Re:Nothing new here
on
Tackling AGP 8X
·
· Score: 3, Informative
The parent poster was incorrect when quoting the PCI Express bandwidth capabilities. The initial bandwidth will provide 2.5Gb/s in each direction (or 200MB/s when overhead is included). That's a single lane, i.e. 2 pins. Up to 32 lanes can be used to provide necessary bandwidth. So, if you'd like, you could set up a 32x2.5Gb/s connection, or 80Gb/s, in each direction. That's a little over 6GB/s.
As the silicon technology improves, the maximum speed of the lane will increase to 10Gb/s, for a total of 320Gb/s in the widest implementation, or about 25GB/s.
Thanks, that's exactly what I need. I do remember seeing it in a store and finding the screen to be very dim. I was hoping that was just a problem with low batteries.. I'll check it out.
Exactly, I was surprised to see those two, which are usually only in more expensive units ($199+). A refurbirshed Visor Edge at $149 used to be the cheapest unit with rechargable batteries and USB.
If it had 4MB, I'd get one right now:(.
Anybody know any other PDAs with rechargable batteries, usb, and at least 4mb of ram at below $150?
Part of the issue was raised in a post a couple parents down, is if the CPU is starved for data, the extra clock speed won't do jack. And those that want the max performance would pay more for the fastest CPU AND get the most cache rather than trading off on cost factors.
But, my point is that the performance of another level of cache at the northbridge is much less than the extra 500MHz. None of the CPUs are curretly starved by the available bandwidth. Hungry, maybe, but there aren't many applications out there that even come close to requiring more than 3.2GB/s that the P4 can take in right now (4.2GB/s when we switch over to 133MHz FSB). So, 500MHz increase will matter in a large majority of applications.
Now, I agree with you (and have said so in my message) that a cache at the CPU side can make a difference. A $100 of cache with minimal latency from the CPU could be better than 500MHz.
How about huge L3 Cache? The problem with hyperthreading is that by definition it is going to cause a larger number of cache misses. Since you are maintaining 2 seperate contexts in one processor. In order to speed that up you are going to need more cache. Faster main ram will help, but won't solve it.
Another level of cache in the chipset is not going to help much. Integrating fast memory into the northbridge itself is prohibitive from the cost standpoint -- who's going to pay $100 more for a northbdirge when they can get another 500MHz added to their CPU for the same price, with much more impact? Using separate, high-speed DRAM that today's graphics cards use will bring the cost increase somewhat down, but the latency improves negligibly -- most of it is wasted on CPU to northbridge communication, and inside the northbridge itself, and the faster RAM might give you 5% latency increase.
So, any additional cache would have to be hooked up to the CPU directly to possibly produce results, and that's out of chipset designer's hands.
The best solution is, probably, to increase L2 cache size, or use a better sharing mechanism during hyperthreading to prevent two threads from thrashing each other's caches.
Why are we still on these crap buses and memories ? video cards (ATI 9700 I mean) can do 20 GB / sec data transfer. If I had that throughput for the main CPU, the PC would be vastly more powerful
Because the PCs would be a lot more expensive if 20 GB/s would have to provided to the CPU. First, the memory controller would have to be integrated into the CPU (which, mind you, AMD Hammer has, but not for b/w reasons, but latency.. the b/w is still the same), and would have to support 4 memory channels, increasing pin count by 200+ pins. That causes the CPU price to skyrocket. Then, the memory would have to run at DDRII-400MHz, instead of the 200 which you get from the fastest DDR available for PCs. That would increase the RAM prices dramatically. Finally, to handle those kinds of RAM speeds, the motherboards would have to grow to at least 6 layers, tripling the motherboard cost.
The question is -- who's going to do all that development work to sell it to a very small number of people who are willing to pay for that performance?
Standard interfaces for custom silicon - no, I'm not talking PCI-X or crap like that. There should be a standard interface directly to the chipset for people who want to do custom silicon ASICs and have them have direct access to the high-bandwidth internals of the chipset. I mean, even in the low end, why should a FCAL controller chip have to pass the PCI bus? Or a hard-core encryption coprocessor? Or a hardware routing ASIC? All need several GB of bandwidth directly to memory (or each other), and I can't see any reason not to have them surface mounted next to the north bridge with a dedicated interface.
Expect something like this in the early 2004, when 3GIO chipsets come out to production.. most will have 4+ side-ports directly to the northbridge to used as you please. The plan is to use them for peripherals, but you'd be free to attach anything that talks 3GIO. It probably won't be quite "a few GB of bandwidth", but that really depends on the chipset designer, and not a protocol/interface limitation.
Improved hyperthreading support - go check out the Ars Technica [arstechnica.com] article on this. Hyperthreading can potentially really help performance, but it's being held back by (among other things) problems with cache coherency and loading. While much of this is on the CPU (and thus, a chipset can't help), there are a bunch of stuff that could be moved into the chipset for help.
What usefull stuff can the chipset do for hyperthreading? I'd love to hear some ideas.
The high end looks very, very, very depressingly identical to the cheap consumer crap.
"Cheap consumer crap" is what sells the most, and most companies do not have the resources to do work on more than a couple of chipsets at a time, so most of the R&D time is spent on implementing the new standards and getting things to work at the new frequencies that CPUs and RAM require. Maybe things will get better when the economy picks up and high end becomes more profitable once again.
Yeah, the residents never seemed to care much about the destruction. That made it too easy to reorganize the city's districts at will.. which was fun, but a little unrealistic.
To raze a building, you should have to buy the building from the owner, first. That would make it a lot more expensive, and tougher, to clear out large sections of land.
Who the hell had the bright idea to tunnel under it? What's next, a tunnel from Boston to Washington, D.C. so they can smuggle more of our tax dollars out of there?
Duh. Is the road from Boston to Washington covered with buildings that are blocking the way?
At some level I was already aware that IC fabrication processes had reached the point at which even the largest features would be entirely invisible to the naked eye.
That's why we invited microscopes, right?:)
But, seriously, put that piece of "rock" under a good microscope, scratch the top off a bit, and you'll easily see the top level of metal. Scratch around it, and you'll see the layer below it.. Get a FIB machine, and you can drill all the way down to metal 1 and cut a wire and reconnect it somewhere else.
It's really the same as doing it on a breadboard, except you need really expensive machinery, and you have to be a little more careful where you put the wires:).
Testing should be confirmation of the design not fault finding.
I'm glad you said "should be" and not "is". Because, in reality, it almost never happens that way. You can rarely foresee every problem in the time that you have to verify a design.
One could argue that if you did find all the problems during the verification stage, you spent too much time on the verification. The rate of problem-finding near the end of the project is significantly slower than at the beginning, and some of these "late" problems can be found and fixed faster during the confirmation stage.
Of course, that will cost you more, but most of the time "schedule is King".
The few experienced engineers go home at 5 and always hit their deadlines.
Where I work, they stay all night trying to help those that are less experienced.
Everybody (up to the CEO) at ATI works in cubicles, as well. It's actually quite common in most techie companies.
Re:No wonder Nvidia is largely considered better!
on
Anand Tours ATI and NVIDIA
·
· Score: 5, Insightful
Try reading the article:
ATI imposed very strict restrictions on photographs during our visit to their offices in Thornhill, Ontario; we saw a lot of interesting things at ATI's offices (including the foundation for their fountain of fire in the lobby of their main building) but we weren't able to take pictures of most of them. On the other hand, ATI sat us down with one of their chip architects and we were able to get a wealth of information about how their GPUs were made.
NVIDIA wasn't able to set us up with any engineers for an extended period of time (although lunch with Chief Scientist, David Kirk is always informative) but they were much more lax on the picture front so we were able to bring you more of the behind the scenes from NVIDIA.
ATI just didn't want anybody taking pictures, but they were the one sharing the real information.
Slashdot Mirror
It refers to data bus size. It's using a single PCI-Express lane for data transfer. If devices in the future require more bandwidth, more lanes can be added without much effort (first PCI-E graphics cards, for example, will be using a 16-lane bus which works in the exact same way.. except it has 16 lanes)
The sad thing is that about 50 guys had to waste their time writing this patent.
50 guys? You must've never dealt with a patent lawyer. It takes one guy a couple of days to write 20 pages of that gibberish.
They're amazingly good at converting a simple diagram along with a couple of plain sentences into piles and piles of patent-speak.
Why would you want to inflict pain on them before you even know if they did violate GPL or not?
The Phantom Menace was so bad that no, I didn't go to see Episode 2. I'm sure e2 made way less money just because TPM was such a disappointment.
How long will it be before an FX board will be taxed by a new game?
This is one of the reasons why you need a faster card. 4200 is already overtaxed by UT2003 at 1024x768 with AA enabled.
The fact that AA can be disabled, and resolutions lowered, doesn't mean that a game can't make use of a faster card!
I think you're just being uninformed, and on top of it, you didn't read the article that you're criticizing.
Making a quick visit to the pricewatch would show you that Radeon 9000 Pro, which is one of the cards XP4 was being compared to, can be found for $81.
That's exactly the price target XP4 is going for, and it is performing less than 50% below R9000 Pro.
The review even talks about the driver issue, and how fully optimized drivers give another 20-30% performance improvement, which still won't be enough to reach the level of the competition.
I thought the world was on the backs of four elephants then a turtle.
For those who are not familiar this is a Terry Pratchett thing.
Actually, it's an old myth that's existed in some shape or form in almost every culture. The closest one is the Hindu myth, where "we find the idea of a lotus flower growing out of Vishnu's navel. Swimming in a pool in the lotus flower is the world turtle, on whose back stand four elephants facing in the four compass directions. On their backs is balanced the flat, disc-shaped world." (The Turtle Moves)
It's this old belief that inspired Terry Pratchett to come up with Discworld, which is "a geological pizza (only without the anchovies) on the back of a starturtle, called Great A'Tuin (sex unknown). The disc itself sits on the back on 4 elephants who stand on Great A'Tuin's meteor pocked shell. Occasionally one of them has to cock its leg to allow the sun to pass." (Turtles All the Way Down)
They didn't say that the technology was similar to clippy, it was based on it.
Since when is there a "high score" in 9-ball?
:)
:).
If your opponent has a lot of balls left on the table, and you have sunk all of yours and then the 8-ball, then you have a high score. Simple as that.
Maybe you and I should play some 9-ball for money
The parent poster was incorrect when quoting the PCI Express bandwidth capabilities. The initial bandwidth will provide 2.5Gb/s in each direction (or 200MB/s when overhead is included). That's a single lane, i.e. 2 pins. Up to 32 lanes can be used to provide necessary bandwidth. So, if you'd like, you could set up a 32x2.5Gb/s connection, or 80Gb/s, in each direction. That's a little over 6GB/s.
:)
As the silicon technology improves, the maximum speed of the lane will increase to 10Gb/s, for a total of 320Gb/s in the widest implementation, or about 25GB/s.
Now, that's a lot of bandwidth.
I think the original poster was referring to "PCI Express", but has incorrectly labeled it as PCI-X, which is a different standard.
PCI Express is what Intel has been pushing for a while and what will become the standard in mid-2004. It's also known as 3GIO.
Thanks, that's exactly what I need. I do remember seeing it in a store and finding the screen to be very dim. I was hoping that was just a problem with low batteries.. I'll check it out.
Exactly, I was surprised to see those two, which are usually only in more expensive units ($199+). A refurbirshed Visor Edge at $149 used to be the cheapest unit with rechargable batteries and USB.
:(.
If it had 4MB, I'd get one right now
Anybody know any other PDAs with rechargable batteries, usb, and at least 4mb of ram at below $150?
Part of the issue was raised in a post a couple parents down, is if the CPU is starved for data, the extra clock speed won't do jack. And those that want the max performance would pay more for the fastest CPU AND get the most cache rather than trading off on cost factors.
But, my point is that the performance of another level of cache at the northbridge is much less than the extra 500MHz. None of the CPUs are curretly starved by the available bandwidth. Hungry, maybe, but there aren't many applications out there that even come close to requiring more than 3.2GB/s that the P4 can take in right now (4.2GB/s when we switch over to 133MHz FSB). So, 500MHz increase will matter in a large majority of applications.
Now, I agree with you (and have said so in my message) that a cache at the CPU side can make a difference. A $100 of cache with minimal latency from the CPU could be better than 500MHz.
How about huge L3 Cache? The problem with hyperthreading is that by definition it is going to cause a larger number of cache misses. Since you are maintaining 2 seperate contexts in one processor. In order to speed that up you are going to need more cache. Faster main ram will help, but won't solve it.
Another level of cache in the chipset is not going to help much. Integrating fast memory into the northbridge itself is prohibitive from the cost standpoint -- who's going to pay $100 more for a northbdirge when they can get another 500MHz added to their CPU for the same price, with much more impact? Using separate, high-speed DRAM that today's graphics cards use will bring the cost increase somewhat down, but the latency improves negligibly -- most of it is wasted on CPU to northbridge communication, and inside the northbridge itself, and the faster RAM might give you 5% latency increase.
So, any additional cache would have to be hooked up to the CPU directly to possibly produce results, and that's out of chipset designer's hands.
The best solution is, probably, to increase L2 cache size, or use a better sharing mechanism during hyperthreading to prevent two threads from thrashing each other's caches.
Why are we still on these crap buses and memories ? video cards (ATI 9700 I mean) can do 20 GB / sec data transfer. If I had that throughput for the main CPU, the PC would be vastly more powerful
Because the PCs would be a lot more expensive if 20 GB/s would have to provided to the CPU. First, the memory controller would have to be integrated into the CPU (which, mind you, AMD Hammer has, but not for b/w reasons, but latency.. the b/w is still the same), and would have to support 4 memory channels, increasing pin count by 200+ pins. That causes the CPU price to skyrocket. Then, the memory would have to run at DDRII-400MHz, instead of the 200 which you get from the fastest DDR available for PCs. That would increase the RAM prices dramatically. Finally, to handle those kinds of RAM speeds, the motherboards would have to grow to at least 6 layers, tripling the motherboard cost.
The question is -- who's going to do all that development work to sell it to a very small number of people who are willing to pay for that performance?
Standard interfaces for custom silicon - no, I'm not talking PCI-X or crap like that. There should be a standard interface directly to the chipset for people who want to do custom silicon ASICs and have them have direct access to the high-bandwidth internals of the chipset. I mean, even in the low end, why should a FCAL controller chip have to pass the PCI bus? Or a hard-core encryption coprocessor? Or a hardware routing ASIC? All need several GB of bandwidth directly to memory (or each other), and I can't see any reason not to have them surface mounted next to the north bridge with a dedicated interface.
Expect something like this in the early 2004, when 3GIO chipsets come out to production.. most will have 4+ side-ports directly to the northbridge to used as you please. The plan is to use them for peripherals, but you'd be free to attach anything that talks 3GIO. It probably won't be quite "a few GB of bandwidth", but that really depends on the chipset designer, and not a protocol/interface limitation.
Improved hyperthreading support - go check out the Ars Technica [arstechnica.com] article on this. Hyperthreading can potentially really help performance, but it's being held back by (among other things) problems with cache coherency and loading. While much of this is on the CPU (and thus, a chipset can't help), there are a bunch of stuff that could be moved into the chipset for help.
What usefull stuff can the chipset do for hyperthreading? I'd love to hear some ideas.
The high end looks very, very, very depressingly identical to the cheap consumer crap.
"Cheap consumer crap" is what sells the most, and most companies do not have the resources to do work on more than a couple of chipsets at a time, so most of the R&D time is spent on implementing the new standards and getting things to work at the new frequencies that CPUs and RAM require. Maybe things will get better when the economy picks up and high end becomes more profitable once again.
Unless it's a typo, and they were talking about 9700, this yahoo news item talks about an AIW 9000.
Yeah, the residents never seemed to care much about the destruction. That made it too easy to reorganize the city's districts at will.. which was fun, but a little unrealistic.
To raze a building, you should have to buy the building from the owner, first. That would make it a lot more expensive, and tougher, to clear out large sections of land.
Who the hell had the bright idea to tunnel under it? What's next, a tunnel from Boston to Washington, D.C. so they can smuggle more of our tax dollars out of there?
Duh. Is the road from Boston to Washington covered with buildings that are blocking the way?
At some level I was already aware that IC fabrication processes had reached the point at which even the largest features would be entirely invisible to the naked eye.
:)
:).
That's why we invited microscopes, right?
But, seriously, put that piece of "rock" under a good microscope, scratch the top off a bit, and you'll easily see the top level of metal. Scratch around it, and you'll see the layer below it.. Get a FIB machine, and you can drill all the way down to metal 1 and cut a wire and reconnect it somewhere else.
It's really the same as doing it on a breadboard, except you need really expensive machinery, and you have to be a little more careful where you put the wires
Testing should be confirmation of the design not fault finding.
I'm glad you said "should be" and not "is". Because, in reality, it almost never happens that way. You can rarely foresee every problem in the time that you have to verify a design.
One could argue that if you did find all the problems during the verification stage, you spent too much time on the verification. The rate of problem-finding near the end of the project is significantly slower than at the beginning, and some of these "late" problems can be found and fixed faster during the confirmation stage.
Of course, that will cost you more, but most of the time "schedule is King".
The few experienced engineers go home at 5 and always hit their deadlines.
Where I work, they stay all night trying to help those that are less experienced.
Here's one for you right away.
The point is moot, anyway, since they're not really bundling the AOL client, but just Netscape (which is what the poster above is complaining about).
Everybody (up to the CEO) at ATI works in cubicles, as well. It's actually quite common in most techie companies.
Try reading the article:
ATI imposed very strict restrictions on photographs during our visit to their offices in Thornhill, Ontario; we saw a lot of interesting things at ATI's offices (including the foundation for their fountain of fire in the lobby of their main building) but we weren't able to take pictures of most of them. On the other hand, ATI sat us down with one of their chip architects and we were able to get a wealth of information about how their GPUs were made.
NVIDIA wasn't able to set us up with any engineers for an extended period of time (although lunch with Chief Scientist, David Kirk is always informative) but they were much more lax on the picture front so we were able to bring you more of the behind the scenes from NVIDIA.
ATI just didn't want anybody taking pictures, but they were the one sharing the real information.