If all computer chips had to be good at was pattern recognition, this would be true. This is, in fact, how signal processors work. However, general purpose computing involves many things that are often quite challenging to the human brain (branching for example). So I don't think emulating the human brain will provide a better general purpose computing architecture.
You should check out neural networks. They work based on the "do a bit and pass it along" principle. They're only good, however, for a certain subset of problems.
Looking at all processors for the past 10 years, they already *are* core/memory chips. More than half the processor die is cache. Also, the 80 core chip Intel made was indeed a network-on-chip architecture. This is true of Cell and many others. It's difficult to program and take advantage of but the payoff can be tremendous. Multiple small, scalar cores each with its own cache pocket (and a massively parallel memory interface).
Disregarding discrete memory in and of itself is unlikely to happen in the future IMO. Dedicated memory chips will always be denser than having small pockets of memory.
Exactly. Keep in mind that fiction does not need to be restrained by a rigid one-to-one mapping. It need not be cylons = terrorists, human = good guys.
In fact, the Cyclon occupation was an incredibly clever (IMO) portrayal of modern-day Iraq and the tension and mentality (on both sides) of an occupation. The Cyclons apparently have this new religion (monotheistic one stressing love and forgiveness) and its teachings stop them from just wiping out the humans on the colony. This is the role of the United States in Iraq currently. The humans are the insurgents. Some have gone along and accepted Cylon rule (and even helped them) while others continue fighting. The morality and view from both sides is explored.
The primary of which being suicide bombing. It wasn't a "oh noes! suicide bombing is bad and cannot be excused" mentality. It tread a fine line and explored the motivations behind such tactics. The desperation, the hatred, etc. It also explored how in resorting to such tactics, the humans were losing their humanity and that the cost of fighting was just too high in those cases.
The show is a wonderful allegory of modern day and has really portrayed its modern day equivalents in a light I had not thought anyone dared.
The bus is only supposed to take over chip-to-chip and chip-to-peripheral communications. Each chip will still have a dedicated (tri-channel in fact), low latency connection to memory.
One of the most impressive things about Quickpath is its self-calibration circuit. Makes making PCB's a lot easier and variations easier to deal with.
I don't think that's true. The P-N-P junctions still conduct in a FET. It's just that the control mechanism is a gate insulated with a dielectric. The control (base in BJT language) then does not need to actually supply current (unlike a BJT) to cause the channel (N channel in the case of PNP) to become conductive. The electric field produced by the gate-to-drain (Vgd) terminals (which have no current flowing through it) will cause the channel-to-drain junction to break down and conduct.
An abstract way to think of this is that a FET is a voltage-steered variable resistor (with non-linear properties beyond the linear region) whereas a BJT is a current-steered variable resistor (again, same thing).
I think you're confusing threshold voltage with supply voltage. A transistor with a lower threshold voltage will leak more. That's an inherent property of the transistor depending on its dimensions and the process.
The supply voltage (which is what's being scaled) is what's put onto the end of the MOSFET's that is attached to the source. The lower this voltage, the less leakage there will be. If this voltage is 0.0001V, there will be virtually no leakage as the transistor is pretty much powered down.
Yes and no. If all instructions were smaller in x86 (most popular CISC), I'd agree. But the variable instruction length really kills any memory performance advantages it has because all processors fetch in blocks (cachelines) and not individual instructions. Profiling really doesn't show x86 to have any instruction load advantage (in terms of instruction stalls due to memory) than, say, PowerPC processors.
One of the primary techniques introduced with the Banias line of processors was multi-VT cells. Since then all of the other major foundries have adopted this as well. Off the top of my head, IBM and TSMC both provide this. The high-VT cells use high threshold FET's that switch slowly but leak little. The low-VT cells leak a lot but switch very fast. You then choose, based on your design and timing margin for each circuit path, what cells to use. This cuts down power a lot if you have a lot of really fast paths that you can afford to use high-VT cells in.
This is becoming less and less true. Leakage power is a dominant if not *the* dominant factor nowadays. So even transistors that are idle will draw a significant amount of power. The problem becomes worse as transistors get smaller. The idea nowadays is not only to dynamically clock only circuits that are active (thus reducing unnecessary switching activity) but to scale and shut off the voltage supply when a transistor is not active. The MIT guy's website contains a previous design for a fast-tracking DC-DC converter that will be able to adjust the supply voltage fairly fast depending on the feedback control mechanism.
Their papers also present various circuit elements (particularly SRAM) that have been designed with sub-threshold logic and storage elements. The numbers, however, don't seem as impressive as I thought they'd be. ~500 mW for a 256KB SRAM block with dynamic voltage scaling.
Actually, scratch that. You'd probably want to bias the voltages coming out of the cell. Two paths, one to bias it by Vt-0.2V and the other Vt-0.4V and have them go to separate FET pairs.
Mathematically speaking, e is the most efficient base. Imagine a decode being a search tree and imagine the base being the number of children per node. A decode function is simply traversing the tree. The first level of the tree being the first bit, second level being the second bit, etc.
To find any number N, one would need a tree of L levels and B children per node at each level. B^L must then be >= N in order to guarantee that the number N is represented in the tree. We can then take this to mean that L = ln(N)/ln(B).
To do a full search of the tree in the worst case time T, would take T = (B^L)*S where S is the amount of time it takes to search and recognize each node. Substituting L:
T = S*B^(ln(N)/ln(B))
To find the base that would result in the lowest search time, take the double derivative of T with respect to B and find the roots (peak and valley where search time either maximizes or minimizes).
Turns out that there is only one positive root (negative base makes no sense) and that's at B = e and it's a minimum.
Each cell, being just a variable resistor, will output a certain amount of voltage. Let's assume a 1.2V supply:
00 = 0.0V 01 = 0.4V 10 = 0.8V 11 = 1.2V
You'd then do a crude A-D conversion (it's crude and small/lower power because it only needs to handle 4 distinct voltage levels). Off the top of my head, the smallest would be two pairs of N-FET and P-FET. One will have the threshold voltage biased at 0.2V and the other biased at 1.0V using a voltage divider from VDD to GND.
The output of the first pair of FETs would be bit 1 and the output of the second pair bit 0.
You can then either send these two bits in parallel or serialize them depending on the memory controller interface.
You'd have 1 less address decode line, yes but you'd have to store data 2 bits at a time and you'd have the extra latency of the "A-D conversion" circuit above.
Not really. If you think about it, fundamentally there just as many states a bunch of atoms can arrange itself in as counting electrons. You're really only bound by Plank's constant in how resistive or conductive a collection of atoms are. Assuming you had a device sensitive enough to detect the variation.
The trick is, of course, in how fast you can change those states. I would imagine electrons are much easier to move than whole atoms. I understand how read speed for PCM is faster than a transistor but writing....I don't know.
Depends on who you are. Intel is notorious in being able to pack tons of SRAM into a small die space and this isn't just due to process shrinks. There are all sorts of flavors of SRAM, the standard taking 6 transistors but some taking as little as 1 depending on density/speed trade-offs.
No, it's twice the amount of data. If you can store 1 bit, you have:
0, 1
Two bits:
00, 01, 10, 11
In order to double it again, we simply add another bit:
000, 001, 010, 011, 100, 101, 110, 111
Each binary digit doubles the data capacity. Just like each decimal digit results in 10x the capacity.
For any given number of bits per cell, n, we have 2^n combinations. This technology added one more bit, so it increased the amount of data storage by:
2^(n+1) / 2^n = 2
It only "doubled" because we started with n = 1. There's nothing inherent about how many more physical states are available that would suggest we have to be able to find them in orders of 2. The next breakthrough will most likely just add another state, i.e. another bit.
You'd be surprised how much of your computer isn't "binary" per se. If you have a modem, I think the standard is a base-16 transmission code. Flash memory currently contains 2-bits-per-cell cells. Hell, the quad-pumped signal going from memory to processor (if you have a Core 2 or P4) isn't "binary" per se.
I'm not sure about the density of PCM vs flash but one of the biggest advantages of flash right now is that it uses the same fabrication process as other semiconductors. It's still CMOS.
Consequently, you have economies of scale that translate from the other microelectronics markets. More importantly, you have one monolithic chip with control, interface, encryption logic, etc. all on one chip with one fab run. Many of our chip designs use small pockets of flash memory here and there (specially available from our fab vendor) for non-volatile storage. This not only makes flash more convenient, it also means that as process technology is pushed forward, so will flash.
The argument of "just buy stock in the company" fails to account for the fact that the amount of capital is restricted to begin with. Yes, over one's lifetime, a middle class man can save, put his 401k towards the right investments and retire with roughly the same income he had while working. That doesn't mean that others aren't using this exactly same method to make *much* more money and paying very little taxes.
This has a string of effects. The middle class man is taxed high because the wealthy are taxed less. The middle class man has less disposable income to invest. He then can reap a lot less benefits from corporate tax breaks and profits.
I'm not arguing we should steal from the rich and give to the poor. I'm arguing that *everyone* suffers if the middle class is left by itself to shoulder the tax burden and that allowing them to have more disposable income will benefit everyone, including the businesses who complain they have such a hard time making profit.
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If all computer chips had to be good at was pattern recognition, this would be true. This is, in fact, how signal processors work. However, general purpose computing involves many things that are often quite challenging to the human brain (branching for example). So I don't think emulating the human brain will provide a better general purpose computing architecture.
You should check out neural networks. They work based on the "do a bit and pass it along" principle. They're only good, however, for a certain subset of problems.
Looking at all processors for the past 10 years, they already *are* core/memory chips. More than half the processor die is cache. Also, the 80 core chip Intel made was indeed a network-on-chip architecture. This is true of Cell and many others. It's difficult to program and take advantage of but the payoff can be tremendous. Multiple small, scalar cores each with its own cache pocket (and a massively parallel memory interface).
Disregarding discrete memory in and of itself is unlikely to happen in the future IMO. Dedicated memory chips will always be denser than having small pockets of memory.
As if CS/Engineering majors needed their college experience to be even more of a sausage-fest.
Simple, what is legal is not 100% correlated with what is moral. In such cases, civil and legal dissent is a citizen's birthright.
Exactly. Keep in mind that fiction does not need to be restrained by a rigid one-to-one mapping. It need not be cylons = terrorists, human = good guys.
In fact, the Cyclon occupation was an incredibly clever (IMO) portrayal of modern-day Iraq and the tension and mentality (on both sides) of an occupation. The Cyclons apparently have this new religion (monotheistic one stressing love and forgiveness) and its teachings stop them from just wiping out the humans on the colony. This is the role of the United States in Iraq currently. The humans are the insurgents. Some have gone along and accepted Cylon rule (and even helped them) while others continue fighting. The morality and view from both sides is explored.
The primary of which being suicide bombing. It wasn't a "oh noes! suicide bombing is bad and cannot be excused" mentality. It tread a fine line and explored the motivations behind such tactics. The desperation, the hatred, etc. It also explored how in resorting to such tactics, the humans were losing their humanity and that the cost of fighting was just too high in those cases.
The show is a wonderful allegory of modern day and has really portrayed its modern day equivalents in a light I had not thought anyone dared.
Is the Cyber Commander's uniform a robe and wizard hat?
The bus is only supposed to take over chip-to-chip and chip-to-peripheral communications. Each chip will still have a dedicated (tri-channel in fact), low latency connection to memory.
One of the most impressive things about Quickpath is its self-calibration circuit. Makes making PCB's a lot easier and variations easier to deal with.
I can see it now. Searching for Barack Obama will turn out 50 links about how he is a Jihadist who supported Saddam Hussein in plotting 9/11.
9/11.
For a typical CMOS digital circuit, Vds will also be Vgs as far as I'm aware. So lowering supply voltage will decrease leakage.
I don't think that's true. The P-N-P junctions still conduct in a FET. It's just that the control mechanism is a gate insulated with a dielectric. The control (base in BJT language) then does not need to actually supply current (unlike a BJT) to cause the channel (N channel in the case of PNP) to become conductive. The electric field produced by the gate-to-drain (Vgd) terminals (which have no current flowing through it) will cause the channel-to-drain junction to break down and conduct.
An abstract way to think of this is that a FET is a voltage-steered variable resistor (with non-linear properties beyond the linear region) whereas a BJT is a current-steered variable resistor (again, same thing).
I think you're confusing threshold voltage with supply voltage. A transistor with a lower threshold voltage will leak more. That's an inherent property of the transistor depending on its dimensions and the process.
The supply voltage (which is what's being scaled) is what's put onto the end of the MOSFET's that is attached to the source. The lower this voltage, the less leakage there will be. If this voltage is 0.0001V, there will be virtually no leakage as the transistor is pretty much powered down.
Yes and no. If all instructions were smaller in x86 (most popular CISC), I'd agree. But the variable instruction length really kills any memory performance advantages it has because all processors fetch in blocks (cachelines) and not individual instructions. Profiling really doesn't show x86 to have any instruction load advantage (in terms of instruction stalls due to memory) than, say, PowerPC processors.
One of the primary techniques introduced with the Banias line of processors was multi-VT cells. Since then all of the other major foundries have adopted this as well. Off the top of my head, IBM and TSMC both provide this. The high-VT cells use high threshold FET's that switch slowly but leak little. The low-VT cells leak a lot but switch very fast. You then choose, based on your design and timing margin for each circuit path, what cells to use. This cuts down power a lot if you have a lot of really fast paths that you can afford to use high-VT cells in.
This is becoming less and less true. Leakage power is a dominant if not *the* dominant factor nowadays. So even transistors that are idle will draw a significant amount of power. The problem becomes worse as transistors get smaller. The idea nowadays is not only to dynamically clock only circuits that are active (thus reducing unnecessary switching activity) but to scale and shut off the voltage supply when a transistor is not active. The MIT guy's website contains a previous design for a fast-tracking DC-DC converter that will be able to adjust the supply voltage fairly fast depending on the feedback control mechanism.
Their papers also present various circuit elements (particularly SRAM) that have been designed with sub-threshold logic and storage elements. The numbers, however, don't seem as impressive as I thought they'd be. ~500 mW for a 256KB SRAM block with dynamic voltage scaling.
Actually, scratch that. You'd probably want to bias the voltages coming out of the cell. Two paths, one to bias it by Vt-0.2V and the other Vt-0.4V and have them go to separate FET pairs.
Mathematically speaking, e is the most efficient base. Imagine a decode being a search tree and imagine the base being the number of children per node. A decode function is simply traversing the tree. The first level of the tree being the first bit, second level being the second bit, etc.
To find any number N, one would need a tree of L levels and B children per node at each level. B^L must then be >= N in order to guarantee that the number N is represented in the tree. We can then take this to mean that L = ln(N)/ln(B).
To do a full search of the tree in the worst case time T, would take T = (B^L)*S where S is the amount of time it takes to search and recognize each node. Substituting L:
T = S*B^(ln(N)/ln(B))
To find the base that would result in the lowest search time, take the double derivative of T with respect to B and find the roots (peak and valley where search time either maximizes or minimizes).
Turns out that there is only one positive root (negative base makes no sense) and that's at B = e and it's a minimum.
Each cell, being just a variable resistor, will output a certain amount of voltage. Let's assume a 1.2V supply:
00 = 0.0V
01 = 0.4V
10 = 0.8V
11 = 1.2V
You'd then do a crude A-D conversion (it's crude and small/lower power because it only needs to handle 4 distinct voltage levels). Off the top of my head, the smallest would be two pairs of N-FET and P-FET. One will have the threshold voltage biased at 0.2V and the other biased at 1.0V using a voltage divider from VDD to GND.
The output of the first pair of FETs would be bit 1 and the output of the second pair bit 0.
You can then either send these two bits in parallel or serialize them depending on the memory controller interface.
You'd have 1 less address decode line, yes but you'd have to store data 2 bits at a time and you'd have the extra latency of the "A-D conversion" circuit above.
Not really. If you think about it, fundamentally there just as many states a bunch of atoms can arrange itself in as counting electrons. You're really only bound by Plank's constant in how resistive or conductive a collection of atoms are. Assuming you had a device sensitive enough to detect the variation.
The trick is, of course, in how fast you can change those states. I would imagine electrons are much easier to move than whole atoms. I understand how read speed for PCM is faster than a transistor but writing....I don't know.
Depends on who you are. Intel is notorious in being able to pack tons of SRAM into a small die space and this isn't just due to process shrinks. There are all sorts of flavors of SRAM, the standard taking 6 transistors but some taking as little as 1 depending on density/speed trade-offs.
No, it's twice the amount of data. If you can store 1 bit, you have:
0, 1
Two bits:
00, 01, 10, 11
In order to double it again, we simply add another bit:
000, 001, 010, 011, 100, 101, 110, 111
Each binary digit doubles the data capacity. Just like each decimal digit results in 10x the capacity.
For any given number of bits per cell, n, we have 2^n combinations. This technology added one more bit, so it increased the amount of data storage by:
2^(n+1) / 2^n = 2
It only "doubled" because we started with n = 1. There's nothing inherent about how many more physical states are available that would suggest we have to be able to find them in orders of 2. The next breakthrough will most likely just add another state, i.e. another bit.
You'd be surprised how much of your computer isn't "binary" per se. If you have a modem, I think the standard is a base-16 transmission code. Flash memory currently contains 2-bits-per-cell cells. Hell, the quad-pumped signal going from memory to processor (if you have a Core 2 or P4) isn't "binary" per se.
I'm not sure about the density of PCM vs flash but one of the biggest advantages of flash right now is that it uses the same fabrication process as other semiconductors. It's still CMOS.
Consequently, you have economies of scale that translate from the other microelectronics markets. More importantly, you have one monolithic chip with control, interface, encryption logic, etc. all on one chip with one fab run. Many of our chip designs use small pockets of flash memory here and there (specially available from our fab vendor) for non-volatile storage. This not only makes flash more convenient, it also means that as process technology is pushed forward, so will flash.
PCM seems limited to non-volatile storage.
Depending on who you're marrying, it might be amazingly appropriate.
I cannot let you do that.
The argument of "just buy stock in the company" fails to account for the fact that the amount of capital is restricted to begin with. Yes, over one's lifetime, a middle class man can save, put his 401k towards the right investments and retire with roughly the same income he had while working. That doesn't mean that others aren't using this exactly same method to make *much* more money and paying very little taxes.
This has a string of effects. The middle class man is taxed high because the wealthy are taxed less. The middle class man has less disposable income to invest. He then can reap a lot less benefits from corporate tax breaks and profits.
I'm not arguing we should steal from the rich and give to the poor. I'm arguing that *everyone* suffers if the middle class is left by itself to shoulder the tax burden and that allowing them to have more disposable income will benefit everyone, including the businesses who complain they have such a hard time making profit.