Slashdot Mirror

Though isn't eMMC basically the same: it's like the old MMC cards (i.e. SD without any of the dumb crap that no one uses) over a circuit board traces, rather than a fixed socket?

eMMC is really bad marketing because with that name you associate it with the pre-SD MMC, where it's really more towards the SSD side than the SD/MMC side, although it's definitely a poor man's SSD. Think of it as an SSD alternative for phones and tablets, which is the most common application area. (eMMC 5.1 is the current standard, with SSD-like speeds possible. They just should've called it nanoSSD or something rather than MMC anything.

so I brought the 3000 home, snapped a shot of the ram and found it's not Sram and it's not Dram
it's called static column ram - which is as close to Sram as you can get (but not Sram, yet we called it that).

Its not close to sram at all other than similarly sounding name, as I wrote in previous post it is an improved variant of page mode DRAM:
>and here a definition of "static column mode" in case you would somehow think this means SRAM: https://www.jedec.org/standard...

even wiki has a section on it https://en.wikipedia.org/wiki/...

In fact if you search for 9A9Z you get all sorts of answers of what it is.

datasheet: http://datasheet.datasheetarch...
a big hints are
-a whole timing diagrams section on refresh
-multiplexed address bus
-fact 4Mbit sram chips didnt exist until 1993, and when they first showed up they were >$140 a pop!!!
-and fifth word of the datasheet reading 'dynamic' :-)

This ram allows the same search and grab as Sram,

Now we are moving 2 posts back. You are confusing two separate things, type of ram and ability to recover data after reset. Those two are independent.
  Both types of ram will keep its data mostly intact over a reset, and somewhat intact after total power loss depending on process size, temperature, time etc.
  Difference between SRAM and DRAM is in physical construction. One uses multiple(4-8) transistor latch arrangement - you put logic level in and it stays there until powered down. The other uses _one_ transistor and capacitor and needs frequent refresh (recharging that capacitor).

  More transistors to build sram means more expensive, around x10 was the minimum. This is why in the nineties a 256KB sram cache for a PC motherboard cost around the same as 4MB simm. This price difference (and use of slow processors) was the reason not a single Amiga featured sram.

there is no sram in amigas (except for 768 bytes of palette inside Lisa chip)
The difference between sram and dram is _not_ that one of them can keep the data over a reset, its that one of them keeps data without explicit _refresh cycles_ when rest of computer is powered down completely. Reboot is not doing ANYTHING to ANY type or ram. Resetting a running computer without stopping current program was standard on Intel 286 (dram simms) when switching from protected mode back to real addressing: https://blogs.msdn.microsoft.c... Windows 2 and XMS could do it multiple times per second, this was early nineties.

This is Amiga 3000 dram: http://www.ubbcentral.com/stor...

as seen on page 6 of schematic http://www.amigawiki.de/dnl/sc...
here is detailed specs: http://amiga.resource.cx/mod/a...
and here a definition of "static column mode" in case you would somehow think this means SRAM: https://www.jedec.org/standard...
even scan doubler FRAM is based on DRAM

so again, there never was any sram in amigas

ps: I fix computers on a component level since nineties :/

http://www.jedec.org/sites/def...

What, you fucking moron? They most certainly assist in specifying safety regulations for how workers should handle radiated things in certain manufacturing environments.

Try again when you've make equipment following some of their standards.

You cannot assume that that the reported data rate (slide 7) is decreased due to 8b/10b encoding.

As in gigabit ethernet, the media appears to be reporting a data rate where the signalling rate would be ((10b/8b)-1) higher (e.g., in gigabit ethernet, 1.25 Gbps). That being said, it could easily be the reverse and people are mistakenly reporting the signalling rate as a data rate.

I don't work in this area, so I can't say. I've gotten as close to an "official" source as I can in the first link.

Did not make it up, or at least not on purpose. Link: http://www.jedec.org/sites/def... Go to page 24 "Endurance Rating" and you see the last requirement is: "4) the SSD retains data with power off for the required time for its application class." Then go down to page 25 and you will see that the above "required time for its application class" for a "client class" device is 1yr. This is consistent with many NAND device datasheets that I've been dealing with. It is common to spec 10 years min power off data retention when new and 1 year when they've reached their max write rating.

Why is it so hard for you aspyrons to understand that the meaning of a word is often dependent on context?

Well, maybe because almost all the international standards organizations actually agree that there's a single meaning now (even though they disagreed in the past).

In a decimal context, kilo means 1000. In a binary context, it means 1024. Most of the people that pretend to have difficulty understanding this are actually making money from their 'confusion' - what's your excuse?

Look, what the GP said was factually accurate:

the IEEE, ISO and SI standards all agree that kilobyte means 1000 bytes, and megabyte means 1000000 bytes.

The IEC adopted these in 1998, leading to full adoption by the IEEE in 2005. SI explicitly defines kilo ONLY to mean 1000, and though bytes are not technically SI units, they regard any other use of the prefixes as incorrect.

The only large body that has endorsed the use of your system in the past decade is JEDEC, though they insist on capital letters, i.e., K, M, and G, instead of the standard SI lower-case. So, a kilobyte (kB) to them is actually 1000 bytes, while a Kilobyte (KB or K) is 1024.

Recently, if you read even JEDEC's standards from 2012, you'll note that they quote the IEEE standards and say the older style "frequently leads to confusion and is deprecated."

So, I don't know about the GP, but my "excuse" for following standard SI style is that basically all international standards bodies agree that "kilo" means 1000, and if you want to have a term for 1024, you should use something else.

Now, the reality of the world is that many hardware manufacturers and such still retain older deprecated usages. But GP's statement was basically accurate. There's no reason to go around insulting people when they state factual information.

You want to keep using a standard that has confused people for decades when the international standards organizations deprecate it because it's confusing? That's your choice. But what's your excuse for attacking people?

I tried to punt the details here toward the references provided, but you raise a good question: why not just use the lifetime percentage exposed at attributed 202/0xCA "Percent Lifetime Remaining". There's two problems with that data.

First off, that SMART attribute hasn't been consistent since the drive was released. See M500 960GB MU03 SMART Issue as one observation about the biggest firmware change. I believe that happened after the Tech Report review. The fact that Crucial changed exposing wear data over the life of the drive is itself enough to get it booted from some companies as an immature product.

But let's say you consider that ancient history now. The other side of the complaints here is that the M500 doesn't give wear data in terms of bytes written. If you have two M500 drives that show identical wear data as measured by 202/0xCA, what does that tell you about their respective workloads? Unfortunately, it doesn't tell you anything useful for that purpose without more context. And that's a critical failure for the standard way such things are rated and evaluated now.

Intel publishes white papers for the recommended drive in TFA like DC S3500 Series RAID Workload Characterization, and that gives a lot of data about how to compare production deployments against drive specifications. I did exactly that for their earlier drives in the blog article I referenced.

There's just not quite enough data available from a Crucial M500 to do a similar analysis on it. "Erase count" is really an implementation detail specific to the drive; you can't compare those across different manufacturers. The most useful standard that aims to eliminate the workload specific aspect from lifespan ratings is JESD218. That also looks at lifetime in terms of terabytes written. There are some really fundamental detaisl that so far seem missing on Crucial's drives. You can back out write data from some of the other statistics, but without a hard published spec for such things I don't consider that very useful.

One thing not mentioned in the article or summary is whether or not this technology reduces standby power consumption in DRAM.

POD by itself doesn't reduce power consumption in standby, since both POD and SSTL turn off the bus drivers then. The older POD technologies from the GDDR families use Thevenin termination, though, so the terminators draw a lot of unnecessary current when they're enabled (as distinct from the result with a dedicated termination supply.)

If you really want to know how this all works, JEDEC has the DDR4 standard available for free download. Follow the "free standards" link.

I have no idea what you are talking about. My guess is 'WP' refers to "Washington Post." To use the 'SD' logo, the cards must implement the DRM:

Having a proven record in DVD, this (CPRM) is enhanced in SD memory cards through the use of "key revocation" technology built into each card.

The card's control circuitry allows data to be read and written (in its protection area) only when appropriate external devices are detected. A check-out (copying) from a PC to the SD memory card is restricted to three copies in compliance with the SDMI specification. All SD-Audio products comply with SDMI.

The SD card copyright protection function has the following features:

• Access to an SD memory card must be enabled by authentication between devices
• random number is generated each time there is mutual authentication and exchange of security information

- http://www.sdcard.org/developers/tech/

I don't find DRM'd cards trustworthy because they are designed to fail in sometimes unpredictable ways. My storage devices have no knowledge of copyright laws, so should not try to enforce them when I am trying to boot from a "known good" filesystem!

I just hope the upcoming Universal Flash Storage (UFS) is a viable floppy replacement. I am not optimistic, as if I had read the proposed standard, I would not be allowed to provide you with that link.

Trojans are easy enough to get rid of with: # dd if=/dev/zero of=/dev/sda
Where /dev/sda is your flash device.

Space requirements.

Biggest DDR3 SO-DIMM modules I could find were 4 GB. They are 30 mm x 66.7 mm and the standard allows for

The DDR3 SO-DIMM is designed for a variety of maximum component widths and maximum lengths, refer to the applicable raw card for exact componet size allowed. Components used
in DDR3 SO-DIMMs are also limited to a maximum height (as shown in dimension "A" of MO-207) of 1.35 mm. [page 19]

You now have an absolute minimum size of 2,701.35 mm^3 (1.35 mm x 30 mm x 66.7 mm), or 675.3375 mm^3/GB. This is a very very idealized minimum by the way.

An Intel 2½" drive is 49,266.28 mm^3 (100.4 mm x 7 mm x 70.1 mm) and currently maxes out at 160 GB leaving you with 307.91425 mm^3/GB. That's 46% of the space that would be needed for DDR3 RAM. Add to that that Intel's 2nd generation SSDs are only using one side of the PCB, and you can expect the storage space requirements to be halved.

Then there's the fact that the SSDs are directly replaceable. In other words, they don't need to rebuild the computer, buy super special boards or anything like that - you can replace a harddrive with an SSD without having to spec out a new supercomputer.

In the end, if you wanted to replace the system with something that could provide 1 TB of RAM per node, they would need a VERY expensive system. Even with 8 GB modules, you would need to somehow fit 128 of them onto a board. I'd really love to see the mother- and daughter-boards involved with that.

In the end it doesn't just come down to raw price or speed of the storage device (RAM vs SSD vs HDD vs tape), but also all the other factors involved, such as space, power, heat and the stuff you need to use it (i.e. a brand new super computer that can support 1 TB RAM/node vs 48 GB at the moment.

Or to use a really bad car analogy, some company has found out that using a BMW M5 Touring Estate gives them faster deliveries than using a Ford Transit. Now you're suggesting that they should be delivering stuff via aeroplanes. Yes, it's much faster, but you need a brand new transportation structure built up around this, which you also need to factor into your cost assessments.

While I accept quantum mechanics and its power to describe the sub atomic universe, I still have no idea where this claim about QM being used in the development of the transistor comes from. I learned about transistors using a theory of electrons and "holes" and in fact this viewpoint comes from no lesser source than Shockley himself.

I've never seen a theoretical description of any transistor device that required any form of quantum mechanics for its explanation. Given the fact that transistors are to this day, macroscopic devices, I still fail to see how QM comes into their theoretical explanation. It's a subatomic theory.

Your education was sufficient but incomplete. Note that the Fowler-Nordheim effect was first identified in 1928: http://en.wikipedia.org/wiki/Field_emission

Typical semiconductor QA testing of transistors includes not only hot carrier testing (small channel length in mosfets lead to high electric fields localized close to drain terminals, high electric fields cause energetic carriers that cause interface states or become trapped in oxide) for electron traps and holes, but the principle subtest of hot carrier testing is a gate voltage sweep to establish the gate switching threshold and subthreshold levels. And that voltage threshold test can be used to evaluate semiconductor integrity - as indicated by tunneling.

Here's a sample of an older testing specification: http://www.jedec.org/download/search/jesd28a.pdf

Please note Annex C of this JEDEC testing document: http://www.jedec.org/download/search/jesd35a.pdf

So, not only are quantum effects a theoretical part of how a transistor works, today's semiconductor manufacturers regularly design their semiconductor geometry taking those effects into account, and can test for design success.

You are aware that modern semiconductor QA testers can measure down to the femto-amp and atto-amp levels?

As we squeeze more and more transistors into a given space - smaller and smaller devices - tunneling is more and more critical.

While I accept quantum mechanics and its power to describe the sub atomic universe, I still have no idea where this claim about QM being used in the development of the transistor comes from. I learned about transistors using a theory of electrons and "holes" and in fact this viewpoint comes from no lesser source than Shockley himself.

I've never seen a theoretical description of any transistor device that required any form of quantum mechanics for its explanation. Given the fact that transistors are to this day, macroscopic devices, I still fail to see how QM comes into their theoretical explanation. It's a subatomic theory.

Your education was sufficient but incomplete. Note that the Fowler-Nordheim effect was first identified in 1928: http://en.wikipedia.org/wiki/Field_emission

Typical semiconductor QA testing of transistors includes not only hot carrier testing (small channel length in mosfets lead to high electric fields localized close to drain terminals, high electric fields cause energetic carriers that cause interface states or become trapped in oxide) for electron traps and holes, but the principle subtest of hot carrier testing is a gate voltage sweep to establish the gate switching threshold and subthreshold levels. And that voltage threshold test can be used to evaluate semiconductor integrity - as indicated by tunneling.

Here's a sample of an older testing specification: http://www.jedec.org/download/search/jesd28a.pdf

Please note Annex C of this JEDEC testing document: http://www.jedec.org/download/search/jesd35a.pdf

So, not only are quantum effects a theoretical part of how a transistor works, today's semiconductor manufacturers regularly design their semiconductor geometry taking those effects into account, and can test for design success.

You are aware that modern semiconductor QA testers can measure down to the femto-amp and atto-amp levels?

As we squeeze more and more transistors into a given space - smaller and smaller devices - tunneling is more and more critical.

I hope everyone just refuses to do business with Rambus and let it go bankrupt.

In a way, the problem is self-solving in that regard. Rambus is no longer a member of JEDEC, and you can bet that anyone associated with JEDEC (which includes the memory manufacturers) is probably going to consider Rambus a perpetual "second choice" for RAM tech. In the end, they need to sell their product to survive beyond the patent expiration of the stuff they slipped into SDRAM on the sly, and making a name for yourself as a "bad faith" company is a bad way to do that.

Further work is ongoing within JEDEC, IPC, iNEMI, and other groups to further refine industry practices. See http://thor.inemi.org/webdownload/newsroom/Presentations/Sn_Whisker_Symposium_2008.pdf for one example of this.

Further work is ongoing within JEDEC, IPC, iNEMI, and other groups to further refine industry practices. See http://thor.inemi.org/webdownload/newsroom/Presentations/Sn_Whisker_Symposium_2008.pdf for one example of this.

1. VESA
2. The Open Group
3. IEEE
4. GSM
5. The Unicode Consortium
6. Bluetooth SIG
7. CAN
8. EIA (responsible for, among other things, JEDEC, who are responsible for DDR and related standards)

Fortunately, most standards bodies got reality: charging outrageous fees for copies of their publications was horribly cost-ineffective for the industries that they supposedly served; there are other ways to raise those relatively small sums.

Today most standards documents are available online for free. The standards bodies seem to have survived the change. Maybe it's time for academic publishing to do the same.

Regarding your comment on cost-effective packaging for optical ICs:

You want to use standard connectors for optical fibres mounted on standard IC packages. OK. Now please solve these problems also:

1) The reliability of sockets mounted on low cost mold injection plastic packages: I doubt such a package can survive a) thermal shock testing b) temp cycling (-40 degC to 85 degC) to the extent that it can actually pass standard JEDEC requirements. The difference in coefficient of thermal expansion will kill you

2) If it does, I doubt you can call it cost effective, if you consider other connectorized packages, even just electrical connectors (>$50 just for the package...) Cost effective packaging is usually less than $1 per device for small scale devices.

The only viable commercial solution I am aware of is the one seen here. And it's not even that inexpensive.

In response to your quotes I went and looked on Molex's site. Since we're talking about video ram here, I decided to look up the spec for the SGRAM JEDEC 144 SODIMM modules used on video cards.

The spec says that the contact resistance is 70 milliohms max, and at a test frequency of 100Khz the stray capacitance between pins is a max of 2 pF.

What this all boils down to is that it's really irrelevant.

All the communication lines of boths DIMMS (have 2 sitting in front of me) and SGRAM SODIMMs are loaded with 10 ohm resistor arrays. This means that any stray capacitance or resistance is overcome by the 10 ohm loading.

They are already doing high speed clocks to DIMMs, close to the speeds that video cards are doing on board.

The REAL crux is that it's A LOT cheaper to manufacture the board with the components already attached. Your footprint is smaller too.

Refer to these documents for further information:

JEDEC SGRAM 144PIN SODIMM video ram specification

Molex SGRAM socket specification

With trademarks, you must actively defend what you have; otherwise a court may find that you failed to defend your mark against "dilution," and you will lose the ability to sue over another party's use of your mark. This is especially true if the mark passes into common, everyday use like Band-Aid or Kleenex.

With patents, no such obligation exists. In fact, I can think of a number of instances in which companies deliberately did not act to prevent the initial widespread adoption of their patented technology -- the idea is to get it adopted as widely as possible, preferably as an accepted standard. Once that happens, then they sue everyone in sight. This is often referred to as a "submarine patent"; two good recent examples of companies waiting for widespread adoption before suddenly starting to demand royalties from everyone are the Rambus DRAM patent nonsense in JEDEC and Fraunhofer's patents on MP3.

I protest, this chip is obviously not JEDEC compliant and is therefore prone to silent failure. RMS and EFF ought to kick their asses.

The two big reasons for the generational change are

• Voltage change: DDR II is going to 1.8 volts to allow thinner gate oxides and denser, faster devices.
• Internal timing. First-generation DDR has some architectural timing issues which make it impossible to go much beyond 333 in volume production.

Yes, this makes for backward-compatibility problems.

Yes, the Committee (JC-42.3) put a huge amount of work into making DDR-II as backward-compatible as possible

Yes, we're starting work on DDR-III. You'll have to wait until 2006 or so.

Target speeds for DDR-II were set at 600 MT/s for fully-loaded systems and 800 MT/s for embedded stuff like graphics.

The signal-integrity issues for DDR-II are ugly, but we met the margin specs with lots of conservativism thrown in, so once we get hands-on time with systems you'll probably see the numbers exceeded just as the original DDR targets were.

Flame away. You can get more info at JEDEC or Advanced Memory International.

First of all, basic rules. The legal guide (and other documents) stipulate that members will participate in good faith (Section C.1) and no restraint of trade activities of any kind will take place (Section A.1), and that JEDEC will not police or audit its members or their reports to the organization (Section E). It's a pretty open organization.

Now for the heavy lifting. The JEDEC Manual has a lot of interesting stuff in it, especially in Section 7.3 which deals with use of Patented Products. First and foremost, JEDEC does not care if patented tech is used, but it does require that the holder agree to grant licenses freely or for a reasonable fee. And as some people have been asking, members must disclose 'any knowledge they may have of patents, or pending patents, that might be involved in the work they are undertaking.' (emphasis mine) Also notice the word 'might', I assume this means if you're not sure, say so anyways, good faith and disclosure and all that. So all members are aware of this clause, it is quite important because the front cover of all publications must include a blurb about patent compliance, all tech referencing patented technology must be noted, and footnotes must say 'compliance with this section of the document requires the use of patent No. xxxx' (or patent has been applied for...), this is described in Section 7.3.1

FYI and draw our own conclusions (IANAL).

First of all, basic rules. The legal guide (and other documents) stipulate that members will participate in good faith (Section C.1) and no restraint of trade activities of any kind will take place (Section A.1), and that JEDEC will not police or audit its members or their reports to the organization (Section E). It's a pretty open organization.

Now for the heavy lifting. The JEDEC Manual has a lot of interesting stuff in it, especially in Section 7.3 which deals with use of Patented Products. First and foremost, JEDEC does not care if patented tech is used, but it does require that the holder agree to grant licenses freely or for a reasonable fee. And as some people have been asking, members must disclose 'any knowledge they may have of patents, or pending patents, that might be involved in the work they are undertaking.' (emphasis mine) Also notice the word 'might', I assume this means if you're not sure, say so anyways, good faith and disclosure and all that. So all members are aware of this clause, it is quite important because the front cover of all publications must include a blurb about patent compliance, all tech referencing patented technology must be noted, and footnotes must say 'compliance with this section of the document requires the use of patent No. xxxx' (or patent has been applied for...), this is described in Section 7.3.1

FYI and draw our own conclusions (IANAL).

First of all, basic rules. The legal guide (and other documents) stipulate that members will participate in good faith (Section C.1) and no restraint of trade activities of any kind will take place (Section A.1), and that JEDEC will not police or audit its members or their reports to the organization (Section E). It's a pretty open organization.

Now for the heavy lifting. The JEDEC Manual has a lot of interesting stuff in it, especially in Section 7.3 which deals with use of Patented Products. First and foremost, JEDEC does not care if patented tech is used, but it does require that the holder agree to grant licenses freely or for a reasonable fee. And as some people have been asking, members must disclose 'any knowledge they may have of patents, or pending patents, that might be involved in the work they are undertaking.' (emphasis mine) Also notice the word 'might', I assume this means if you're not sure, say so anyways, good faith and disclosure and all that. So all members are aware of this clause, it is quite important because the front cover of all publications must include a blurb about patent compliance, all tech referencing patented technology must be noted, and footnotes must say 'compliance with this section of the document requires the use of patent No. xxxx' (or patent has been applied for...), this is described in Section 7.3.1

FYI and draw our own conclusions (IANAL).

Rambus is one of the primary members of JEDEC, a coalition between major players in the semiconducter industry. Several years ago, when the major players of JEDEC got together and finalised the SDRAM standard, and later the DDR SDRAM standard, Rambus provided key technology to make those standards possible.

Hemos, you seem to think that Rambus stay's in business by charging frivolous lawsuits against other memory manufacturers. Fortunately, that is far from the truth. Rambus is an intellectual property corporation, meaning they devote their resources to inventing the technology that makes todays high speed memory possible, but they do not actually manufacturer memory. That is where liscensing fees come into play. Rambus liscenses their technology to other manufacturers who actually produce the DIMMs. Sadly, Micron and Hundai seem to think that it's okay for them to manufacture memory using stolen technology with out any legal repercussions. I certainly hope our court system will do The Right Thing and smack Micron and Hundai with some major penalties to make up for their theft and corporate espionage.

• Not really surprising. Engineering by fiat fails if trumped by a Higher Authority (e.g., physics)
  
• The problem isn't the Camino chip, it's the physics. Turns out that Rambus has a major signal-integrity failure mode that sort of got swept under the rug until the systems houses got bit by it.
  
• The DRAM companies never liked Rambus, but had their arms twisted by Intel. Now they have a chance to bail and are taking it.
  
• The comment about DDR (double-data-rate SDRAM) having no standard will come as quite a surprise to the people at the memory companies and in particular JEDEC's JC-42 memory committee, which thinks that they have issued one, and AMII, which is sponsored by the memory industry (including NEC and Samsung) to promote its use.