Intel Demos New P4 'Extreme Edition'

typobox43 writes "Louis Burns of Intel displayed a "high-definition video stream running on a 'mystery' desktop processor." This processor turned out to be the new Intel Pentium 4 Extreme Edition 3.20 GHz, with an extra 2 Megabytes of cache."

Comments

Possible Advertising Campaign?

[The_Rippa]

Saturday. Saturday! SATURDAY!

At Intel Headquarters!

Witness the unveiling of the next...

Biggest!

Meanest!

Fastest processor you can imagine.

Pen-Pent-Pentium EXXXXXTREME

It's 3.2 gigahertz of binary badness.

Come witness as it peforms calculations at mind-boggling speeds!

Special Guest The Blue Man Group

Tickets start at $20 for adults, discounts for children and seniors

If you miss this, you'd better be dead... or in jail...

And if you're in jail, break out!

Re:Possible Advertising Campaign?

[L-Train8]

Extreme? Whenever I hear that word in an advertising campaign, I think of Homer Simpson as Poochy the Pooch: "Hey kids, remember to recycle... to the extreme!"

Re:Possible Advertising Campaign?

[m00by]

dude, you so TOTALLY forgot the most important part: you pay for the whole seat, but you'll only need the EDGE!!! =D

Re:Possible Advertising Campaign?

[nrmrvrk]

Special guess celebrity: Randy Macho Man Savage:

Kid: "Pentium chips aren't an extreme sport, Macho Man..."

MM: "PENTIUM CHIPS NOT EXTREEEEEMMMMEEE!?!?! OOHHHH YEEAAAAH!!!!"

Re:Possible Advertising Campaign?

[MrLint]

Pentium Extreme! its just as good as having a 64 bit CPU!

Re:Possible Advertising Campaign?

[Anonymous Coward]

Pentium EXXXXXTREME*

*extras Xs may result from occasional floating-point errors.

Re:Possible Advertising Campaign?

[GMFTatsujin]

Change "pay for" to "license" and you've got a deal!

Re:Possible Advertising Campaign?

[cheezedawg]

1) Get rid of 20-stage pipeline, it's too long for anything serious.

No its not. In fact, according to this research, the P4 pipeline is not deep enough. That paper concludes that P4 performance could be improved by up to 90% by increasing the pipeline depth to around 50 stages and increasing the cache size.

Do you actually think that Intel didn't know the consequences of increasing the pipeline depth? The Intel engineers didn't just guess on the P4 architecture- it was a very deliberate design decision. Judging by the P4's performance gains, it was a pretty good decision, too.

maddox influence?

[edrugtrader]

they must be reading maddox's site

I have a 3.2Ghz PC that I bought for home...

[Osrin]

... I struggle to tax it with anything I do, including some of the more intensive games.

This "extreme" version of the chip has to be aimed at a very niche market, at least for the next couple of years until more processor intensive software catches up.

Re:I have a 3.2Ghz PC that I bought for home...

[Fulcrum of Evil]

This "extreme" version of the chip has to be aimed at a very niche market

Yes, it's the 'mine's bigger' market, though I wouldn't call it niche, exactly.

Re:I have a 3.2Ghz PC that I bought for home...

[be-fan]

Try compiling KDE. My 2GHz P4 struggles to do it in under a working day. Heck, it takes nearly a minute just to recompile a KDE theme after making a change to it!

Re:I have a 3.2Ghz PC that I bought for home...

[Glonoinha]

All a matter of time.

I remember reading once in a Usenet thread - some guy was trolling and asked 'will my P90, overclocked to 100MHz, be enough to handle the flight combat simulators you guys are discussing?'

The first time I read it it was hilarious because he was either bragging or dreaming, the P90 chip was out in limited supply at the time and was easily 50% faster than the common P60 machine used by the sim-gamers, not to mention the overclocking it. Of course it was going to be fast enough.

The second time I saw it (a few years later) it was hilarious because the bare minimum system for any sim/game was a PII/300 with a 3D graphics card and his P90 was so pitifully underpowered it didn't have a chance.

So we get to enjoy the 'is this CPU enough' question twice, generally, for any given CPU. Just a matter of timing.

Obligatory Waynes World

[Znonymous Coward]

Extreme close up! Whhoooooooooooo... Whhoooooooooooo.

Level Three Cache

[Master Bait]

Ho hum. I suppose if it was level two cache, Intel would have said so very loudly, so they just call it 'cache'.

Multiprocessor?

[tinrobot]

The rumors are that this chips are the same or very similar to the $4000 Xeon MPs with 2MB cache. I wonder if these will work on the workstation class MP motherboards. Would be sweeeeet.

Re:Multiprocessor?

[loopWork]

Different pinout, so no.

Ohpleaseohpleaseohpleaseohpleas

[JoeLinux]

I wanna see major competition between Intel and AMD. That way I can get my 875P motherboard "tossed in free with the purchase of any Intel Pentium 4 Extreme(tm) Processor." It's about time I upgraded from a Celeron 433 anyway. Ghost Recon plays more like Ghost Recon: The Slideshow.

Joe

Tom's Hardware reviewed a similar Xeon...

[tugrul]

... with 1MB of L3. The results weren't that exciting.

Re:Tom's Hardware reviewed a similar Xeon...

[ciroknight]

But at the same time, the Level Three Cache is MUCH "further away" from the core in the sense that it takes much longer for data to travel accross the lines of the processor to get to it. Level Two isn't much closer, but that little edge does make a huge difference in this case. Game developers now have room to seriously push their applications because the processor will be able to cache more (data||instructions). It should vastly improve scores on very memory intensive apps.

On the other hand, I would much rather see them quadruple the size of the Level One Cache. This would improve performance on these processors, but at the same time, without the extra registers that a 64-bit chip would have, these improvements are limited by their usefulness, not to mention they would take up loads more valuable core real estate. I can't wait to see Intel move to a 64-bit chip with a 2 meg level 2 and maybe a 128k level one... we'd start to see chips FLY....

Re:Tom's Hardware reviewed a similar Xeon...

[akuma(x86)]

Computer architecture 101.

Average memory access latency per memory access =
(L1_hit_rate * L1_hit_cycle_time) +
(L1_miss_L2_hit_rate * L2_hit_cycle_time) +
(L2_miss_L3_hit_rate * L3_hit_cycle_time) +
(L3_miss_rate * DRAM_latency)

80-95% of your accesses will hit the 8k L1 in typical applications. This is the vast majority of the accesses. The latency of this cache is TINY on a P4. Do the math for a 3.2GHz 3 cycle cache.

Given a curve of cache-size vs. latency and hit rates for all the cache sizes, the optimal hierarchy is a simple optimization problem. I can assure you that this equation has been solved and the optimal heirarchy has been chosen (given the other constraints of obviously die-size and power).

Quadrupling the L1 will double the latency and kill your average access time, making your chip almost certainly slower.

Bigger caches mean longer latencies. It's limited by the basic laws of physics. There's only so much distance you can traverse in a ceratin amount of time and larger caches have longer distances (meaning higher RC delays).

The reason we want larger outer level caches is because the DRAM_latency is enourmous and has an impact on average access time. Hardware prefetching can also help to alleviate this problem - This solution is available on both Athlon and P4 chips and will only get better in the future because it is absolutely critical to hide this DRAM latency.

Ok, now to address the notion that more registers will improve performance...
You won't get as much performance out of more registers as you might think. First of all, when the compiler runs out of registers it spills the excess to the stack -- pushing it out with a store (spill) and reading it back in with a load (fill).

In modern processors (just about every chip out on the market), there is the concept of store buffers. Each store writes it's data to a store buffer. Subsequent loads that require data from stores, get their data by forwarding out of the store buffer. So -- the spilled store writes the buffer and the fill load reads the buffer -- all of this happening much faster than a memory access because it's just reading out a local on-chip buffer, so the load looks more like a fast register read. This architectural trick emulates the effect of having more registers, subject to the size of your store buffer. There are even more advanced architectural tricks you can play to completely eliminate the spill-fill pair from the critical path (look up memory-renaming in the literature).

If you're worried about chip-real estate, you should be very concerned that a 64-bit application's pointers will take up twice as much space effectively making your caches and memory bandwidth appear smaller.

text incase of /.ing

[Anonymous Coward]

Intel Developer Forum Cache for questions

By Nebojsa Novakovic: Tuesday 16 September 2003, 18:14
WHEN, AT today's IDF opening, Louis Burns demonstrated a high-definition video stream running on a "mystery" desktop processor, everyone must hve thought it was the upcoming Prescott part. Wrong! It was the (also upcoming), previously unheard of, even at The Inq, Intel(R) Pentium(R) 4 processor Extreme Edition 3.20 GHz , with an extra 2 Megabytes of pron. In Intel's own words, "this new processor will be targeted at high-end gamers and computing power users."

As a matter of fact, 2MB cache will help a lot those users whose apps (including games and such) have a lot of big cache-friendly *wink* pieces of code and data, but probably not the data-streaming intensive stuff. I do expect to see speedups anywhere from 2% to 20% depending on the application, maybe some more if using multithreading/multitasking (large cache can keep in code / date pieces from more threads).

However, this doesn't seem to be a new CPU in reality - after all, Intel is doing very well with its XeonMP 2.8 GHz 2 MB cache CPU, and how much effort does it really take to repackage it for the 3.2 GHz / 800 FSB desktop with less stringent thermal and reliability requirements than the big iron, anyway?

Intel would gain a lot with this move. If, touch wood, there are problems with Prescott, a large-cache Pentium4 part will provide some buffer against large-cache Athlon64 (i.e. rebadged Opteron) parts. At the same time, enormous extra benefits from the economies of scale would further reduce the identical die XeonMP manufacturing cost, helping Intel compete better on the quad-CPU server front as well. Interesting move? I think so. Let's see how the beast performs in real!

More impressed with AMD.

[Thinkit3]

What I'm really not impressed with is Intel saying desktop users don't need sixty-four bit. Well, we don't need gobs of cache. We need sixty-four bits.

Re:More impressed with AMD.

[C. Mattix]

The difference is that all the existing apps would need to be recompiled to fully use the 64bit. Even lowly DOS can use performance improvements with a larger cache. And with Hyperthreading the number of clocks per instruction is very small, this lends itself to using a larger cache more often.

See also:

Ars Technia on Caching

Extreme price...

[Anonymous Coward]

$740 in 1,000 unit quantities. I think I'll pass.

Cinema-like video

[Rosco P. Coltrane]

Louis Burns of Intel displayed a "high-definition video stream running on a 'mystery' desktop processor.

Gosh, one of these days I'll have to take a sneak peak at the hardware they run in that mystery little room in my local theater. The monitor is so big, the soundcard is great, and I can see it all for a buck!

I will not buy anything that has X, eXtreme,

[teamhasnoi]

X-treme, XXXtreme, X-tream, XT-ream, AXEtreme, Xtreme, or is generally Xed-up in anyway.

Please send a message to the X-tra stupid Advertising XX-cutives that X in the name is X-tremely dated and not an X-ellent idea.

The new marketing buzzword is 'Shit-Hot', as in "The new Intel Shit-Hot P4!"

Thanks.

Paper Launch?

[Dumass]

Not to be labeled a fanboy (although not necessarily denying that status)... but this sounds like a paper launch just to take some press away from AMD.

"He [Burns] said the chip will be available to buy in the 30-60-day timeframe." from this article.

Prescott is going to be late and has been getting bad press for not being backward compatible with current motherboards. Why not make some noise with a product that wont be around for another month?

database searches

[chipace]

This chip would be great for database searches... it has more cache than uni-processor xeons and it probably will be cheaper. Thanks gamers! I guess the wait for Prescott is real... seeing that Intel had this chip on tap.

CNET article with more details

[HeroicAutobot]

CNET has an article with more details (or speculation more likely).

Some interesting quotes:

"The performance boost is awesome," Burns said Tuesday during a speech at the Intel Developer Forum here.

"It is a Xeon with a different pin-out, or least that's what it looks like to me," said Nathan Brookwood, an analyst at Insight 64.

Intel did not disclose the price of the Pentium 4 Extreme Edition. It likely will be as expensive as its counterpart, the 2.8GHz Xeon with 2MB cache. That chip sells for $3,692 in quantities of 1,000.

"It absolutely will be kind of pricey," Brookwood said.

Wow!

[ENOENT]

3.2 GHz! That's 6.7% faster than 3.0 GHz! You feel the need to send money to Intel! Fnord! Imagine how fast the Internet will be if you have one of these on your desktop! You will need a neon-colored bunny suit just to look at your computer! You will be assimilated by the Blue Man Group!

Re:64bit vs 32bit

[2nd Post!]

Nope, the only 'desktop' 64 bit processors come from IBM and AMD;
AMD Opteron
AMD Athlon64
IBM PPC970

Intel's 64 bit solutions is the Itanium! Anything with the Pentium moniker is 32 bit. The Itanium is the one which suffers 32 bit emulation lag.

So if you want 64 bit, you're stuck with, realistically, a Mac or some brand of Athlon CPU.

Re:64bit vs 32bit

[Naito]

You're thinking of the Itanium. It used to run 32bit X86 under a hardware emulator, but that was about as fast as the Pentium MMX. Intel has since switched to using a software emulator, something like Transmeta does with the Cruesoe, and it's actually faster than the hardware emulator, about the same speed as a Pentium III now.

The Xeon is a Pentium4 in different packaging and with SMP enabled. Actually, SMP is probably enabled with the Pentium4 too, but since there are no such motherboards and you can't plug them into Xeon DP mobos, nobody can test that. Xeons already come in versions that have up to 8MB of L3 cache, the new Pentium 4 is probably just a rebadged Xeon certified to run on an 800Mhz bus.

Re:Interesting, but...

[militantbob]

I need that much juice. My Windows machine typically handles mIRC, Yahoo Messenger, 3D Studio Max, 3 or 4 IE instances, etc.

Of course, most of those programs are essentially idle at any given moment. But when I'm trying to render a massive 3dmax scene while switching over IRC to ramble libertarianesquely about the failings and dangers of big government, while at the same time opening/reading 3 or 4 web documents... my machine bogs down on me. Now, this machine is a P4-2.9GHz with a gig of RAM on SCSI disks... perhaps the extended speed and cache on the new CPU would make a difference.

At the same time, I could use one of these on my colo box, which is hosting 17 domains with about 3,000 pageloads per hour. Then again, I could always get something other than x86, if I weren't a cheap and ignorant bastard.

Processor-Intensive SW: Engineering Applications

[reporter]

This "extreme" version of the chip has to be aimed at a very niche market, at least for the next couple of years until more processor intensive software catches up.

The processor-intensive software is already here. It is called HSpice, Verilog, fluid-dynamics simulation, etc. The Pentium 4 has done nicely in the engineering workstation market, and the "Extreme Edition" should do even better.

Please check the SPEC web site for a performance evaluation of the Pentium 4's floating-point (FP) performance. In particular, it outperforms the UltraSPARC III even though the latter has a 2-to-1 advantage in the width of its databus -- 64 bits versus 32 bits.

What changed the x86 chips from also-ran losers in FP performance to the kings of the hill? SSE.

The SSE extension to the x86 instruction set architecture (ISA) opened up a whole new world of applications for the Pentium III and successors. Older Pentiums were saddled with a FP stack that hurt their performance. The SSE extension established a directly addressable bank of 8 128-bit registers or 32 32-bit registers for FP operations. As a result, the Pentium 4 outperforms the UltraSPARC III on video applications.

At 3.2 GHz, the "Extreme Edition" of the Pentium 4 should help the Pentium 4 to capture even more of the engineering workstation market. Nowadays, the first-choice workstation among engineers in Silicon Valley and Boston's Route 128 is Linux running on a fast Pentium/Athlon, not Solaris lumbering on a slow UltraSPARC III.

... from the desk of the reporter

Re:I'm so sick of "extreme" this and "Xtreme" that

[mr.henry]

IANAAM (I am not an advertising major..), but apparently the "X" is supposed to make us think of sex, and therefore make whatever product a company is pitching more appealing. "SX" is even more blatant. In product model lineups, it's everywhere.

With that in mind, and seeing past the fnords, LX or LS (think Lexus LS 400, or whatever the latest is), is the most appealing of all: lesbian sex.

I hope I don't come across as crazy or perverted, but advertising will do ANYTHING to sell crap to people.

Re:Interesting, but...

[Graspee_Leemoor]

" I need that much juice. My Windows machine typically handles mIRC, Yahoo Messenger, 3D Studio Max, 3 or 4 IE instances, etc."

3 or (gasp!) 4!!!! instances of IE?!?!?!?

Dude, you are XTREEEEEEEEEEME!

graspee

Wait for the next version after this

[PanchoVilla]

In a couple of months Intel will be releasing the new Pentium IV TypeR !!!! The heatsink will even have one of those ugly shopping cart handle type spoilers and NEON too...........

EXTREME? How about stable?

[narftrek]

What is it with Extreme as the buzzword these days? When you hear extreme you think of people jumping off cliffs or launching motorcycles off tall things. Things that some may consider DANGEROUS or STUPID. It can also mean "on the edge" as in pushing the limits or ground breaking technology. I don't know about the rest of you but I don't want a computer that pushes the edge, is dangerous, or stupid. I want a nice stable (as in doesn't crash 10 times a day) computer that I can watch my pr0n on. Is that too much to ask? Extreme is worn out in my book-pick a new buzzword.

Re:Interesting, but...

[commodoresloat]

...of all the people who are going to run out and buy it, who REALLY needs that much juice?

Some of these people even believe they need more than 640K of RAM.

Part 2 of Article up now

[dubiousdave]

The second part of their article is here.

Re:1GHz is plenty!

[Pharmboy]

What supprises me is that they didn't finally go to 1GHz FSB. , I know, that would mean you need DDR500(PC4000).

Actually, no you don't. Apple sells their dual 2ghz box, that has a 1ghz fsb (dual pipe), and 400mhz ram. goto apple.com/powermac for info. It obviously doesn't talk to the ram that fast, but 1g pipe to the chipset doesn't suck either. Oh yea, and up to 8gb of ram so far. its a bit different in other aspects as well.

I am just waiting to score one of the dual 2.0 boxes used (cant afford $3500) but that will take a while. They also bench out better cycle to cycle that intel (similar to amd or better) Its actually the IBM 970 cpus (reduced power 4 cpu) that IBM is said to be releasing soon in entry level servers, with 4 cpus, for $3500, for Linux.

Awwww

[sys$manager]

I was hoping for Pentuim 4 Turbo Alpha.

HAAAAADOUKEN

Re:Processor-Intensive SW: Engineering Application

[mczak]

SSE is single-precision (32bit) floats only, so pretty useless for scientific calculations (usually require doubles).
However, I believe the intel compiler uses SSE2 (which can handle 64bit floats) exclusively for float code, since the P4 legacy fpu is just slow. Of course there are compiler switches for the compiler so the code also runs on good old Athlon, Athlon XP, PIII (which lack SSE2, the Athlon also lacks SSE) - and those aren't exactly slow doing float calculations neither.

Re:Old IBM XT?

[shadowcabbit]

On my friend's computer it seemed to stand for "Xcruciating Torment". He hated that thing.

Re:Databus of Pentium 4 is 32 bits, not 64 bits.

[Hoser McMoose]

Err, no. The internal data bus of the P4 is 256-bits wide, at least if you're talking about it's L2 cache bus. L1 cache doesn't really have a "bus", especially not the P4's trace cache (it's replacement for an L1 i-cache), but if my memory serves me correctly, the L1 d-cache of the P4 can read or write a pair of 64-byte values in 2 clock cycles. I guess that makes it's "bus" 128 bytes (not bits) wide. I don't know the bus width of this new L3 cache on this P4 "Extreme", aka a XeonMP, but I would guess it's 64-bits wide.

I haven't got a clue as to the internal data bus of the USIII, but I would guess that it's either 128-bit or 256-bit wide. Side note: the Power4 uses a MASSIVE 1024-bit wide internal bus, one of the reasons for it's impressive performance.

The only situation where the USIII has 64-bits and the P4 has 32-bits is if you are talking about integer registers or memory pointer width, neither of which are going to play a role in Spec CFP scores.

Apples compared with Oranges

[zealotasd]

You are making a incorrect comparison in computing technologies. UltraSPARC III is for higher precision, but it is way out of its competitive market by two years ago. Pentium 4 is built for highest performance at the expense of power consumption. In a more objective comparison with the UltraSPARC III, we would compare performance/initial cost/power consumption (and forecasted power consumption cost to price barrier). UltraSPARC III is built for good performance on its implemented hardware, thus it utilizes its bus and memory architecture to optimum. The Pentium 4 does not perform with the mathematical precision and architecture efficiency as does a UltraSPARC III. The Pentium 4's memory architecture isn't even being used to full efficiency because of the nature of x86 being a pro-legacy architecture.

The biggest black sheep of the industry is the legendary Alpha architecture. It's a 100% 64bit precision platform with highest efficiency per watt and it was purposely bought by Intel to be silenced and migrate all its users to the Itanium architecture. Not even an Itanium2 can perform as well as an Alpha of two years ago (21264/ev6). The only downfall of Alpha is the legitimate and objective comparison of performance/initial cost as being the notion it is highly non-competitive with other offers. The reason it is not as competitive with other architectures is not based on fabrication costs: it is based on it being the better architecure that was purchased before its parents' bankruptcy (DEC...Compaq?), and to try to recover the R&D costs of the overly-invested lesser architecture known as Itanium.

People who still use Alpha already know that if it is buried then the only logical successor would be a Power4 hands down. All the while, HP's PA-RISC is being incorporated into the same Itanium architecture to migrate its dwindling userbase to Itanium. So much is going wrong in the idustry it makes me sick to the stomach.

Re:Speed / Cache is irrelevant *soon*

[darkwiz]

In the next year we'll see the first solid state hard drives (Some that will run fast or faster than the processor) and faster RAM that would run the same speed as the processor.

Cache on a processor would be redundant if you can access the RAM at the same speeds. AMD is aware of this and are working to make compatible products.

No.... we won't. What you are describing is insane. Come on: 3.2GHz x 32 bits? Access/transfer times over a full scale bus with a latency in picoseconds? Um... no.

There is a reason no one has done that yet - made system RAM the same speed as the CPU - and it ain't economics: it is physics. Nature does not take bribes.

Look, it isn't that it is too expensive to make fast RAM. And it isn't the distance - it is the capacitance. The problem with fast RAM is getting that signal off chip to the CPU. And the wires that connect the RAM and CPU are orders of magnitude higher capacitance than the wires on chip. That is a fundamental problem which you won't overcome without a fundamental change in how you move the data around.

Solid state drive/memory that runs at compatible speeds as the processor will probably reduce the need for what we call ram these days and operating systems could just use the drive for it's RAM.

Um.. no. Never will that be the case except in situations where using an archaicly small amount of processing power is adequate. Storage technology, as it is formulated now, cannot approach the speed of access, communication, and storage that even a low grade CPU would use for cache.

Maybe - MAYBE when we are using diamond wafers, high-temperature-superconductor-nanotube-quantum-d ot wires, and other buzzwords.