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The Arrival of Very Small Memory
Roland Piquepaille writes "After the ages of DRAM and SRAM memories, is this time for nanotech memories? ExtremeTech says that "molecular memories" as well as memories based on carbon nanotubes are emerging. With these nanotech memories, several startup companies are envisioning future chips mixing logic, memory and reconfigurable computing elements. One of these promising startups is ZettaCore, which has built a prototype of a molecular memory designed to replace both SRAM and DRAM kinds of memories. These molecules, which are about 1 nanometer in size, are also self-assembling, meaning that they can be manufactured with existing equipment used in the semiconductor industry. This overview contains more details about the technology and includes a diagram of these molecules in a memory array."
Sorry, what were you talking about?
64 bit computers can have up to 18Tb of RAM, but with motherboard physical limitationss it iss not possible. Even with 4Gb dimms (which are expensive) your lucky to get more than 16Gb out of standard motherboards. With this technology, We will be able to break this barrier, and do wonderful things in small spaces.. I for one, welcome my 18Tb Dimm!
I have a fetish for traffic cones
With these nanotech memories, several startup companies are envisioning future chips mixing logic, memory and reconfigurable computing elements
Do they mention if the CPU and motherboard manufacturing companies care? Technology succeeds because of marketing, not because it's innovative or high quality-witness Betamax,
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Xilinx have silicon with embedded PowerPC processors, BlockRam (chunks of pre-generated SRAM) and huge swathes of FPGA cells and interconnect. The chips have other abilities too - built-in 18-bit multipliers and communications channges (10 Gbps/channel, 20 channels!). All very cool stuff. Very expensive too :-(
:-)
I'm sort of surprised there aren't more FPGA-hackers than there appears to be. It's not hard to learn verilog (very similar to C), and despite what most FPGA designers will tell you, as long as you keep your mind focused on 'everything happens in parallel', a decent programmer can produce good FPGA code too. The start kits (300,000 gates, about enough for a hardware JPEG core and maybe a network MAC) are cheap (100 or so), and designing a processor is a pretty simple operation, and immensely gratifying
Just my thoughts,
Simon
Physicists get Hadrons!
Not to state the obvious, but it will take low manufacturing costs, industry willingness, consumer demand, and a whole lot of marketing before this or any other revolutionary changes become de facto standards.
Better, smaller, faster, is no match for cheaper, more accessible, and well-marketed.
I'm a friend of a friend of the working class.
Does this mean I'm gonna start getting spam about how HU6E my memory is? I'm starting to get memory envy.
"I wish to God these calculations would have been made by steam." -Charles Babbage
This could not only increase RAM but mean we have computing devices with just one big memory pool...no Flash, no Disk, no CD, no DVD.........
Can I order mine now please?
And if you thought that was boring you obviously havn't read my Journal ;-)
Hm, doesn't sound as good, does it?
Good old progress making something small and making it smaller then integrated with other parts. This can have impact in a ton of areas including smaller and lighter laptops, PDA, and PCs, perhaps a future where you can mix Xerox's Electronic Paper with this to offer interactive News Papers. As well as a lot of cool stuff. But of corse the will be people who will use it for evil Like a chip that is implanted in Tin Foil that can see where you are. And how you are using tin foil. Or Devices attached to clothing that can all you to be tracked and record everything you see and say. or a Beowulf cluster of these the size of a PC. Oh the horror! Just remember when they start using these chips for evil please remember that you recommend them first!
Some times there is truth in sarcasm, other times there isn't hmmm.
If something is so important that you feel the need to post it on the internet... It probably isn't that important.
No one will ever need less than 640mm of memory
Very cool but memory chips aren't really gigantic. I would be more interested in speed or parallel memory access.
I shall go and tell the indestructible man that someone plans to murder him.
I mean, if the chips become so much smaller, it's easy to see the capacity of i.e. Ram chips will reach levels unimaginable now.
But how are these bits gonna be addressed ? you need *lots* of pins, and how to connect those pins to the logical layer ?
I guess motherboards, processors and such need to be radically redesigned to be able to use this new technology.
How long would it take before mainstream mobo's use other (like i.e. photons instead of electrons) than conventional techniques ?
just curious
r.
Except for embedded devices like cell phones and pdas, this won't change much. The memory density may go up, and since the chips are thinner the heat problem may improve, but the size of system chips won't change.
The reason is simple, human fingers and hands aren't going to shrink. SDRAM cards are about as small as most people can handle comfortably. SDRAM chips for CPUs work very well not at holding chips but at being easy to install and make positive contact with a large number of contacts on a relatively small edge. The design factors for these things are many, the chips they carry are only a single one of them.
I suppose someday it'll be theoretically possible to put that monster gamer machine in a thinline dress watch, but as they found with the "databank" watches the limitations are the input/output devices average people can comfortably work with, not electronic capabilities.
It doesn't matter what you wrap your emotions around, Reality is a brick wall specifically designed to scramble eggs
You are assuming a bit addressable memory?
Actually, I know that you probably meant MB, but this is a significant point. If your 64bit computer had only word addressable memory (i.e., 64 bit chunks) then the same addressing could address 8 times as many bits (to the word level) as a byte addressable memory could address (to the byte level), and larger chunking is also possible. There could, e.g., be an alternate set of instructions that only addressed information to, e.g., to KB level, or to be more practical, to the 8MB (or 16MB) level (used for memory mapping LARGE disks).
The number of bits does, indeed, tell you how many separate addresses you have, but it doesn't tell you the interpretation of those addresses. There have been bit addressable machines. The CDC 6000/7000 series had 60 bit address chunking (for the main processors...I believe the peripheral processors had character [6-bit] addressability). And there have been many other choices. What the best choice is depends on a mix of what you intend to be doing, and what your hardware is.
So lets look forwards a few years. Unicode is likely to make 16-bit characters the most common chunking size, so byte addressibility will probably go by the wayside and be replaced by 16-bit chunking. This will probably quadruple the number of applications that can use "character-sized integers" as their integer of preference. So double-byte addressing will become the dominant form, and byte instructions will become deprecated, much as bit-level instructions have been deprecated. (They're still kept around for special purposes, but they're hard to reach from anything higher than assembler.)
Given that, byte size addressing will become unused. Probably IO between registers and RAM won't even deal with anything as small as a double-byte. 64 bit chunks are probably the minimum size that will be handled. (Makes the bus design simpler if you just drop any excess you aren't interested in.) And quite likely even that won't be the minimum size...depending on CPU register memory.
Remember, we're still in the early days of 64-bit CPU design. I may doubt that we'll ever go to 128-bit CPUs, but just consider the number of op-codes that even a 64 bit register allows. What I expect instead is that CPU chips will develop large on-chip RAM caches, supplemented by even larger L1-caches, etc. And that an on-chip SMP configuration will develop...how many processors? That will be determined by experimentation and evolution. But the limitation of the pin-outs at the edge of the chip will give a strong reason to find ways to handle compressed data forms. (Compressed here is more like the kind of compression that vector graphics gives over pixel graphics than like bzip2.) Say chips optimize out at 8 cpus per chip. The typical instruction for data from outside the chip would be "move a block of data from the L1 cache to register set n" or "Fill the L1 cache from RAM location x". Which means that memory addressibilty wouldn't be even at the 64-bit level, but at some higher level. Probably, say, 1/8th of an L1 cache. And the L1 cache would be addressible to a smaller level, say 4 64-bit registers. (N.B.: These are wild guesses, merely intended to indicate the kind of addressing that I see as plausible).
So how much memory could a 64-bit cpu address? O' at a wild guess, 2^64 * 64KB. Or more. Or less. (Sorry, it's a quite wild guess.) I don't know what prefix to use for that kind of RAM size, but TB isn't in it.
Of course, this isn't the first generation of 64-bit chips. But we're talking about a pretty speculative form of RAM here...so the CPU that uses it will probably be a generation or two more advanced than the current ones.
I think we've pushed this "anyone can grow up to be president" thing too far.