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Researchers Design Microchip Ten Times More Efficient
WirePosted writes to mention that a new highly efficient microchip has been announced by researchers from MIT and Texas Instruments. The new chip touts up to 10 times more energy efficiency than current generation chips. "One key to the new chip design, Chandrakasan says, was to build a high-efficiency DC-to-DC converter--which reduces the voltage to the lower level--right on the same chip, reducing the number of separate components. The redesigned memory and logic, along with the DC-to-DC converter, are all integrated to realize a complete system-on-a-chip solution."
The article doesn't say whether these chips are cheaper to make than the current technology. That will be the deciding factor regarding how soon these make their way into our portable devices.
"Be light, stinging, insolent and melancholy"
I thought this sounded familiar.
Prov 9:8 Do not rebuke mockers or they will hate you; rebuke the wise and they will love you.
The first thing that came to mind when I saw this article was the Transmeta Crusoe processor. Which unfortunately never achieved much of any significant market penetration. Indeed, it seems that you really have to have something more than just an incredibly efficient chip in order to compete against the Intel - AMD behemoth.
Personally, I would love to see a chip that requires very low power make it into the mainstream market. I think it would great to have something like that for the miniITX form factor or something of that nature that hobbyists could tinker with and find fun applications for. The Transmeta, unfortunately, never realized that as far as I ever saw.
Damn_registrars has no butt-hole. Damn_registrars has no use for a butt-hole.
Just like all these articles on breakthroughs in energy efficient technology, there's only one thing I'm interested in.
from TFA:
So far the new chip is at the proof of concept stage. Commercial applications could become available "in five years, maybe even sooner, in a number of exciting areas," Chandrakasan says.
-- Boycott Shell
It seems like all of American know-how goes into designing things like this, then companies move the jobs overseas. Now, if they moved it to countries that are friendly to here, I would not care. But where do they send it to? China. Not even Taiwan anymore. Plain ole china. And yet, China is on a real spending jag to build their military up. The amazing part is that many of the CEOs at these companies are the same ones gripping about American's losing their edge, while they send the high-end jobs elsewhere.
The reason is that they needed to build up an industry to accept them. There were already other chips fabs that had a name. So what did transmeta do? Nothing. They should have spent a few bucks and looked for new ideas that used their chip. They only needed a few interesting ideas to make it. How much money? What a million / idea? Even had it cost them 3 million, then it would have been NOTHING in the long (or even short) run.
I prefer the "u" in honour as it seems to be missing these days.
I am very interested to see how they managed to reliably demonstrate on/off states of individual transistors at the 0.3V level given that standard logic families use between 1-5V for individual transistors. Of course the article wouldn't have these details considering the article was entitled "Ten times more energy-efficient microchip recharges itself". I suppose whoever wrote the article drew that conclusion from the CONJECTURE posed in MIT's press release.
Just try and tell that one to Bill Gates.
Since power usage is (roughly!) proportional to voltage squared, getting the chip to run at less than one third the usual voltage will indeed give an order of magnitude reduction in power usage.
From the report: One of the biggest problems the team had to overcome was the variability that occurs in typical chip manufacturing. At lower voltage levels, variations and imperfections in the silicon chip become more problematic. "Designing the chip to minimize its vulnerability to such variations is a big part of our strategy," Chandrakasan says. I.e. current state of the art transistors does not work reliably at such voltage levels, I'm guessing that they have to give up significant parts of the theoretical power reduction in order to make it work at all.
Terje
"almost all programming can be viewed as an exercise in caching"
Would a body heat powered computer in your head have enough processing power to serve the same function as a "Cyberbrain"?
If they are in the head, the head is pretty warm, in fact it is one of the warmest areas of the body.
I think that powering protectics, at least the control systems via body heat would simplfy the power requirements for prosthetics.
Tsukasa: All I really want, is to be left alone...
Without RTF I would guess that you could run every voltage as needed on a CPU instead of a single voltage. The MMX processor would need a higher voltage than the pipeline units (just making an example for illustration)
Perhaps memory chips may hold data at a much lower voltage and only need a boost during a write operation.
love is just extroverted narcissism
"The power consumption in the new chip is so low that devices using them may even be able to be recharged by human body heat."
That's what we be now - human batteries. Just wait until AI gets ahold of this new source of energy...
If memory serves power dissipation has a formula on the order of I2R, I being current in amps and R being resistance in ohms. So, if you had a chip that ran on 1,000 volts at 30ma instead of the usual 1 volt and ~30 amps wouldn't it be just as efficient as a 0.3volt chip running at (and I'm guessing here because tfa doesn't mention current) 1 amp or maybe even less?
Their work is definitely interesting, but I think some important questions remain unanswered, the main among them is the tradeoff between correctness of operation vs. performance because of variability. There is a paper in ISLPD 2006 which shows that for a 65nm circuit to operate at 0.3 V, the clock period must be scaled up by a factor of at least 230% to compensate for variability related issues. Additionally, there is a huge problem as far as tool support goes. This is not just mix-and-match style design. In order for this to have widespread use, it needs to work well in the EDA tool workflow. This means that libraries (and to some extent transistors) need to be characterized well at the subthreshold operating voltages. This causes a catch-22 situation. In order to design something using this subthreshold voltage technology, you need good transistor models, but the fabs have no interest in providing these models unless there is large customer demand. It is pretty expensive to get good models. The way this works is most fabs actually create transistors/gates at the given feature size, characterize them, including parameters for variation/process variability and give these to their customers, who design their chips based on these simulations. The reason these are so important is that for synchronous circuits, you have to base the design of the clock scheme on the worst/average case delay, and this you can get only by doing complete (usually Monte Carlo based) simulation of the chip using the transistor models that fab gives you. If you base the parameters solely on simulation based tools, you ignore all sorts of effects in the real world, causing a massive drop in yield(i.e. working chips made by fab).
Legally obligatory sig : My opinions are my own... etc etc
Slightly O.T., but can I petition for a reusable "seeyouinfiveyears" tag that gets tacked onto any article where the technology will be out of the lab and in the factory in 'five years'?
Because 5 years from now, I'd really love to quickly and easily see just how accurate or inaccurate that industry standard five-year prediction really is.
Anyway, I didn't find an explanation in the article. So what is a theoretical 100% efficiency with respect to logic circuits? Every electron turned into a bit of information? Every pair of electrons? It seems impractical to define efficiency in this case. For instance, I don't think coulombs per megaflop could be construed as efficiency, per se. If there was a standard out there, maybe a theoretical minimum number of electrons to perform a logical operation on a standard circuit, we could compare other circuits with that...
On the other hand, I could just cut journalists some slack when they use technical terms in a mass-media context. Now where did I leave my soapbox?
Language students: Don't try to learn English here. This ain't it.
If they have a substantially better DC-DC conversion technology, that's worth a lot of money to a lot of people already.
-jcr
The only title of honor that a tyrant can grant is "Enemy of the State."
This is good cause my power bill will be 10x todays by the time this new chip goes live.
Horns are really just a broken halo.
This method, incidentally, has been five years away for several years. I think that other methods of reducing power output on chips (Gallium Arsonide, asychronous solid-state circuits, reduced resistivity in the interconnects) and on computers overall (better caching on drives, smarter offloading, etc) will prove to be the way to go.
It's a small world and it smells funny; I'd buy another if it wasn't for the money; Take back what I paid (SoM)
Simple: You assume that every bit of power going in is wasted. Therefore, there is no such thing as absolute "conversion efficiency", but using 10 times less power does make you 10 times as efficient, since you get the same bits coming out (assuming the same program and input) for 1/10 the watts going in.
Less is more.
So if the existing design is 1x efficient, does that mean the new chips are -9x the power of the current chip, meaning that you actually get energy from using them? They should put those into the priuses.
A pacemaker that never requires a battery change sounds good to me.
Haven't they got those things running off ATP yet?
When our name is on the back of your car, we're behind you all the way!
Note: I posted this earlier as a reply, but no one seems to have noticed it. Hence this repost. I'm a long-time-reader-very-rare-poster, so sorry if this is not the right way to go about it.
Although the study quoted by the OP got a lot of media attention because of MIT involvement, what is more interesting is this actual product that has been released last month: "One AAA battery! The boss must be kidding..."
This company (Silicon Labs) has managed to put a DC-DC converter in a microcontroller and have managed to do this on an actual product that you can buy now (not just a research project!). They claim to be able to run for years (even >15 years) on typical low-power applications such as data loggers that wake up for a short while take a measurement and go to sleep. This is also the first microchip that can run on one battery... if you think that adding an external DC-DC converter would do the same trick, you have to remember that the external DC-DC converter needs to be ON even during sleep mode so the micro can wake up again, which burns quite a bit of power. They claim to have eliminated this by putting the DC-DC converter on chip.
More articles on this micro: http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=206801775 http://www.electronicsweekly.com/Articles/2008/02/26/43201/silicon-labs-microcontroller-features-integrated-dc-dc-for-portable-uses.htm
Another thing to note here is that having multiple power rails tends to add a cost, and eat up rel estate on a PCB board. By embedding the DC-to-DC converter on the SOC you can possible reduce the power supply to a simple regulator that manages the battery power. TI already uses embedded DC-To-DC converters in their Firewire IC's. This is a big deal for embedded system design.
New! Device Legs: These legs will help your poor OEM installed product escape any hamfistedness it may encounter. Ava