We had to do this in my driver training. Throw the car in neutral, turn off the power, then turn it back on again with your foot over the brake in case something on the road requires your attention.
They did not do this where I learned but I have always driven a manual transmission. Putting the car into gear and releasing the clutch to restart the engine is second nature for me if already moving. I have always owned cars that I could push start solo.
In the case of the 2004-2009 Prius, the pedal for the parking brake is hooked directly to a cable that goes straight to the rear drum brakes. That means it will work fine in an emergency, but remember, these are only the rears, and they're drums (except the touring edition). It still might work in many emergency situations, but I don't know if that's enough to stop a car that thinks you're flooring it.
Even when completely rebuilt and adjusted, I have never used a drum parking brake that could stall the engine. Lock up the rear wheel or hold the car on an incline? Sure. But they will not stall the engine on a rear wheel drive car. Try using your parking brake sometime to slow down from freeway speeds. It takes quite a bit of distance.
And are you also your own ISP or does your email pass through someone else's routers? Hope you don't mind them recording packets and saving every DNS lookup and every website you visit as part of the "ordinary course of doing business".
The law makes a distinction between data in transit and data in storage. The former has more protection through wiretap laws at least up until recently than the later. Email stored on a server awaiting download via POP3 or similar is considered data in storage.
I long ago decided that opportunistic encryption was the endgame in the battle over 4th amendment protection of data in transit which is a poor outcome for both sides. If government lacks the ability to enforce or even define 4th amendment protections for private data, then all private data without exception in transit through third parties should be encrypted.
I've never seen a NAND chip that does this. Ok, OneNand does something like this but it is not really for XIP, more it's a way to allow the ARM to be reading one buffer out of SRAM while another buffer is being fetched, i.e. it was a performance hack. You can XIP a bootstrap though, but only one page's worth. Of course you could use a demand paging scheme to execute larger applications, just like a normal NAND. Still OneNand isn't smart enough to do this without additional software support.
SST has had such a device out for a couple of years now:
Or at least it wasn't last time I checked. Mind you it could be done but if it was it means the hardware would need to handle bad blocks. Still you could just have a list of bad blocks/replacement blocks in some sort of TLB like content addressable memory and make sure any attempts to access them are redirected. From the devices I've used only around 1% of the blocks are potentially bad, so the CAM wouldn't have to be that large.
The SST device includes all of the hardware on chip to handle caching, ECC, and NAND Flash management so those operations are transparent. The on-chip static RAM is divided between program memory and XiP cache under user control.
Then again not doing this sort of thing in hardware is probably what makes NAND so cheap.
Actually I'm talking about mobile phones. They typically have quite a lot of flash memory - 128MB-512MB - above the point where NAND becomes cheaper than NOR. They also have a lot of SDRAM. All of this is offchip from the ARM.
The flash microcontrollers I've seen are 64K-256K and at that level NOR is apparently cheaper.
I gather from reading various trade articles on the subject that the motivation for XiP capability using Nand Flash is the density improvement. Single devices having separate Nor and Nand arrays for code and data respectively have been available for a long time but the Nor area penalty has become significantly enough to warrant significant complexity if it can be left out.
I suspect code shadowing is a better solution in most applications.
Greenspan was appointed chairman of the Federal Reserve about 5 years after Rand was dead. I've known about their association since reading his essays published in her books.
Him running the Federal Reserve always struck me as a very Dr. Robert Stadler kind of activity although to be fair his advice to congress was regularly ignored.
Execute in Place ( XIP ) from flash is very common on low-end embedded hardware, especially with System-On-Chip machines having internal flash on chip. Most ARM7 ( not to be confused with ARMv7 ) systems out there probably do this. And that is a very very big segment of CPU market.
That used to be common back when NOR flash was. Now NAND is more common you need to copy stuff to RAM to execute it. Actually it's quite natural to demand page from NAND into RAM, i.e you have a chunk of virtual address space that is logically mapped to a chunk of RAM. When the CPU touches a page, a page fault occurs and the page is fetched from NAND.
That is not what Execute in Place means in the context of Flash memory. Most NOR Flash naturally supports Execute in Place which requires random access whereas NAND Flash does not. When applied to NAND Flash, the Flash chip itself caches accessed pages internally and presents them through a DRAM or SRAM like interface as random access memory. Before this if you wanted to execute code out of NAND Flash, as you point out, you had to manually copy it to another location first which is decidedly not Execute in Place.
I am familiar with various ARM based microcontrollers and they almost certainly use use NOR like Flash to inherently support Execute in Place because there are no delays when crossing Flash page boundaries and all accesses require the same number of wait states without any exceptions. Given the common real time nature of microcontroller applications, if there were delays when accessing new pages it would be highlighted in the specifications.
No, the only way to sensibly limit number of people is to decide how many people there should be. Then if there are too many, have peope fight each other until only desired amount is left.
There is also the Heinlein method. You could subsidize children by older couples who elected not to have children when they were young. Extending the time between generations slows down population growth just like having fewer children does. As a bonus, over time this would gradually weed out risky genes and behaviors which cause early death. * This would be rather damaging to any social security like ponzi scheme though unless you could raise productivity so it is doubly politically impractical and some nations (Italy and Japan that I know of) actually encourage the opposite.
* There was a research project involving east coast opossums which demonstrated that selecting for late reproduction could significantly extend individual lifetimes in later generations by removing early cancer causing and other early onset debilitating genes. In the specific case of the opossums, a couple of generations of selection did much better than double individual lifetimes.
Note that there is a large selection bias in the example you cite. The Romans were great engineers, but I am pretty sure they also built a lot of shitty bridges and aqueducts. It is a sort of natural selection, the ones that are still standing today happen to be the good ones.
The nature of the construction they used, unreinforced masonry in compression, is one of the few construction methods that scales up in length, area, and volume reliably. Such structures never fail in compression because the crush strength of stone is so much higher than the forces involved in any economical structure.
What needs to be done is people need to stop depending on oil, and bike to work. Bike to work by living closer to where one works.
This is difficult to do in a state like California where zoning is extensively used to divide business and housing for purposes of rent seeking. There are very few areas where travel by bicycle is remotely safe.
Like dealing with the aftermath of Libertarian Wealth Redistribution brought to you by Ayn Rand loving Alan Greenspan and his Investment Bankster Cronies, AKA "The Roving Cavaliers of Credit"...
I suspect Rand would have considered Greenspan a sell-out for running the Federal Reserve unless of course it was his plan all along to damage the economy ala Fransisco for which I have seen no evidence.
There's no way a real-time missile tracking system is going to be dealing with time at an accuracy of 0.1 sec.
I suspect the terms accuracy and precision were confused. The tracking system could very well be designed with a precision of 0.1 seconds (with the associated programming error causing an offset after hand-off which drifts over time) but maintain an accuracy much better than that. While it is unusual, it is not unknown for conversions between analog and digital domains to have integral non-linearity errors much much less than the resolution.
Yes military grade guidance systems that are accurate to with 1 meter and travel 500 miles are very advanced and a hobbyist couldn't build that from hobby store parts.
I would only consider designing and building it a challenge but microcontrollers and FPGAs are not hobby store parts. The most difficult problems would be economical testing (failure is expensive) and terminal guidance.
I could build a GPS receiver without ASICs but the precision code is encrypted and the necessary corrections are not available in real time which limits accuracy. That leaves other methods for terminal guidance which are either difficult to engineer like fast image recognition or require some type of target designation. Radio Electronics long ago had the designs for a sun seeking Estes style rocket which was amazingly simple.
Which is why the upcoming NVIDIA "Fermi" GPU based boards will support 4GB of ECC memory.
According to the patent nVidia filed, 4GiB if RAM on the Fermi will yield about 3.2GiB of addressable memory with ECC enabled. Instead of adding extra ECC bits, the 32 bit wide burst length is increased from 4 lines to 5 lines so for every 128 data bits loaded from a 32 bit wide channel, 160 bits is actually read with 16 bits thrown away. I wonder if the successor to GDDR3/5 will support a 36 bit wide channel for ECC applications.
USB provides 100mA. The current can be boosted to 500mA upon request. Sadly, the request must come from a device driver (rather than from the device itself), and that's why your BlackBerry, iPod, whatever won't charge when connected to the USB port on a computer that doesn't have device drivers for it.
If you enumerated as a secondary device like a disk could you then request 500mA without having to install a specialized device driver? I know my Sansa does this but not if it takes advantage of a higher charging current.
A USB cable has +5V sitting on one of its pins, and can deliver up to 500mA of it, at all times.
This is incorrect. A USB port can deliver 100mA at all times but the standard requires enumeration before delivering 500mA because not all sources (unpowered hubs for example) can supply 500mA. It's actually a lot like the new PoE standard where a minimum power is guaranteed and higher power is available after some type of handshaking.
Realize that a RF poweramp will only have peak efficiency for some specific limited range of output power settings. If you make a device that is capable of 20dBm output, there is no way the same device will be efficient at 0dBm.
It is relatively common now where high efficiency over a large transmit power range is needed for the supply voltage of the power amplifier to be adjusted for a given transmit power. This is also often done in combination with various techniques for increasing linearity.
Disabling the final power amplifier stage and taking the RF output from an earlier stage is also sometimes done.
Any moderately recent AMD CPU will support ECC, and it's not hard to find a mainboard that does as well (for example I believe any ASUS mainboard for AMD will support ECC, I know the one I checked a couple days ago does (cheapest ASUS AM3 mainboard on Newegg then, probably still is, only like $5 more than the cheapest other AM3 board)).
I built a Phenom II 940 with 8GB of DDR2 ECC on an Asus M3A78-T at the beginning of the year which works great. A system built around the cheapest version of the Xeon i7 at the time would have more than doubled the total cost of just the CPU, motherboard, and memory. I used part of the considerable savings to buy a fast hardware RAID controller and 4 big SATA drives.
You could build a Xeon i5 systems supporting ECC now but it would still cost more than an equivalent Phenom II system.
When I last checked, Asus supported ECC on every AMD/ATI based AM2+ and AM3 motherboard. Gigabyte did also with the exception of those with built in video for some reason.
Some motherboards only lack ECC support in the BIOS which as I understand it you can enable and support in Linux or BSD after booting.
It's better if you just search for DDR-2 800 and pick out the ECC compared to the non. They are pretty much the same price, but the ECC is genearlly slower (due to higher latency) than non-ECC. Whether or not that matters to you or not is personal preference. Clearly since manufacturers don't see the need to include ECC in desktop level PCs there is not exactly a public outcry for this RAM.
Any latency difference with current DDR2 and DDR3 memory is primarily a function of the memory controller and how cache lines are handled. Specifically for the later, if you are only writing out full cache lines then read/modify/write cycles to support ECC are not necessary. Critical word first access is no longer significant because burst transfer rates have increased so much compared to the physical DRAM access time. This is especially the case with current systems switching to faster and narrower memory channels. Phenom, i5, and i7 based CPUs all support independent 64/72 bit memory channels with ECC applied across a 2 or 4 line burst size (128/144 or 256/288 bits). Ganging between channels is used to make ECC chipkill more effective although the Xeon version of the i7 with an odd number of channels would seem to have a problem with this.
The performance difference on my Phenom II 940 with and without ECC is insignificant and even difficult to measure.
Has it been published in any of Larry Niven's short story compilations? I don't think I've seen it before, but I would certainly like to.
"Rotating Cylinders and the Possibility of Global Causality Violation" was published in "Convergent Series" which is long out of print. Some more recent collections of his stories and essays have been published which may include it.
Either they're spewing out energy, which goes down in intensity as the square of the distance, or they're like Sony, and making big air-core transformers, where the fields go down as the CUBE of the distance.
Hmmmmm. I wonder what happens when you accidentally create a shorted turn in proximity to the transmitter.
Power and energy are too often confused when discussing electric vehicles. Capacitors already have the needed power density. They just lack the energy density and I am not sanguine that they will ever exceed chemical batteries in that respect.
Currently most hybrid vehicles size the battery packs based on longevity and power requirements making for a rather short electric only range. The GM Volt and other electric vehicles designed to run exclusively on battery power for significant distances have limitations because of battery pack energy requirements and not power requirements. By the time you have accumulated enough cells to meet your energy requirements, you are way above any likely power requirements that the car would require.
That is one of the reasons Toyota continues to use NiMH cells in their hybrids versus a lithium based chemistry. The former is more economical for a given power even if not for a given energy. It is too bad that the Cobalsys patents have been holding up large format NiMH cell development and production for years in the US. High power density lithium cells have only recently become generally available and I was rather surprised when I first saw them in power tools.
Capacitors have two problems: Low energy density (which may not matter for hybrid electric vehicles where you just want improved performance for a given engine power and regenerative braking) and variable output voltage. The later complicates the power electronics for the AC or DC motors because the input voltage has to vary over a much wider range if you want to actually recover a significant amount of energy from the capacitor.
You might notice that Coleman produces that screwdriver using supercapacitors but does not produce an equivalent cordless drill because the energy density just is not there to be even close to useful.
At least battery powered cars can currently be built and only suffer from an economics (or political if you include patents) problem.
The story of Moria has at least two different movies in it between the original founding and fall as well as Balin's return. You also also have Lonely Mountain and Dale between the time of the The Hobbit through The Lord of the Rings were they were besieged (from Dol Guldur?) as well. The stories of the origin of the Witch King of Angmar and the fall of Arnor would be interesting.
The history of Dol Guldur in southern Mirkwood is also possibility.
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You can have my Signetics WOM when you pry it from my dead cold S-100 bus.
I actually prefer a hydraulic clutch because then I don't have to periodically adjust the cable or linkage length.
They did not do this where I learned but I have always driven a manual transmission. Putting the car into gear and releasing the clutch to restart the engine is second nature for me if already moving. I have always owned cars that I could push start solo.
Even when completely rebuilt and adjusted, I have never used a drum parking brake that could stall the engine. Lock up the rear wheel or hold the car on an incline? Sure. But they will not stall the engine on a rear wheel drive car. Try using your parking brake sometime to slow down from freeway speeds. It takes quite a bit of distance.
The law makes a distinction between data in transit and data in storage. The former has more protection through wiretap laws at least up until recently than the later. Email stored on a server awaiting download via POP3 or similar is considered data in storage.
I long ago decided that opportunistic encryption was the endgame in the battle over 4th amendment protection of data in transit which is a poor outcome for both sides. If government lacks the ability to enforce or even define 4th amendment protections for private data, then all private data without exception in transit through third parties should be encrypted.
SST has had such a device out for a couple of years now:
http://www.sst.com/about_sst/news/detail.dot?crumbTitle=NewsDetail&id=361
The SST device includes all of the hardware on chip to handle caching, ECC, and NAND Flash management so those operations are transparent. The on-chip static RAM is divided between program memory and XiP cache under user control.
I gather from reading various trade articles on the subject that the motivation for XiP capability using Nand Flash is the density improvement. Single devices having separate Nor and Nand arrays for code and data respectively have been available for a long time but the Nor area penalty has become significantly enough to warrant significant complexity if it can be left out.
I suspect code shadowing is a better solution in most applications.
Greenspan was appointed chairman of the Federal Reserve about 5 years after Rand was dead. I've known about their association since reading his essays published in her books.
Him running the Federal Reserve always struck me as a very Dr. Robert Stadler kind of activity although to be fair his advice to congress was regularly ignored.
That is not what Execute in Place means in the context of Flash memory. Most NOR Flash naturally supports Execute in Place which requires random access whereas NAND Flash does not. When applied to NAND Flash, the Flash chip itself caches accessed pages internally and presents them through a DRAM or SRAM like interface as random access memory. Before this if you wanted to execute code out of NAND Flash, as you point out, you had to manually copy it to another location first which is decidedly not Execute in Place.
I am familiar with various ARM based microcontrollers and they almost certainly use use NOR like Flash to inherently support Execute in Place because there are no delays when crossing Flash page boundaries and all accesses require the same number of wait states without any exceptions. Given the common real time nature of microcontroller applications, if there were delays when accessing new pages it would be highlighted in the specifications.
There is also the Heinlein method. You could subsidize children by older couples who elected not to have children when they were young. Extending the time between generations slows down population growth just like having fewer children does. As a bonus, over time this would gradually weed out risky genes and behaviors which cause early death. * This would be rather damaging to any social security like ponzi scheme though unless you could raise productivity so it is doubly politically impractical and some nations (Italy and Japan that I know of) actually encourage the opposite.
* There was a research project involving east coast opossums which demonstrated that selecting for late reproduction could significantly extend individual lifetimes in later generations by removing early cancer causing and other early onset debilitating genes. In the specific case of the opossums, a couple of generations of selection did much better than double individual lifetimes.
The nature of the construction they used, unreinforced masonry in compression, is one of the few construction methods that scales up in length, area, and volume reliably. Such structures never fail in compression because the crush strength of stone is so much higher than the forces involved in any economical structure.
This is difficult to do in a state like California where zoning is extensively used to divide business and housing for purposes of rent seeking. There are very few areas where travel by bicycle is remotely safe.
I suspect Rand would have considered Greenspan a sell-out for running the Federal Reserve unless of course it was his plan all along to damage the economy ala Fransisco for which I have seen no evidence.
I suspect the terms accuracy and precision were confused. The tracking system could very well be designed with a precision of 0.1 seconds (with the associated programming error causing an offset after hand-off which drifts over time) but maintain an accuracy much better than that. While it is unusual, it is not unknown for conversions between analog and digital domains to have integral non-linearity errors much much less than the resolution.
I would only consider designing and building it a challenge but microcontrollers and FPGAs are not hobby store parts. The most difficult problems would be economical testing (failure is expensive) and terminal guidance.
I could build a GPS receiver without ASICs but the precision code is encrypted and the necessary corrections are not available in real time which limits accuracy. That leaves other methods for terminal guidance which are either difficult to engineer like fast image recognition or require some type of target designation. Radio Electronics long ago had the designs for a sun seeking Estes style rocket which was amazingly simple.
According to the patent nVidia filed, 4GiB if RAM on the Fermi will yield about 3.2GiB of addressable memory with ECC enabled. Instead of adding extra ECC bits, the 32 bit wide burst length is increased from 4 lines to 5 lines so for every 128 data bits loaded from a 32 bit wide channel, 160 bits is actually read with 16 bits thrown away. I wonder if the successor to GDDR3/5 will support a 36 bit wide channel for ECC applications.
If you enumerated as a secondary device like a disk could you then request 500mA without having to install a specialized device driver? I know my Sansa does this but not if it takes advantage of a higher charging current.
This is incorrect. A USB port can deliver 100mA at all times but the standard requires enumeration before delivering 500mA because not all sources (unpowered hubs for example) can supply 500mA. It's actually a lot like the new PoE standard where a minimum power is guaranteed and higher power is available after some type of handshaking.
It is relatively common now where high efficiency over a large transmit power range is needed for the supply voltage of the power amplifier to be adjusted for a given transmit power. This is also often done in combination with various techniques for increasing linearity.
Disabling the final power amplifier stage and taking the RF output from an earlier stage is also sometimes done.
I built a Phenom II 940 with 8GB of DDR2 ECC on an Asus M3A78-T at the beginning of the year which works great. A system built around the cheapest version of the Xeon i7 at the time would have more than doubled the total cost of just the CPU, motherboard, and memory. I used part of the considerable savings to buy a fast hardware RAID controller and 4 big SATA drives.
You could build a Xeon i5 systems supporting ECC now but it would still cost more than an equivalent Phenom II system.
When I last checked, Asus supported ECC on every AMD/ATI based AM2+ and AM3 motherboard. Gigabyte did also with the exception of those with built in video for some reason.
Some motherboards only lack ECC support in the BIOS which as I understand it you can enable and support in Linux or BSD after booting.
Any latency difference with current DDR2 and DDR3 memory is primarily a function of the memory controller and how cache lines are handled. Specifically for the later, if you are only writing out full cache lines then read/modify/write cycles to support ECC are not necessary. Critical word first access is no longer significant because burst transfer rates have increased so much compared to the physical DRAM access time. This is especially the case with current systems switching to faster and narrower memory channels. Phenom, i5, and i7 based CPUs all support independent 64/72 bit memory channels with ECC applied across a 2 or 4 line burst size (128/144 or 256/288 bits). Ganging between channels is used to make ECC chipkill more effective although the Xeon version of the i7 with an odd number of channels would seem to have a problem with this.
The performance difference on my Phenom II 940 with and without ECC is insignificant and even difficult to measure.
"Rotating Cylinders and the Possibility of Global Causality Violation" was published in "Convergent Series" which is long out of print. Some more recent collections of his stories and essays have been published which may include it.
Hmmmmm. I wonder what happens when you accidentally create a shorted turn in proximity to the transmitter.
Power and energy are too often confused when discussing electric vehicles. Capacitors already have the needed power density. They just lack the energy density and I am not sanguine that they will ever exceed chemical batteries in that respect.
Currently most hybrid vehicles size the battery packs based on longevity and power requirements making for a rather short electric only range. The GM Volt and other electric vehicles designed to run exclusively on battery power for significant distances have limitations because of battery pack energy requirements and not power requirements. By the time you have accumulated enough cells to meet your energy requirements, you are way above any likely power requirements that the car would require.
That is one of the reasons Toyota continues to use NiMH cells in their hybrids versus a lithium based chemistry. The former is more economical for a given power even if not for a given energy. It is too bad that the Cobalsys patents have been holding up large format NiMH cell development and production for years in the US. High power density lithium cells have only recently become generally available and I was rather surprised when I first saw them in power tools.
Capacitors have two problems: Low energy density (which may not matter for hybrid electric vehicles where you just want improved performance for a given engine power and regenerative braking) and variable output voltage. The later complicates the power electronics for the AC or DC motors because the input voltage has to vary over a much wider range if you want to actually recover a significant amount of energy from the capacitor.
You might notice that Coleman produces that screwdriver using supercapacitors but does not produce an equivalent cordless drill because the energy density just is not there to be even close to useful.
At least battery powered cars can currently be built and only suffer from an economics (or political if you include patents) problem.
The story of Moria has at least two different movies in it between the original founding and fall as well as Balin's return. You also also have Lonely Mountain and Dale between the time of the The Hobbit through The Lord of the Rings were they were besieged (from Dol Guldur?) as well. The stories of the origin of the Witch King of Angmar and the fall of Arnor would be interesting.
The history of Dol Guldur in southern Mirkwood is also possibility.