I used to store CDs that way when I ran out of jewel cases but lost an entire spindle once to dust scratches even with the little ridge. I am sure it helps when the disks are packaged in a clean environment and shipped to you but afterwards I found it to be inadequate compared to sleeves or separate cases.
The problem with spindles other then actually finding one disk is that if you twist them, the CDs or DVDs tend to get scratched axialy which is the most difficult orientation for the error correcting code to recover from. This is the same reason they recommend cleaning them in the radial direction.
I am not convinced it is possible to resolve Apple's use of Intel versus AMD processors except possibly in the case of laptops which would naturally lead to them using Intel over their whole product line (at least to start) even if they determined AMD would be a better choice for some configurations. Even including all of the public pricing information available and different configurations, Intel could have made an offer too good for Apple to refuse and there is enough evidence they have done such things is the past not to factor that uncertainty in. Apple made the safe bet even without technical considerations.
there's another thing AMD's onboard NB locked them out of. Since the CPU interfaces directly to the RAM, that means you have to have a RAM subsystem for each CPU chip.
There is no requirement for dual Opteron systems and by extension the proposed 4x4 system to have memory on each CPU. At least one of the early dual processor boards only attached DIMM sockets to one CPU and the other CPU had no local memory. Benchmark tests on that system as well as others configured with memory on only one processor actually showed very little performance degradation. I tend to look at RAM expansion first so would naturally never advocate buying a motherboard restricted in that way but it does work.
The only difficulty I find in AMD's position is their chipset support. Any of my Intel systems have excellent driver support for everything included in the Intel chipset. I have several nVidia test systems and I find between poor driver support, inadequate documentation, and flaky IDE/ethernet/PCI controllers that they are difficult to justify.
If anything I am but it was more a case that I agreed with his position in the debate about the costs of AMD's integrated memory controller and whether is was appropriate for single processor consumer systems.
It is not a matter of reducing the number of chips on a motherboard for AMD or necessarily matching Intel's price. It was a matter of having a solution that would work were Intel was weak (2 to 8 cpu workstations and servers), using one design to cover both that market and the single cpu consumer market, and using greater economy of scale to cover the extra research, development, and production expenses. I agree with the notion that the mass production of one basic design paid for the added cost of the integrated memory controller which in turn allowed them to best Intel in the 2 to 8 processor server market.
If anything, the AMD design actually uses fewer chips then the Intel one since the north bridge as such no longer really exists. AMD chipsets still have one but it no longer has a memory controller and serves mostly as an I/O bridge for the graphics subsystem. If it was not for SLI motherboard configurations, there would only be a south bridge with all of the I/O hanging off of it. I am not sure if they are thinking of this with their upcoming 4x4 systems but the possibility exists to place the graphics processor into one of the HT connected external slots making their current north bridge completely vestigial. I do not see the graphics chip vendors wanting to split their wares between PCIe and HT voluntarily but the rumors about AMD and ATI have been suggestive. These kinds of things look to be at least a year away making them at the horizon of speculation.
As for Apple, it was more important that they switch away from PowerPC to x86 while they are strong then the choice between Intel and AMD. Once that was decided, Intel was the obvious choice just based on mitigating the risk as much as possible. I do not know any technical reason a Mac Mini could not be made using an AMD processor and chipset but why make things more complicated then necessary when you are transitioning to a new architecture? I am sure the Apple skunk works has some AMD systems running Mac OSX as a plan B just in case. Apple with Steve Jobs at the helm has been nothing if not prepared for the unexpected future. I am reminded somewhat of Intel when they made the life or death switch from memory production to microprocessors.
I've heard rumors Intel wants to go to FB-DIMMs with Conroe. We'll see what happens if they do that. That could really hurt them in the same way you mention with Athlon non-registered ECC.
They have working north bridge memory controllers supporting 4 banks of FB-DIMMS already but the RAM is currently too expensive when compared to DDR2 for the consumer space. That design is really for systems requiring more then 4 to 8 GBytes of RAM where DDR or DDR2 become very difficult to layout when your memory controller is on a single chip. FB-DIMMS are also poorly suited for the portable market do to the extra power required.
I do not know why AMD segmented their market between the single and dual processor system instead of between the dual and quad processor systems. If they had done it the other way, it could have been like having dual core systems 2 years earlier. Presumably their bean counters knew what they were doing but the 4x4 design they recently showed makes it look like either they have reconsidered that initial decision or things have changed enough leading to a different outcome.
In the first case, the 875P and the socket 939/940 Athlons fetch from memory like AA AA AA. There is only one bank which is 128 bits wide.
In the second case, the 975X and other Intel DDR2 memory controllers fetch AB AB AB. They use both banks of 64 bits each simulaneously.
For the 875P and the socket 939/940 Athlons, the 64 bit DIMMs are arranged in pairs to make a single bank of RAM 128 bits wide. The memory controller fetches 4 lines of 128 bits at a time to fill the processor's cache. Note that there is nothing inherent about DDR memory design that requires them to use 1 bank of 128 bits. They could also have used 2 interleaved banks of 64 bits like the current DDR2 controllers but there was not enough advantage to doing so until DDR2 came out. Either Intel was planning ahead for dual core consumer processors or there were performance reasons to use 2 seperate banks with DDR2.
For the Intel DDR2 controllers, the 64 bit DIMMs can be accessed separately but simultaneously allowing the fetching of data from 2 non continuous blocks of memory as long as they are in alternate banks. Since each bank is half the size of the single 128 bit bank in the earlier DDR controllers, they fetch 8 lines instead of 4 but do it at twice the speed. It is like having two completely separate memory controllers with the odd addresses on one and the even addresses on the other except they alternate every 64 bytes. Both systems (1 bank of 128 bits and 2 banks of 64 bits) use the same number of data, address, and clock lines except for the interface differences between DDR and DDR2. There is actually an interesting comment about this in the Athlon 64 technical data about how the address and clock drivers for each 64 bit DIMM mirror each other allowing 4 total DIMMs without external buffering.
Intel would need a FSB-1600 to keep up with their DDR2-800 controllers. AMD does not have to worry about it since their memory controller presumably communicates with the crossbar on their processor at least that fast. There are actually some indications that a single core on the socket AM2 processors can not fetch data fast enough to saturate the memory controller. There may be an unresolved design issue or it could simply be that a single core can not issues loads fast enough. I have not seen any dual core tests to confirm anything though.
I just don't see AMD's solution making financial sense in the bulk of the market in the long term.
Hehe. Linus Torvalis was just involved in a discussion like this over at RWT. It makes PERFECT sense for AMD to have done this. It allows their fabs to produce a single basic design for multiple markets instead of dividing their effort into multiple designs. The mass production of one design lowered the cost enough to make up for any extra expense in the consumer market. This same effect has allowed x86 to overtake higher end markets from the bottom over time. Presumably Sony and IBM (or at least Sony) are looking to do the same thing to x86 with Cell starting with the console market but I think Cell is too specialized to pull it off not to mention Sony's past successes in introducing new standards and products. They have become expert in snatching defeat from he jaws of victory.
Incidently, I think one of AMDs first mistakes was not allowing cheap dual processor systems using socket 939 Athlons with ECC and non registered DIMMs. They could have sold twice as many processors to the high end consumer market but there are many reasons including fab capacity that this may not have been an option. Their upcoming 4x4 initiative looks like a step back to this.
Classic interleaving was used because the DRAM arrays were unable to supply data fast enough for the busses of the time. Interleaving allowed you to use one bus at twice or even four times the frequency that one DRAM array would support. Internally, DDR and DDR2 chips actually act very similar to this when they send busts of 4 or 8 transactions across one bus.
Each cache line fill is 64 bytes. The processor actually picks which of the 4 sets of 16 bytes it wants from the 128 bit DDR bank which then returns that one first and the other 3 sets of 16 bytes afterward in a total burst of 4 transactions. DDR controllers like the Intel 875P and the Athlon 64 DDR use two banks of 64 bits in lockstep. Each bank is presented with exactly the same commands and addresses and each transaction is 128 bits in size.
With the Intel DDR2 controllers, you have the option of interleaving both 64 bit banks such that the 64 byte cache fill lines come from alternate banks. Now the processor uses a burst size of 8 instead of 4 to get 64 bytes from one 64 bit bank. Since DDR2 can run at twice the clock speed of DDR, it can fulfill the entire request just as quickly as a DDR bank of twice the width. Since the other DDR2 bank is free, the DDR2 controller can execute 2 different memory requests simultaneously as long as they are both in different banks. This could be very handy on a multiprocessing system where 2 processors could alternately access each bank simultaneously. Now if someone would just make dual core processors . . .
AMD's advantage is that they are not limited by FSB throughput (Intel's fastest FSB is slower then 128 bit wide DDR2-800) and the benchmarks do show very high DDR2 memory transfer rates. Unfortunately, it appears they only modified the older Socket939/940 memory controller enough to support DDR2 and may be still using 1 bank of 128 bits with a burst size of 4 resulting in larger command overhead and fewer available pages. I do not have access to the AM2 design or programming specifications to verify this however.
You could think of AMD's integrated memory controller as just moving part of the north bridge onto the CPU. The result is better latency between the CPU and memory (one less off chip bus to deal with) while increasing the latency between any I/O devices and memory. As you point out, it was probably most important to them in facilitating their NUMA architecture.
None of this answers why latencies were so much worse with the initial DDR2 chipsets. Some of it was that the initial DDR2 cores were running at a lower frequency then the DDR cores. The cores themselves were different do to at least supply voltage changes making the established DDR cores more comparatively mature. There are some minor command differences as well but I have not seen an accurate enough description of them to judge.
The additional grids added to tubes serve a different purpose then the "triple gate" Intel is testing. Tetrodes add a screen grid which acts to lower Miller capacitance (the capacitance between the control grid and plate multiplied by the voltage gain) as well as lowering space charge. Both bipolar transistors and field effect transisters suffer from Miller capacitance and in the case of dual gate MOSFETs the second gate can be used in a similar way or a cascode configuration can be used. The third grid in a pentode suppresses secondary emmision from the plate which raises the gain.
My point is that Intel DDR and DDR2 chipsets use very different memory configurations (one bank of 128 bits versus two interleaved banks of 64 bits) and that the latency tests comparing them may not be accurately measuring what is really happening. Depending on the specifics of the test, they could be comparing one bank 128 bits wide versus one bank 64 bits wide running at twice the clock speed in which case fill rates and latency should be almost identical. If the test uses a block size larger then the burst size on one DDR2 bank, both interleaved banks will be used and the DDR2 fill time could be almost half of the DDR time except the Intel FSB does not have the transfer rate to support it. Were the latency tests for the first available word or for a cache line fill or what? In a lot of cases, it is not clear what was actually being measured and none of the tests I have seen made any attempt to simultaneously fetch from separate interleaved areas of memory where the 128 bit wide DDR system would perform relatively poorly.
Read what I said about AM2 performance again. They SHOULD be able to make better use of DDR2 then Intel because of lack of FSB limits BUT something is preventing it. I was not able to find any AM2 detailed specifications online and the Athlon 64 BIOS programming guide does not cover the AM2 yet. My guess is it is treating both 64 bit banks of DDR2 as one bank 128 bits wide (Like the Intel DDR controllers, the Athlon 64 DDR controller does not support interleaving two 64 bit banks that I could tell.) and using the smaller DDR2 burst size. This will give almost identical latencies for very small transfers but make the command overhead percentage larger then if it used the larger burst size and interleaved banks.
I was curious enough to dig through the Intel north bridge data sheets for the 875P DDR and 975X DDR2 memory controllers. AMD's documentation is not as easy to digest and I was not able to find any detailed data on the socket AM2 processors.
The Intel 975X interleaves two 64 bit channels while the 875P uses both DRAM banks as one 128 bit channel. Naive benchmarking will not show any advantage in fetching simultaneously from separate interleaved banks and Intel's FSB throughput is too low to take real advantage of it anyway. AMD should be in a better position as the AM2 memory controller should be able to use the full DDR2 bandwidth but it may be using the separate DDR2 banks as one with half the open pages and a poor total burst fill size. Adding a second core to a design already prepared for it is probably easier to justify then making major changes to the memory controller when you have a major derivative design coming out in the next year.
I posted asking about this before (http://slashdot.org/comments.pl?sid=173501&cid=14 439092) but never got a real answer. There was a discussion on RWT that touched the DDR2 versus DDR latency which other then the possibility of delaying the command cycle in DDR2 brought up that the DDR2 Intel controllers (and by extension the AM2 controller) were actually using 2 x 64 channels instead of 1 x 128 in order raise the efficiency. I never followed up on it completely as I have no DDR2 motherboards to play with. Going through the Intel north bridge technical documents should resolve it.
Would not that be a Beowulf cluster of Grendels? In the sequel you get to find out what eats Grendels.
I forget which but one of the role playing games we had listed Lucifer's Hammer in the bibliography for further reading concerning the destruction of civilization and cannibalism. Unlike the various poorly done movies, I always enjoyed Lucifer's Hammer just for realizing one third of the way through that the impact has already happened and most of the story remains. Save the lightning.
I agree completely about the reliablility issues. For myself, I would tend to derate any consumer or industrial PC power supply by 2/3rds. Like all things that make a transition to consumer space, marketing and poor engineering takes it toll.
As far as efficiency, for switching power supplies it tends to either be maximum at maximum load or only decrease slightly. It would be very unusual to find a switching power supply that had a significant efficiency decrease at maximum load because of cooling issues. Any loss do to efficiency has to be directly dissapated by the power supply itself and to have the efficiency go down as the power goes up would quickly lead to power dissapation issues. For some designs there IS a large load that could cause this but it would be above the rated continuous load.
The rating for the power supply is based on maximum continuous load and not the actual load drawn from the power line. If it says 400 watts, then you can have some combination of loads on the outputs drawing up to 400 watts total presumably without failure. The actual power drawn from the line input is proportional to the output load plus whatever inefficiencies (typically 75 to 85 percent) the power supply itself has. Power supplies normally loose efficiency at very light loads however so it pays to only use a power supply as large as necessary after taking into account worst case conditions. The effect is monotonic so even with this loss of efficiency, lowering the output power will always lower the input power.
If your 400 watt power supply was ALWAYS drawing 400 watts, then at light loads you would expect the exhaust temperature to be sky high as it dissipates the energy not being used. Luckily, this is not the case.
Channel Capacity (bits/s) = 0.332 x Bandwidth x SNR (db) from Shannon-Hartley theorem is a rough estimate but assumes better conditions then they would likely get. Pessimistically, 10MHz and 10db gives 33.2 Mbits/s total. A lot depends on the details like cell size, transmit/receive turn around time, and transmit power.
One thing to note is that you can't do anything to shape your download traffic.
You can still shape your download traffic from the customer side but it is not as effective as shaping your upload traffic. While it can not prevent bursts of incoming packets from filling the queue, it still has the effect of activating TCP flow control which serves to keep the incoming queue empty and latency low during continuous transfers.
I have not played with it yet but ALTQ has provisions for manipulating TCP flow control directly which would allow the same result without dropping incoming packets after they have propogated across the relatively expensive cable or DSL link.
Not only is it not known to have happened but ethical standards have prevented this from being performed as any sort of experiment that I am aware of. Chimpanzees, gorillas, and orangutans have 24 chromosomes instead of our 23 because of the fusion of 2 smaller great ape chromosomes into human chromosome 2 but such does not necessarily make the creation of a mule impossible.
I should add that the machine in the movie was identical to one of our machines down to the font used on the dial and the paint on each chassis.
While the thought of testing a watermelon in compression is humorous I can not see it working out well in real life. Still, it was a nice touch and fit in with the movie as I understand it.
Let me assure you that we did. While it was called a tensile strength tester it could be used in tension or compression even without a jig. We were slowly replacing them with dead load machines for ease of use and accuracy. Our applications involved linearity, hysteresis, and creep way below failure so the hydraulic based machines were actually a poor match for what we really needed.
It actually made a relatively poor can crusher because of limited travel but worked fine for coins.
We used to crush soda cans in our tensile strength tester. Unfortunately, I am the only person who I know of that has both seen the movie and recognised the machine the watermelon was in so was never able to share my appreciation of the joke with anybody.
For anybody who tries it, make sure any mounted load cell is shielded from aluminum slivers if you crush cans.
Behavioral interviewing has been seized on by HR people as being somehow more valid than any other technique.
It would be more accurate to say any other technique legally available. The use of tests to gauge the performance of prospective employees has a long legal history. In general, tests that are specific to the job have been deemed acceptable but tests of a more general nature are not mostly because of discrimination issues. I suspect the HR people are using the tools available to them rather then picking the ones they might prefer under other circumstances.
I used to deal with these issues a lot when I worked with low level analog design. The input and output circuitry in the audio amplifiers can rectify any amplitude modulated RF that they detect. That includes the output of the cell phone if it uses a modulation that does not have a constant envelope. In the case of FM or a constant envelope modulation the bias point may change in the amplifier but that is not normally a problem or audible. In poor designs it is possible for the amplifier to go into oscillation and even self destruct.
TDMA multiplexes by assigning a time slot for the phone to transmit in and at other times its transmitter is shut down. Turning the transmitter on and off is just another form of amplitude modulation and it is very easy for low frequency circuits to detect it. Systems that use QAM might also cause this problem but I would normally expect the amplitude modulation to be too fast for it to be detected.
Solutions include shielding the input and output leads on the amplifier as well as designing the amplifier to be resistant to this kind of EMI. I have successfully wound RF chokes into the input, output, and power supply leads in the past to make existing equipment more resistant.
I do not have to cherry pick anything. The PARTRIOT act passed with overwhelming support from both parties. The Democrats are saying they would have acted better then the Republicans if they had controlled the White House yet where have they shown themselves any different in Congress? Has there been anything except token resistance?
Both parties are statist and centralization of power at the expense of the Constitution and the Bill of Rights will continue under either one. Picking one or the other merely selects which civil rights will be given up first and not which will be ultimately retained.
None of this is a surprise. Between Duverger's law, Hotelling's law, and plurality voting we get exactly the kind of representation I would expect and we deserve. The differences between the Republicans and Democrats are cosmetic.
Consider the problems we face with campaign finance and corporate corruption in our politics. Normally one would like to only have to bribe the winner of any election but in our system, it only costs twice as much to control everything.
I might have believed this if the Democrats had not voted for the PARTRIOT act as well. 9/11 would still have happened and our response would have been just as poorly conceived.
It is 50% efficiency for a load perfectly matched to the source for maximum power transfer. In power distribution loads are hardly ever matched that way for this very reason.
Excluding reactive losses, transformer losses come from the hysteresis of the core material (basically zero at 60 Hz) and the resistive winding losses.
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I used to store CDs that way when I ran out of jewel cases but lost an entire spindle once to dust scratches even with the little ridge. I am sure it helps when the disks are packaged in a clean environment and shipped to you but afterwards I found it to be inadequate compared to sleeves or separate cases.
The problem with spindles other then actually finding one disk is that if you twist them, the CDs or DVDs tend to get scratched axialy which is the most difficult orientation for the error correcting code to recover from. This is the same reason they recommend cleaning them in the radial direction.
I am not convinced it is possible to resolve Apple's use of Intel versus AMD processors except possibly in the case of laptops which would naturally lead to them using Intel over their whole product line (at least to start) even if they determined AMD would be a better choice for some configurations. Even including all of the public pricing information available and different configurations, Intel could have made an offer too good for Apple to refuse and there is enough evidence they have done such things is the past not to factor that uncertainty in. Apple made the safe bet even without technical considerations.
there's another thing AMD's onboard NB locked them out of. Since the CPU interfaces directly to the RAM, that means you have to have a RAM subsystem for each CPU chip.
There is no requirement for dual Opteron systems and by extension the proposed 4x4 system to have memory on each CPU. At least one of the early dual processor boards only attached DIMM sockets to one CPU and the other CPU had no local memory. Benchmark tests on that system as well as others configured with memory on only one processor actually showed very little performance degradation. I tend to look at RAM expansion first so would naturally never advocate buying a motherboard restricted in that way but it does work.
The only difficulty I find in AMD's position is their chipset support. Any of my Intel systems have excellent driver support for everything included in the Intel chipset. I have several nVidia test systems and I find between poor driver support, inadequate documentation, and flaky IDE/ethernet/PCI controllers that they are difficult to justify.
If anything I am but it was more a case that I agreed with his position in the debate about the costs of AMD's integrated memory controller and whether is was appropriate for single processor consumer systems.
It is not a matter of reducing the number of chips on a motherboard for AMD or necessarily matching Intel's price. It was a matter of having a solution that would work were Intel was weak (2 to 8 cpu workstations and servers), using one design to cover both that market and the single cpu consumer market, and using greater economy of scale to cover the extra research, development, and production expenses. I agree with the notion that the mass production of one basic design paid for the added cost of the integrated memory controller which in turn allowed them to best Intel in the 2 to 8 processor server market.
If anything, the AMD design actually uses fewer chips then the Intel one since the north bridge as such no longer really exists. AMD chipsets still have one but it no longer has a memory controller and serves mostly as an I/O bridge for the graphics subsystem. If it was not for SLI motherboard configurations, there would only be a south bridge with all of the I/O hanging off of it. I am not sure if they are thinking of this with their upcoming 4x4 systems but the possibility exists to place the graphics processor into one of the HT connected external slots making their current north bridge completely vestigial. I do not see the graphics chip vendors wanting to split their wares between PCIe and HT voluntarily but the rumors about AMD and ATI have been suggestive. These kinds of things look to be at least a year away making them at the horizon of speculation.
As for Apple, it was more important that they switch away from PowerPC to x86 while they are strong then the choice between Intel and AMD. Once that was decided, Intel was the obvious choice just based on mitigating the risk as much as possible. I do not know any technical reason a Mac Mini could not be made using an AMD processor and chipset but why make things more complicated then necessary when you are transitioning to a new architecture? I am sure the Apple skunk works has some AMD systems running Mac OSX as a plan B just in case. Apple with Steve Jobs at the helm has been nothing if not prepared for the unexpected future. I am reminded somewhat of Intel when they made the life or death switch from memory production to microprocessors.
I've heard rumors Intel wants to go to FB-DIMMs with Conroe. We'll see what happens if they do that. That could really hurt them in the same way you mention with Athlon non-registered ECC.
They have working north bridge memory controllers supporting 4 banks of FB-DIMMS already but the RAM is currently too expensive when compared to DDR2 for the consumer space. That design is really for systems requiring more then 4 to 8 GBytes of RAM where DDR or DDR2 become very difficult to layout when your memory controller is on a single chip. FB-DIMMS are also poorly suited for the portable market do to the extra power required.
I do not know why AMD segmented their market between the single and dual processor system instead of between the dual and quad processor systems. If they had done it the other way, it could have been like having dual core systems 2 years earlier. Presumably their bean counters knew what they were doing but the 4x4 design they recently showed makes it look like either they have reconsidered that initial decision or things have changed enough leading to a different outcome.
In the first case, the 875P and the socket 939/940 Athlons fetch from memory like AA AA AA. There is only one bank which is 128 bits wide.
In the second case, the 975X and other Intel DDR2 memory controllers fetch AB AB AB. They use both banks of 64 bits each simulaneously.
For the 875P and the socket 939/940 Athlons, the 64 bit DIMMs are arranged in pairs to make a single bank of RAM 128 bits wide. The memory controller fetches 4 lines of 128 bits at a time to fill the processor's cache. Note that there is nothing inherent about DDR memory design that requires them to use 1 bank of 128 bits. They could also have used 2 interleaved banks of 64 bits like the current DDR2 controllers but there was not enough advantage to doing so until DDR2 came out. Either Intel was planning ahead for dual core consumer processors or there were performance reasons to use 2 seperate banks with DDR2.
For the Intel DDR2 controllers, the 64 bit DIMMs can be accessed separately but simultaneously allowing the fetching of data from 2 non continuous blocks of memory as long as they are in alternate banks. Since each bank is half the size of the single 128 bit bank in the earlier DDR controllers, they fetch 8 lines instead of 4 but do it at twice the speed. It is like having two completely separate memory controllers with the odd addresses on one and the even addresses on the other except they alternate every 64 bytes. Both systems (1 bank of 128 bits and 2 banks of 64 bits) use the same number of data, address, and clock lines except for the interface differences between DDR and DDR2. There is actually an interesting comment about this in the Athlon 64 technical data about how the address and clock drivers for each 64 bit DIMM mirror each other allowing 4 total DIMMs without external buffering.
Intel would need a FSB-1600 to keep up with their DDR2-800 controllers. AMD does not have to worry about it since their memory controller presumably communicates with the crossbar on their processor at least that fast. There are actually some indications that a single core on the socket AM2 processors can not fetch data fast enough to saturate the memory controller. There may be an unresolved design issue or it could simply be that a single core can not issues loads fast enough. I have not seen any dual core tests to confirm anything though.
I just don't see AMD's solution making financial sense in the bulk of the market in the long term.
Hehe. Linus Torvalis was just involved in a discussion like this over at RWT. It makes PERFECT sense for AMD to have done this. It allows their fabs to produce a single basic design for multiple markets instead of dividing their effort into multiple designs. The mass production of one design lowered the cost enough to make up for any extra expense in the consumer market. This same effect has allowed x86 to overtake higher end markets from the bottom over time. Presumably Sony and IBM (or at least Sony) are looking to do the same thing to x86 with Cell starting with the console market but I think Cell is too specialized to pull it off not to mention Sony's past successes in introducing new standards and products. They have become expert in snatching defeat from he jaws of victory.
Incidently, I think one of AMDs first mistakes was not allowing cheap dual processor systems using socket 939 Athlons with ECC and non registered DIMMs. They could have sold twice as many processors to the high end consumer market but there are many reasons including fab capacity that this may not have been an option. Their upcoming 4x4 initiative looks like a step back to this.
Classic interleaving was used because the DRAM arrays were unable to supply data fast enough for the busses of the time. Interleaving allowed you to use one bus at twice or even four times the frequency that one DRAM array would support. Internally, DDR and DDR2 chips actually act very similar to this when they send busts of 4 or 8 transactions across one bus.
Each cache line fill is 64 bytes. The processor actually picks which of the 4 sets of 16 bytes it wants from the 128 bit DDR bank which then returns that one first and the other 3 sets of 16 bytes afterward in a total burst of 4 transactions. DDR controllers like the Intel 875P and the Athlon 64 DDR use two banks of 64 bits in lockstep. Each bank is presented with exactly the same commands and addresses and each transaction is 128 bits in size.
With the Intel DDR2 controllers, you have the option of interleaving both 64 bit banks such that the 64 byte cache fill lines come from alternate banks. Now the processor uses a burst size of 8 instead of 4 to get 64 bytes from one 64 bit bank. Since DDR2 can run at twice the clock speed of DDR, it can fulfill the entire request just as quickly as a DDR bank of twice the width. Since the other DDR2 bank is free, the DDR2 controller can execute 2 different memory requests simultaneously as long as they are both in different banks. This could be very handy on a multiprocessing system where 2 processors could alternately access each bank simultaneously. Now if someone would just make dual core processors . . .
AMD's advantage is that they are not limited by FSB throughput (Intel's fastest FSB is slower then 128 bit wide DDR2-800) and the benchmarks do show very high DDR2 memory transfer rates. Unfortunately, it appears they only modified the older Socket939/940 memory controller enough to support DDR2 and may be still using 1 bank of 128 bits with a burst size of 4 resulting in larger command overhead and fewer available pages. I do not have access to the AM2 design or programming specifications to verify this however.
You could think of AMD's integrated memory controller as just moving part of the north bridge onto the CPU. The result is better latency between the CPU and memory (one less off chip bus to deal with) while increasing the latency between any I/O devices and memory. As you point out, it was probably most important to them in facilitating their NUMA architecture.
None of this answers why latencies were so much worse with the initial DDR2 chipsets. Some of it was that the initial DDR2 cores were running at a lower frequency then the DDR cores. The cores themselves were different do to at least supply voltage changes making the established DDR cores more comparatively mature. There are some minor command differences as well but I have not seen an accurate enough description of them to judge.
The additional grids added to tubes serve a different purpose then the "triple gate" Intel is testing. Tetrodes add a screen grid which acts to lower Miller capacitance (the capacitance between the control grid and plate multiplied by the voltage gain) as well as lowering space charge. Both bipolar transistors and field effect transisters suffer from Miller capacitance and in the case of dual gate MOSFETs the second gate can be used in a similar way or a cascode configuration can be used. The third grid in a pentode suppresses secondary emmision from the plate which raises the gain.
My point is that Intel DDR and DDR2 chipsets use very different memory configurations (one bank of 128 bits versus two interleaved banks of 64 bits) and that the latency tests comparing them may not be accurately measuring what is really happening. Depending on the specifics of the test, they could be comparing one bank 128 bits wide versus one bank 64 bits wide running at twice the clock speed in which case fill rates and latency should be almost identical. If the test uses a block size larger then the burst size on one DDR2 bank, both interleaved banks will be used and the DDR2 fill time could be almost half of the DDR time except the Intel FSB does not have the transfer rate to support it. Were the latency tests for the first available word or for a cache line fill or what? In a lot of cases, it is not clear what was actually being measured and none of the tests I have seen made any attempt to simultaneously fetch from separate interleaved areas of memory where the 128 bit wide DDR system would perform relatively poorly.
Read what I said about AM2 performance again. They SHOULD be able to make better use of DDR2 then Intel because of lack of FSB limits BUT something is preventing it. I was not able to find any AM2 detailed specifications online and the Athlon 64 BIOS programming guide does not cover the AM2 yet. My guess is it is treating both 64 bit banks of DDR2 as one bank 128 bits wide (Like the Intel DDR controllers, the Athlon 64 DDR controller does not support interleaving two 64 bit banks that I could tell.) and using the smaller DDR2 burst size. This will give almost identical latencies for very small transfers but make the command overhead percentage larger then if it used the larger burst size and interleaved banks.
I was curious enough to dig through the Intel north bridge data sheets for the 875P DDR and 975X DDR2 memory controllers. AMD's documentation is not as easy to digest and I was not able to find any detailed data on the socket AM2 processors.
The Intel 975X interleaves two 64 bit channels while the 875P uses both DRAM banks as one 128 bit channel. Naive benchmarking will not show any advantage in fetching simultaneously from separate interleaved banks and Intel's FSB throughput is too low to take real advantage of it anyway. AMD should be in a better position as the AM2 memory controller should be able to use the full DDR2 bandwidth but it may be using the separate DDR2 banks as one with half the open pages and a poor total burst fill size. Adding a second core to a design already prepared for it is probably easier to justify then making major changes to the memory controller when you have a major derivative design coming out in the next year.
I posted asking about this before (http://slashdot.org/comments.pl?sid=173501&cid=14 439092) but never got a real answer. There was a discussion on RWT that touched the DDR2 versus DDR latency which other then the possibility of delaying the command cycle in DDR2 brought up that the DDR2 Intel controllers (and by extension the AM2 controller) were actually using 2 x 64 channels instead of 1 x 128 in order raise the efficiency. I never followed up on it completely as I have no DDR2 motherboards to play with. Going through the Intel north bridge technical documents should resolve it.
Would not that be a Beowulf cluster of Grendels? In the sequel you get to find out what eats Grendels.
I forget which but one of the role playing games we had listed Lucifer's Hammer in the bibliography for further reading concerning the destruction of civilization and cannibalism. Unlike the various poorly done movies, I always enjoyed Lucifer's Hammer just for realizing one third of the way through that the impact has already happened and most of the story remains. Save the lightning.
I agree completely about the reliablility issues. For myself, I would tend to derate any consumer or industrial PC power supply by 2/3rds. Like all things that make a transition to consumer space, marketing and poor engineering takes it toll.
As far as efficiency, for switching power supplies it tends to either be maximum at maximum load or only decrease slightly. It would be very unusual to find a switching power supply that had a significant efficiency decrease at maximum load because of cooling issues. Any loss do to efficiency has to be directly dissapated by the power supply itself and to have the efficiency go down as the power goes up would quickly lead to power dissapation issues. For some designs there IS a large load that could cause this but it would be above the rated continuous load.
The rating for the power supply is based on maximum continuous load and not the actual load drawn from the power line. If it says 400 watts, then you can have some combination of loads on the outputs drawing up to 400 watts total presumably without failure. The actual power drawn from the line input is proportional to the output load plus whatever inefficiencies (typically 75 to 85 percent) the power supply itself has. Power supplies normally loose efficiency at very light loads however so it pays to only use a power supply as large as necessary after taking into account worst case conditions. The effect is monotonic so even with this loss of efficiency, lowering the output power will always lower the input power.
If your 400 watt power supply was ALWAYS drawing 400 watts, then at light loads you would expect the exhaust temperature to be sky high as it dissipates the energy not being used. Luckily, this is not the case.
Channel Capacity (bits/s) = 0.332 x Bandwidth x SNR (db) from Shannon-Hartley theorem is a rough estimate but assumes better conditions then they would likely get. Pessimistically, 10MHz and 10db gives 33.2 Mbits/s total. A lot depends on the details like cell size, transmit/receive turn around time, and transmit power.
One thing to note is that you can't do anything to shape your download traffic.
You can still shape your download traffic from the customer side but it is not as effective as shaping your upload traffic. While it can not prevent bursts of incoming packets from filling the queue, it still has the effect of activating TCP flow control which serves to keep the incoming queue empty and latency low during continuous transfers.
I have not played with it yet but ALTQ has provisions for manipulating TCP flow control directly which would allow the same result without dropping incoming packets after they have propogated across the relatively expensive cable or DSL link.
Not only is it not known to have happened but ethical standards have prevented this from being performed as any sort of experiment that I am aware of. Chimpanzees, gorillas, and orangutans have 24 chromosomes instead of our 23 because of the fusion of 2 smaller great ape chromosomes into human chromosome 2 but such does not necessarily make the creation of a mule impossible.
I should add that the machine in the movie was identical to one of our machines down to the font used on the dial and the paint on each chassis.
While the thought of testing a watermelon in compression is humorous I can not see it working out well in real life. Still, it was a nice touch and fit in with the movie as I understand it.
Let me assure you that we did. While it was called a tensile strength tester it could be used in tension or compression even without a jig. We were slowly replacing them with dead load machines for ease of use and accuracy. Our applications involved linearity, hysteresis, and creep way below failure so the hydraulic based machines were actually a poor match for what we really needed.
It actually made a relatively poor can crusher because of limited travel but worked fine for coins.
We used to crush soda cans in our tensile strength tester. Unfortunately, I am the only person who I know of that has both seen the movie and recognised the machine the watermelon was in so was never able to share my appreciation of the joke with anybody.
For anybody who tries it, make sure any mounted load cell is shielded from aluminum slivers if you crush cans.
Behavioral interviewing has been seized on by HR people as being somehow more valid than any other technique.
It would be more accurate to say any other technique legally available. The use of tests to gauge the performance of prospective employees has a long legal history. In general, tests that are specific to the job have been deemed acceptable but tests of a more general nature are not mostly because of discrimination issues. I suspect the HR people are using the tools available to them rather then picking the ones they might prefer under other circumstances.
I used to deal with these issues a lot when I worked with low level analog design. The input and output circuitry in the audio amplifiers can rectify any amplitude modulated RF that they detect. That includes the output of the cell phone if it uses a modulation that does not have a constant envelope. In the case of FM or a constant envelope modulation the bias point may change in the amplifier but that is not normally a problem or audible. In poor designs it is possible for the amplifier to go into oscillation and even self destruct.
TDMA multiplexes by assigning a time slot for the phone to transmit in and at other times its transmitter is shut down. Turning the transmitter on and off is just another form of amplitude modulation and it is very easy for low frequency circuits to detect it. Systems that use QAM might also cause this problem but I would normally expect the amplitude modulation to be too fast for it to be detected.
Solutions include shielding the input and output leads on the amplifier as well as designing the amplifier to be resistant to this kind of EMI. I have successfully wound RF chokes into the input, output, and power supply leads in the past to make existing equipment more resistant.
I do not have to cherry pick anything. The PARTRIOT act passed with overwhelming support from both parties. The Democrats are saying they would have acted better then the Republicans if they had controlled the White House yet where have they shown themselves any different in Congress? Has there been anything except token resistance?
Both parties are statist and centralization of power at the expense of the Constitution and the Bill of Rights will continue under either one. Picking one or the other merely selects which civil rights will be given up first and not which will be ultimately retained.
None of this is a surprise. Between Duverger's law, Hotelling's law, and plurality voting we get exactly the kind of representation I would expect and we deserve. The differences between the Republicans and Democrats are cosmetic.
Consider the problems we face with campaign finance and corporate corruption in our politics. Normally one would like to only have to bribe the winner of any election but in our system, it only costs twice as much to control everything.
I might have believed this if the Democrats had not voted for the PARTRIOT act as well. 9/11 would still have happened and our response would have been just as poorly conceived.
Why would a patriot attack those things when there are better targets? It is not a contest of damage. Firearms are not used to destroy other weapons.
It is 50% efficiency for a load perfectly matched to the source for maximum power transfer. In power distribution loads are hardly ever matched that way for this very reason.
Excluding reactive losses, transformer losses come from the hysteresis of the core material (basically zero at 60 Hz) and the resistive winding losses.