I havent seen anything that isnt mass producable. Look at current silicon processes. A P4 takes four weeks to get from one side of the fab to the other. No matter how silly the process is if (dirty) capitalist (swines) want to make it in mass they will and no engineer will be spared.
100,000 thinner than a human hair? Can anyone tell me what that is in nm/pm ? Currently we are working on a 1,000,000th the size of a cow process to make our chips.
Ok thats all fine and dandy to say we can now have transistors which will carry on moores law for another x years but there are still physical problems we cannot get roud without rethinking the whole VLSI consept. In future technology it will take several clock cycles to get a signal at a speed of light from one side of the chip to the other. Its impossible to breat that rule. Imagine distributing a clock where the destination is 50 cycles ahead and each clock path has to be accurate to within a 10th of a cycle. Or if one transistor has one atom of impurity it will make a pipeline stage three times slower and basicly make the chip unworkable. The material to make these circuits out of isnt the biggest problem. Even before silicon runs out of steam we will hit a great big technology wall which requires new ways of thinking. I beleve asynchronous logic is the answear but thats just me.
Unforntnately retarding your cpu to the worst possible conditions each time is silly. The P4s look at the temerature and dynamicly slow themselves down to half speed when they need to. This practise is not only ging to get more common but will be expanded and used at finer granularities. Who would buy a P4 if in its worst possible stage, data and enviroment vareables it run at 1G? When you start having clock gating it will only cool down the processor on average executions (pending loops etc.). And thus has no point as the chip would still work at exactly thesame speed as the worst possible scenario with none of the gating being turned on. The next set of high power precessors will have finer temperature detection and will retard only parts of the chip that are going mad. Eather that or async logic will kick in.
Well all very nice dynamicly changing your system frequency by detecting that an area of the chip has been working too hard and had wormed up some what. unfortunately nearly impossible. You cant have probes all over the chip and slow down the whole system because one gets too many operations. Imagine if you started running a 3d game and then your performance drops horrificly because your multiplyer is working too hard and getting hot.
We have been workingb on asynchronous chips which slow down when the chip heats up. The problem with having super high heat producing chips and a great big super high enegry sucking heat sink is that the chip will have hot and cold regions. These hotspots will get hotter as the gradient gets larger. The problem is that clocked design will not be able to cope with a small area of the chip being slow. Anly a very localy generated clock can cope with it and slow down the circuit.
Does anyone have the Atari 2600 schematics and details of its consruction and roms? Every year the third years have to create something as a part of their third year project and its allways something that never gets used anyway. So making all the chips in hardware on an FPGA might be cool.
This stuff sounds very much like Sutherlands stuff he was playing with. Very fine grain asynchronous pipelines with very high throughput. Evans & Sutherland were the people who made the military simulators long long time ago
"HOOVER is a US-registered trademark for floor-polishers, carpet shampooers, vacuum cleaner BAGS, REPAIR of vacuum cleaners, lots of other stuff... but not for vacuum cleaners themselves."
Well the thing is that I want to do asynchronous circuits which you actually have to use strange methods which are silly to describe in VHDL. The world is moving towards languages for needs. So asynchronous designers would use BALSA (asynchronous logic language). Im worning on a method of creating asynchronous circuits from synchronous descriptions like VHDL or schematic but at the end of it all it all gets mapped to a library of gates which is the much easyer to work with.
I open sourced my third year project which was made in schematics and I keep getting emails from people saying things like "I sound the schematics on your website but I cant find the VHDL source code".
That wasn't their point. They just didn't want MIPS to become another Hoover. People call vacuum cleaners hoovers and now hoover have lost their trade mark. Anyone can call their vaccum cleaner a hoover. MIPS are scared that calling a MIPS processor a MIPS (Microprocessor without interlocking pipeline stages) will invalidate their trademark. I had to grep through the report and replace each MIPS with MIPS microprocessor.
When I made my MIPS clone MIPS hot straight on my back sending me many threatening letters. Firstly they wanted to make sure I wasn't breaking any of their IPs. Then they wanted me to place a massive blurb to state I want anything to do with their company. Then they went down to the level of requesting my report of the building of this processor to use mips and a perfect adjective rather than a noun. Each time recommending that it would me much easier if I just gave up and took it off the web.
The whole point of having an FPGA implementation is to allow you to get the latest version of the processor with a patch debug or improvement. Imagine compiling the latest distribution down to your processor and off you go. If you want it to do something special then hack the code. www.opencores.org has many processors allready. I made a MIPS R3000 with a cache and MMU etc with minimal knowledge of hardware design.
I spent a few months cracking ARM 60 CPUs and seeing if I could find the key kept in the memory by observing the power consumption. Using a fast storage scope I could simply hook onto sequences in the program (branches are easily visible) and find the operations on the key. The power measurements told me how many bits in the key were on or off when driving the ALU read bus. As the algorithm was working with bytes it was very easy to find most of the bits of information. From a 32bit (4 billion combinations) key I could get down to about 2000 possibilities. From there its easy to just try them all out. Synchronous processors were very simple to crack. Asynchronous processors didn't have easily visible features like the clock to find the key instructions. They also have temporal shifts so different runs have the instructions executing at different times dependant on the data. From an asynchronous Amulet2e I could only get two or three bits of information (down to 1 billion possibilities).
A piece of news that not many people have noticed recently is that MIPS have settled with Lexra. Lexra is a company producing MIPS compatible chips without a MIPS licence. Lexra have been revealing holes in the MIPS patents in the ongoing court case. As Lexra have been succeeding a little too well and MIPS have simply given up and in order to stop Lexra from revealing that the MIPS 32 architecture is not patent able they have given them a MIPS32 licence. Unfortunately MIPS still have a couple invalid patents to press on people who try to make compatible processors. This is quite annoying personally as I have recently released a MIPS compatible processor (Yellow Star) and have now received letters from MIPS complaining about everything on the web page and threatening legal action even though I haven't broken their invalid patents.
Re:ARM's AMULET....(credit where it's due please)
on
Clockless Chips
·
· Score: 1
I am currently studying in the Amulet group and I can say that yes the group did receave some macrocells from ARM but the CPU was designed by the group. Id like to also point out that there are three Amulet chips. (Amulet 1,2 and 3)
You should look at my PHD research topic. Its about the automatic conversion of sync circuits into async ones. Making them faster, possibly smaller, encrypted and produce less harmonic noise.
It takes a sync design and hyper pipelines it (remember without a clock you dont get a performance loss when hyperpipelining) then passes out an async design. You dont have to worry what data is in which stage in your pipelined design.
You obveousley dont understand asynchronous logic. The point of async is that all communications are safe and there is no clock counting when transmitting data. When you want to transmit you simply communicate and handshake with your destination.
This is so good for communications that many people are looking at GALS (Globaly async locally sync) systems.
Im studying at the university of Manchester (UK) and as my third year project I have reverse engineered a MIPS R3000. I am hoping to release it to the public in open source. It runs on a Xillinx Vertex 300 (3 times smaller than the ARM team) and runs at 50 - 100 Mhz. The whole thing was made from gate level with no VHDL. Have a look if you like at: http://www.cs.man.ac.uk/~brejc8/
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I havent seen anything that isnt mass producable. Look at current silicon processes. A P4 takes four weeks to get from one side of the fab to the other. No matter how silly the process is if (dirty) capitalist (swines) want to make it in mass they will and no engineer will be spared.
100,000 thinner than a human hair? Can anyone tell me what that is in nm/pm ?
Currently we are working on a 1,000,000th the size of a cow process to make our chips.
Ok thats all fine and dandy to say we can now have transistors which will carry on moores law for another x years but there are still physical problems we cannot get roud without rethinking the whole VLSI consept.
In future technology it will take several clock cycles to get a signal at a speed of light from one side of the chip to the other. Its impossible to breat that rule.
Imagine distributing a clock where the destination is 50 cycles ahead and each clock path has to be accurate to within a 10th of a cycle.
Or if one transistor has one atom of impurity it will make a pipeline stage three times slower and basicly make the chip unworkable.
The material to make these circuits out of isnt the biggest problem. Even before silicon runs out of steam we will hit a great big technology wall which requires new ways of thinking.
I beleve asynchronous logic is the answear but thats just me.
Does anyone have more details on what asynchronous logic is in the P4 and why it was funky?
Unforntnately retarding your cpu to the worst possible conditions each time is silly. The P4s look at the temerature and dynamicly slow themselves down to half speed when they need to. This practise is not only ging to get more common but will be expanded and used at finer granularities. Who would buy a P4 if in its worst possible stage, data and enviroment vareables it run at 1G? When you start having clock gating it will only cool down the processor on average executions (pending loops etc.). And thus has no point as the chip would still work at exactly thesame speed as the worst possible scenario with none of the gating being turned on.
The next set of high power precessors will have finer temperature detection and will retard only parts of the chip that are going mad.
Eather that or async logic will kick in.
Well all very nice dynamicly changing your system frequency by detecting that an area of the chip has been working too hard and had wormed up some what. unfortunately nearly impossible. You cant have probes all over the chip and slow down the whole system because one gets too many operations. Imagine if you started running a 3d game and then your performance drops horrificly because your multiplyer is working too hard and getting hot.
We have been workingb on asynchronous chips which slow down when the chip heats up. The problem with having super high heat producing chips and a great big super high enegry sucking heat sink is that the chip will have hot and cold regions. These hotspots will get hotter as the gradient gets larger. The problem is that clocked design will not be able to cope with a small area of the chip being slow. Anly a very localy generated clock can cope with it and slow down the circuit.
Does anyone have the Atari 2600 schematics and details of its consruction and roms? Every year the third years have to create something as a part of their third year project and its allways something that never gets used anyway. So making all the chips in hardware on an FPGA might be cool.
This stuff sounds very much like Sutherlands stuff he was playing with. Very fine grain asynchronous pipelines with very high throughput.
Evans & Sutherland were the people who made the military simulators long long time ago
Instead of typing it in just click
http://www.cs.man.ac.uk/~brejc8/
I might have to get a cleaner power source
http://www.cs.man.ac.uk/~brejc8/rat.html
From: http://www.cni.org/Hforums/cni-copyright/2002-01/0 063.html
... but not for vacuum cleaners themselves."
"HOOVER is a US-registered trademark for floor-polishers,
carpet shampooers, vacuum cleaner BAGS, REPAIR of vacuum cleaners, lots of
other stuff
Well the thing is that I want to do asynchronous circuits which you actually have to use strange methods which are silly to describe in VHDL. The world is moving towards languages for needs. So asynchronous designers would use BALSA (asynchronous logic language). Im worning on a method of creating asynchronous circuits from synchronous descriptions like VHDL or schematic but at the end of it all it all gets mapped to a library of gates which is the much easyer to work with.
I open sourced my third year project which was made in schematics and I keep getting emails from people saying things like "I sound the schematics on your website but I cant find the VHDL source code".
That wasn't their point. They just didn't want MIPS to become another Hoover. People call vacuum cleaners hoovers and now hoover have lost their trade mark. Anyone can call their vaccum cleaner a hoover. MIPS are scared that calling a MIPS processor a MIPS (Microprocessor without interlocking pipeline stages) will invalidate their trademark. I had to grep through the report and replace each MIPS with MIPS microprocessor.
When I made my MIPS clone MIPS hot straight on my back sending me many threatening letters. Firstly they wanted to make sure I wasn't breaking any of their IPs. Then they wanted me to place a massive blurb to state I want anything to do with their company. Then they went down to the level of requesting my report of the building of this processor to use mips and a perfect adjective rather than a noun. Each time recommending that it would me much easier if I just gave up and took it off the web.
The whole point of having an FPGA implementation is to allow you to get the latest version of the processor with a patch debug or improvement. Imagine compiling the latest distribution down to your processor and off you go. If you want it to do something special then hack the code.
www.opencores.org has many processors allready. I made a MIPS R3000 with a cache and MMU etc with minimal knowledge of hardware design.
I spent a few months cracking ARM 60 CPUs and seeing if I could find the key kept in the memory by observing the power consumption. Using a fast storage scope I could simply hook onto sequences in the program (branches are easily visible) and find the operations on the key. The power measurements told me how many bits in the key were on or off when driving the ALU read bus. As the algorithm was working with bytes it was very easy to find most of the bits of information. From a 32bit (4 billion combinations) key I could get down to about 2000 possibilities. From there its easy to just try them all out. Synchronous processors were very simple to crack. Asynchronous processors didn't have easily visible features like the clock to find the key instructions. They also have temporal shifts so different runs have the instructions executing at different times dependant on the data. From an asynchronous Amulet2e I could only get two or three bits of information (down to 1 billion possibilities).
A piece of news that not many people have noticed recently is that MIPS have settled with Lexra.
Lexra is a company producing MIPS compatible chips without a MIPS licence. Lexra have been revealing holes in the MIPS patents in the ongoing court case. As Lexra have been succeeding a little too well and MIPS have simply given up and in order to stop Lexra from revealing that the MIPS 32 architecture is not patent able they have given them a MIPS32 licence.
Unfortunately MIPS still have a couple invalid patents to press on people who try to make compatible processors.
This is quite annoying personally as I have recently released a MIPS compatible processor (Yellow Star) and have now received letters from MIPS complaining about everything on the web page and threatening legal action even though I haven't broken their invalid patents.
I am currently studying in the Amulet group and I can say that yes the group did receave some macrocells from ARM but the CPU was designed by the group. Id like to also point out that there are three Amulet chips. (Amulet 1,2 and 3)
You should look at my PHD research topic. Its about the automatic conversion of sync circuits into async ones. Making them faster, possibly smaller, encrypted and produce less harmonic noise.
It takes a sync design and hyper pipelines it (remember without a clock you dont get a performance loss when hyperpipelining) then passes out an async design. You dont have to worry what data is in which stage in your pipelined design.
You obveousley dont understand asynchronous logic. The point of async is that all communications are safe and there is no clock counting when transmitting data. When you want to transmit you simply communicate and handshake with your destination.
This is so good for communications that many people are looking at GALS (Globaly async locally sync) systems.
Im studying at the university of Manchester (UK) and as my third year project I have reverse engineered a MIPS R3000. I am hoping to release it to the public in open source. It runs on a Xillinx Vertex 300 (3 times smaller than the ARM team) and runs at 50 - 100 Mhz. The whole thing was made from gate level with no VHDL. Have a look if you like at: http://www.cs.man.ac.uk/~brejc8/
The story is at http://www.theregister.co.uk/content/1/14405.html
I used it today but now its gone just when i was about to show it off to my friends