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Clockless Chips
iarkin writes "TechReview is running a very interesting
article about clockless chips.
Clockless, or asynchronous, chips work very much faster and consume less power than their synchronous equivalents (Intel hade some experiments on these chips back in -97, the results showed that the asynchronous chips were three times faster and consumed only half the power)."
can you imagine a beowulf cluster of those!
The One Rule Of Chess You'll Ever Need: Don't play someone who carries a kit in their bookbag.
.. otherwise people would've noticed this has been
posted before (sept 15)
If chips were clockless, I'm sure that Intel and the various PeeCee manufacturers would have to re-think their marketing strategies.
(It was nice to see AMD trying to break away).
Clockless chips will never take off. How are people supposed to draw incorrect conclusions about which chip is the fastest when there's no MHz/GHz rating?
If they are faster consume a lot less power that would make them great for laptops. The only complaint I have with my laptop is battery life. Any idea of how long before this technology might be available?
FearLinux.com
This concept is will be very hard to market to the consumer. With out a definitive way to give a chip a speed classification consumers won't know what is better or worse. The way I understand it if you give it more power it goes faster, thats on some clockless chips. So I guess that could be the speed classification number.
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In other news, AMD abandons all current R&D to work on clockless chips so they can win the clock-speed wars against Intel...
There is no escape from The Muffin.
If there is no clock, how do they know that they are 3 times faster? :-D
This was already posted about a week ago. People keep bringing up the same topics over and over.
I just visited CalTech, they have some exciting research about asynchronous chips coming along.
This is gonna be bad for business I tell you ...
"A door is what a dog is perpetually on the wrong side of" - Ogden Nash
Measure processor speed in MIPS instead of MHz, after all, a processor that can execute 10 million instructions per second should be faster than a processor that execute 1 million instructions per second. -- The blue-eyed programmer-cat >^..^
It wouldn't be that bad. The industry would just get away from numbers, and move to something like many software makers are doing today.
In place of a 2Ghz Pentium IV we will be seeing an Axium Gold.
It will take a little getting used to, but we'll get over it. Ford doesn't call their cars Model A's or Model T's anymore!
97, the results showed that the asynchronous chips were three times faster and consumed only half the power
so....the reason they weren't used is because....of....what else....
$$$$$
(from marketing mhZ!)
-k.
I need a TiVo for my car. Pause live traffic now.
They can just use things like millions of instructions per second (MIPS). That would at least be as meaningful as clock speed anyway, as far as benchmarking and what not.
"It's comin' back around again..." -RATM
An asyncronos chip will hit the highest speed automatically. An better cooler will acelerate your PC without adjusting any settings. Or if you just want a silent pc it wouldn't need a fan, it will just work slower.
But I don't really think that chips that are completly asyncronos could be successfull, but there is a good possiblity that we will see hybrid chips with asyncronos and syncronos parts. Imagine a CPU with a fixed FSB but a asyncronos ALU.
Jan
When technology such as this exists why do companies not develop with it? Do they feel that they should save it down the road? No! Dont! Your slowing the progress of humanity. Imagine a chip six times faster then today's chips running at the same power for the same price? 12ghz! Imagine the computational power that would be available using the same resources we have today. Why waste the future companies, go with inovation, in this case it would of been worth it!
AJ
-------
artlu.net
Seems like there was a story about this earlier...
Hmm.
Oh! Here it is:
Clockless Computing: The State Of The Art by timothy with 140 comments on 01-09-15 6:26
Love,
Ahem.
Not A Sig
Async processing is a very old idea. The problem is that designing the logic for it is a far greater chore than for regular chips. CPU designers are simply not good enough to do it well yet.
Marketing just has to play up the clockless thing like it's the best ever. "Gigahertz, Schmigahertz"... "So fast it doesn't even need a clock"... etc.
---If you can't trust a nerd, who can you trust?
If there are no numbers to prove it?
"How Sun swerved to avoid Rambus"
http://www.theregister.co.uk/content/3/22279.html
More details on the CPU:
http://www.theregister.co.uk/content/3/22274.html
Sun press release:
Extends UltraSPARC III Chip Family Tree--First Use of Sun-Developed Asynchronous Logic Design in Chip's Memory Interface
At Sun Labs:
feature article
async research home page
I took the clock out of my computer with an xacto knife. I immediately noticed an infinite difference in the speed at which it ran.
I also have an asynchronous clock ever since the spring in my wristwatch snapped.
People have spent the past twenty plus years designing development tools for synchronous design. There's just a lot less groundwork covered for asychronous design because no one has spent the millions of dollars to create a (mostly) new tool chain.
Intel has never produced, nor have they discussed at any ISSCC or HotCHips forum a plan for an asynchronous design.
Unless you can provide me with more detail, I think that statment is wrong.
https://www.accountkiller.com/removal-requested
Clockless chips would result, perhaps, in the most interesting (funny?) marketing.
Intel would develop a standard way of indicating performance. Based on something their particular chips are good at. We'll say they release the Pentium Clockless 1000, Pentium Clockless 2000 and Pentium Clockless 3000.
AMD would, if trends indicate anything, market them using performance ratings. Instead of deciding performance based on the intel standard, they would have new names to indicate that their processors, in some situations, are faster than their Intel counterparts. They'd probably be called the AMD Athlon Clockless XP 1100+, and so on.
In response, Intel would start releasing worse processors, but with higher numbers. Pentium Clockless II 5000 would be their flagship.
AMD would continue making their processors in the traditional manner, but would adopt a new naming mechanism. AMD Ahtlon Clockless Performance XP Super Fantastic 6000, maybe.
Repeat ad nauseum.
-NeoTomba
It is muy hard to design a chip without a clock. Speed gains would probably be offset by the time it would take to design the chip, given the rate which clock speeds advance.
The main problem with async. design is the asycnchronous part of it. In a typical computer, you have tons of parts that you use interchangably. These parts have operate at different speeds. How would two devices working at different speeds operate smoothly. Generally, this is very hard. But the thing is they can: But the devices themselves need to agree on a few things. But async. design is higly complicated because in a clockless environment you have to pretty much garauntee something like "I'll do this within 2 equivalent clock cycle." or have other types of signalling negotiation. You can't clock on a "clock" to do stuff. You have to clock on a "async" signal.
This is the problem in the large. When you go down to the chip level, there are tons of nightmares. There can be feedback loops causing race conditions that only occur at certain times. There are load problems that might increase complexity so much more than equivalent problems in a clocked design. Clocked design makes things a lot simpler and still designing a chip is extremely diffucult.
But the future I don't think is in clockless design, but "careful clock" design. For example, there are chips which are smart enough to disable sending the clock to certain part of a chip when it knows those parts will never be used. That saves a lot of power. There are chips which aim to spread the clock around carefully thus increasing the speed. And remember, almost 50% of the power in a chip is lost due to the wiring!
me.
...chips work very much faster...
...Intel hade some experiments...
Unfortunately, these chips only seem to have half the spell-check and grammar-check capability.
As I understand it, traditional systems use a clock signal to let each stage of the pipeline know when the previous stage has completed. Each stage is designed to have few enough transisters that a signal has to pass through to guarantee that it will be done by the time the next clock signal arrives. Clockless systems instead design the processor such that at each step in the processing, the difference between a partial result and a completed result is self-evident. This requires more work, both in the design of the processor and in terms of transisters, but at the benefit of eliminating the clock (and many associated transisters) and any waiting between when the processor has completed a step and when the clock signal arrives.
Since dealing with the clock signal has become increasingly complex, instead dealing with not having one is becoming a more reasonable solution.
if that's the case, i'll never have to worry about my state machine taking an extra delay going from one state to the other...
or the problems with single extra delays when synchronizing blocks between requests and acknowledges...
reminds me of the ease of doing everything in software...
obviously it would be interesting in how things would be done on the synthesis side of things...
there will always be blocks that will have clocks especially in the registers as such. blocks that are so called asynchronous maybe called that if the triggering line may not be the clock line, but it's still sensitive to something else.
ie, you may have a d flip flop which would latch out its data on the enable "event" (which is attached to the clk line)
it's easy to say "oh we'll have our complete design asynchronous" but complete design? until someone show us one first... it's pretty difficult. and it's nothing revolutionary here....
my blog
The article mentions the year -97. Perhaps this is a typo, but I kind of like the idea of using negative years for those before 2000 so that you'd subtract 2000 from a year, but that would make 1997 be year -3 not -97.
--Ben
"You cannot increase the clock speed, for that is impossible. You must first realize, there is not clock."
-- Funky bald kid holding a processor and talking to Neo.
Slashdot is SO behind. Kuro5hin had a story about this back in -96, right after the tests were done! Leave it to /. to wait 2,098 years to post a story. Sheesh.
"Destroy science and religion. Science would re-emerge exactly the same; but not religion." - Penn Jillette, paraphrased
The truth?
There is no clock.
Wind it too hard and it runs three times as fast and consumes less power!
Intel tried this, and created a chip that was Pentium compatible, but ran three times faster than conventional processors, consuming half the power. It never made it out of the labs, though.
Now, imagine such a processor made today, and marketed towards geeks! It'll be the cool thing to have.
The IBM Power4 architecture uses a "Wavepipelined" interconnect bus. This is a clockless bus. I believe the Alpha 21384 was going to use this as well.
r dw are/datactr/p690.html
Too bad IBM won't sell the chips. They only sell the servers. Each die has 170 million transistors with 2 microprocessors per die! They package 4 dies in one package totaling 710 million transistors.
It kicks the snot out of anything Intel or AMD has.
Initial benchmarks show the SPECINT2000 and
SPECFP2000 at 808 and 1169 are comfortably ahead of the competition (2GHz Pentium IV was the SPECINT leader at 656, while Alpha 21264 @833MHz was SPECFP leader at 777).
Anybody have $450,000 to spare?
http://www-1.ibm.com/servers/eserver/pseries/ha
Oh, well. It's not a problem for me, since I use an industry-standard browser. Why people want to waste their time with stuff that doesn't work is beyond me. Anyone who thinks their browser is better than the current MSIE product generation is deluded and can safely be ignored. (Which is what seems to be happening to you.)
http://slashdot.org/article.pl?sid=01/09/15/133235 &mode=thread
May I suggest you read the - as 19, as does the rest of us.
Internet Exlorer
A new browser? I think not. Just another example of the benefits of a Liberal Arts education... (if you could call it that).
I would have thought Theatre majors could manage to spell correctly.... Or is this maybe the Shakespearean spelling? Some sort of in-period thing?
-- Mal: "Well they tell you: never hit a man with a closed fist. But it is, on occasion, hilarious."
Chips are sold like CD-Roms. So a 500mhz would be a 100 and a 750 would be a 150 and a 1 ghz would be a 200. There would have to be some sort of standard measuring which calculated amount of data processed, but after that it would make it simple to decided if you should upgrade. Hmm I can go from a 200 to a 204. Not worth 300 dollars.
So we could have the IBM linux watch made with clockless chips :-)
--
Chuchi
Chuchi
Just test how fast Photoshop filters take to run. :) "It's as fast as a stupercomputer!"
Or more likely Intel (by then the only CPU company left of course) will start binning by actualy performance - look for "runs Win 95 fast enough", "runs NT fast enough" and the expensive "runs XP a bit" speed grades
I can't wait to see all of the timing errors that will pop up in software due to this. The defect reports due to race conditions alone will fill up Gigs of storage. Not to mention that systems will be as individual as fingerprints! Hours of debugging fun!!!
That is all.
It's a little known fact that "Ontological Argument" was in fact a much loved part of that medieval panel game "I'm Sorry I Haven't A Creed" which was billed as "the antidote to ecumenical councils, in which four Church Fathers are given silly things to do by the chairman, Gerbert of Aurillac". In the "Ontological Argument" round, each contestant in turn would say something gnomic like "God is that than which there is no greater" or "existence is more perfect than non-existence" until at some point one of them would say "And thus God exists!", at which point the audience would cheer and clap and the round would be over. Supposedly "variations" of the game existed, with unexplained extra rules such as reverse traddling or pillar saints being wild.
Another popular round was "Chain of Causation" (for some reason known as "Cheddar Gorge" in England). This would start with the chairman naming some everyday commonplace such as a turnip or the Black Death, then the first contestant would name something else supposed to have caused it, the second contestant would name something supposed to have caused the first contestant's cause, and so on, with the contestants trying to avoid naming anything which was near enough to a deity or Supreme Being to be deemed the First Cause. When one made that mistake (or the chairman got bored) a hooter would sound and the round was over. There was an especially fine version of it done in Rheims cathedral when the Blessed St Willy managed to say "chasuble" in a silly voice as his cause on three successive turns.
There was also "Limericks" where the chairman would supply an initial line such as "When St Antony was walking his pig" and the four contestants had to supply a line each to produce a limerick which was humorous but not heretical.
Other typical rounds were "One Gregorian Chant to the tune of another", "Letters to the Corinthians (expurgated version)" and pairs of contestants playing well known folk airs on shawm and sackbut, or singing alternate words of hymns. It usually ended with the names of late arrivals to a theological convocation.
At some point in most games the chairman would say "I'll be handing out penances, because penances mean pardons. What do penances mean?" and the audience would shout back "Pardons", at which point the chairman would mutter in an exasperated fashion about cloth-eared audiences.
The show was finally cancelled by the Puritans, who didn't hold with people enjoying themselves. Such a shame we have nothing like it today.
Oh well
I wish there was a fscking blue pill
Fant additionally proposes replacing the conventional system of digital logic with what he calls "null convention logic," a scheme that identifies not only "yes" and "no," but also "no answer yet"
This brings to mind the Ternary Computing article back in October.
There are 10 types of people in this world, those who can count in binary and those who can't.
Of course I'm used to things getting published a little late on slashdot ;-)
M0571y H@rml355.
that don't make sense: (from the article)
A chip without a clock would be about as useful as a page of text without any space between the letters
Actually, it's about as useful as a page of text that only exists when you have your eyes closed.
by George Lucas in determining the wold wide release dates for AOTC.
alot has been done on clockless
what it requires is a great understanding and stringent design
these are the reason why intel did IA64 non specultive
have a look at IBM's report in IA64 in the microprocessor report (they give good reasons why its doomed however clever people think it is)
amulet spun out of manchester and a stanford spin out company also started up
not exactly new new thing
only can be done in small teams with very trained people
but hey they got a clockless ARM running a long time ago
regards
john jones
we saw this article sept 15.
If you read the article there's quite a bit of reference to various internal Intel projects. Maybe Intel just doesn't publicize every internal project they work on.
I think interdata made/sold a relatively large number of async computers back in the 1970's.
Treatment, not tyranny. End the drug war and free our American POWs.
See my user info for links.
This article was in wired magazine last month and has been posted like 80 other places since then.
OLD NEWS!
It's not the OS it's the user that sucks. If it's user friendly, you get stupider people. - clinko
Example:
But after a point, cranking up the clock speed becomes an exercise in diminishing returns. That's why a one-gigahertz chip doesn't run twice as fast as a 500-megahertz chip.
She doesnt realize that it's not the size of your clock that matters but how you use it.
To support that claim I give you the common misnomer that the famous Intel with his huge 1Ghz clock can outperform the lesser known Sun with a 450 Mhz clock.
Yes I could mention bus speed, or instructions per cycle etc.. but that wouldn't be funny now would it?
I think you underestimate just how much I just dont care.
this is blank like the space in between a set containing nothing.
some very much faster brain so I could score higher than -97 on my exams.
Sure, in theory they are possible, and tests have been done on some types of circuit.. but to claim 'asynchronous chips are smaller, take less power, and are 3x faster' is kind of silly.. if this is the case, where are the chips?
some intel guys were at async 2000. They mentioned the fetch/decode logic in the p4 was async.
I confess to being somewhat skeptical about claims that Intel developed an asynchronous Pentium that ran three times faster than its clocked cousins and on half the power. Why, pray tell, would such a thing not have gone straight to market?
Asynchronous design is aimed at low power applications, not high speeds. Asynchronous design is more energy efficient because state only changes when necessary, rather than on every clock tick. The cost of this is something like a three-fold increase in the on-chip logic to arrange for all the handshaking signals used between logic blocks to indicate that results are available for the next processing stage. This extra logic costs both in terms of silicon real estate (i.e. you have less room for on-chip cache) and in processing time (there are more gate delays between each processing stage).
Synchronous design is fast (a) because you set your clock rate as high as possible, limited by the longest gate delay in the circuit, and (b) because you can use all that extra silicon for cache which saves you from really taking it in the pants when you have to go to off-chip memory. One way of raising the clock speed (if that's your goal) is to reduce the gate delay for each processing stage, hence the longer pipelines of simpler stages as seen in the Pentium IV.
There is a problem of distributing a clock signal over the entire surface of a chip (capacitance effects come into play), so I am prepared to believe that there may be room for asynchronous interfaces between the larger logic blocks on a chip, but otherwise I very much doubt that largely asynchronous design as practised today will outperform clocked logic.
It's too bad to see such an interesting subject butchered by someone so lacking in technical knowledge. The entire article felt like a compilation of Comdex marketing brochures. Check this out:
From that first choice came the steamroller effect of Moore's Law, wherein nearly all research, development and production in the semiconductor industry has focused on clocked chips
Yeah, that made sense... Maybe she was thinking of "Murphy's Law"
Anyone remember this article?
Looks suspiciously similar to me.
I was really surprised to see this article here seeing as Open Source magazine featured an extensive article on this subject...a year ago! And MIT's Technology Review did it two months ago. Clockless technology is a marvelous concept that will take forever and a day to catch on because it simply isn't economical for anyone at this point...maybe one day though...since people's need for power and speed to continues to grow. It's the age old question of who has the biggest, uhm stuff, only we're dealing with who can put out the fastest chip first...when will companies begin to put the drive of the market and the needs of their consumers before their own desire to have the "bestest" products now?
"that which does not kill me makes me bitter" -anon
Since Transmeta is already a bit off the deep end and is known for energy-saving Intel compatible CPU's it seems to me it'd be good for them to partner with one of these async companies and work on a chip that incorporates both their ideas. Because Transmeta CPU's use less hardware they'd seem to me to be easier to reimplement in this manner and because of their code morphing concept they can still be Intel compat. Because of both the code morphing and the async design they'd run with less energy and less heat and because of the async design they'd be faster than Intel. (well even if it took long enough to get to market they'd still be pretty fast.. and very good for rack mounted machines and laptops)
At what price learning? At what cost wisdom? The price is a man's peace of mind, and the cost is his life.
to arrogant to admit they don't know what clockless/asynchronous circuits are. Which is very obvious from the lame but humorous replies on why it's not done.
The real problem is making sure your logic is sounds. Asynchronous chips need super great timing tests much more testing is needed than for a synchronous. The fact is you are now dealing completely with the delays of EVERYTHING in the circuit. The calculation of delays can screw everything up. Current cad tools need to be updated greatly. Our chips today are so complex than making something similar that works in asynchronous circuit would be immensly hard as the cad tools havent been developed w/ async in mind.
Why isn't Apple in this game. They already lost the clock speed war, and aren't RISC chips suppose to be simpler?
Clockless cpus...
This is an intresting concept, mainly becuase syncing when you read from other devices and when you write becomes somewhat, let's say, interesting. Normally, as your cpu works, it runs on a signal going on and off (the clock) to make sure that data has a chance to stabalize before you use it. Infact, when I worked with chips like the serdes, I would have to set all my processing 180 degreese out of phase with the clock to ensure good data.
I would like to know how this will affect optical networks if put into use, as it might be possible to get incorrect data, if the light stream cuts off half way through the sampling time. It seems to me, that playing without clocks, though may be faster and better for power usage, is playing without a safety net. I just don't want to be on the computer that falls.
The other real obstical to this, I see, is designing all the rest of the hardware to operate without clocks, so that that the ram works in sync with the cpu.
Like I said, I don't want the cpu that doesn't know if the data is stable yet, (as with all chips there is a period of time where data fluxuates, as a result of the transistor getting a charge.)
=================
Unix is very user friendly, it's just picky about who its friends are.
There are some compelling reasons:
Though synchronous design has enabled great strides to be taken in the design and performance of computers, there is evidence that it is beginning to hit some fundamental limitations. A circuit can only operate synchronously if all parts of it see the clock at the same time, at least to a reasonable approximation. However clocks are electrical signals, and when they propagate down wires they are subject to the same delays as other signals. If the delay to particular part of the circuit takes a significant part of a clock cycle-time, that part of the circuit cannot be viewed as being in step with other parts.
For some time now it has been difficult to sustain the synchronous framework from chip to chip at maximum clock rates. On-chip phase-locked loops help compensate for chip-to-chip tolerances, but above about 50MHz even this isn't enough.
Building the complete CPU on a single chip avoids inter-chip skew, as the highest clock rates are only used for processor-MMU-cache transactions. However, even on a single chip, clock skew is becoming a problem. High-performance processors must dedicate increasing proportions of their silicon area to the clock drivers to achieve acceptable skew, and clearly there is a limit to how much further this proportion can increase. Electrical signals travel on chips at a fraction of the speed of light; as the tracks get thinner, the chips get bigger and the clocks get faster, the skew problem gets worse. Perhaps the clock could be injected optically to avoid the wire delays, but the signals which are issued as a result of the clock still have to propagate along wires in time for the next pulse, so a similar problem remains.
Even more urgent than the physical limitation of clock distribution is the problem of heat. CMOS is a good technology for low power as gates only dissipate energy when they are switching. Normally this should correspond to the gate doing useful work, but unfortunately in a synchronous circuit this is not always the case. Many gates switch because they are connected to the clock, not because they have new inputs to process. The biggest gate of all is the clock driver, and it must switch all the time to provide the timing reference even if only a small part of the chip has anything useful to do. Often it will switch when none of the chip has anything to do, because stopping and starting a high-speed clock is not easy.
Early CMOS devices were very low power, but as process rules have shrunk CMOS has become faster and denser, and today's high-performance CMOS processors can dissipate 20 or 30 watts. Furthermore there is evidence that the trend towards higher power will continue. Process rules have at least another order of magnitude to shrink, leading directly to two orders of magnitude increase in dissipation for a maximum performance chip. (The power for a given function and performance is reduced by process shrinking, but the smaller capacitances allow the clock rate to increase. A typical function therefore delivers more performance at the same power. However you can get more functions onto a single chip, so the total chip power goes up.) Whilst a reduction in the power supply voltage helps reduce the dissipation (by a factor of 3 for 3 Volt operation and a factor of 6 for 2 Volt operation, relative to a 5 Volt norm in both cases), the end result is still a chip with an increasing thermal problem. Processors which dissipate several hundred watts are clearly no use in battery powered equipment, and even on the desktop they impose difficulties because they require water cooling or similar costly heat-removal technology.
As feature sizes reduce and chips encompass more functionality it is likely that the average proportion of the chip which is doing something useful at any time will shrink. Therefore the global clock is becoming increasingly inefficient.
Maybe if they watched what they ate and dressed better they would get some action.
Clockless, or asynchronous, chips work very much faster and consume less power than their synchronous equivalents...
Well, yeah! Look at any electronics book where they have an ALU (Arithmetic Logic Unit). You can perform whatever integer operations the unit supports in almost no time flat. It all works with so-called logic gates that are cleverly arranged in the unit. There is no need for a clock. You just spill the bits on one end of the thing and the results come flying out the other side after whatever the thing's propogation delay is. Which isn't very long. (I don't have a reference book handy right now so I can't tell you exactly.) Oh yeah, and this "technology" has been around since the invention of the transistor.
So why do we need a clock in a microprocessor? Because there are a zillion other operations going on, and it's really hard to make a system as complicated as a computer (millions of transistors, eh?) that operates asynchronously without messing things up. (With that much circuitry, it's a miracle the things work at all.) So they put a clock on the thing. The real arithmetic still happens in no time flat, but then it sits there waiting for the clock pulse to come around and allow the results through. It's really amazing shit. And I don't even know jack about 'lectronics.
But I was going to say something, and I forgot what it was. Oh well. Maybe I'll remember later. I really hate when that happens though. Oh well.
Try it for yourself and see.
People have spent the past twenty plus years designing development tools for synchronous design. There's just a lot less groundwork covered for asychronous design because no one has spent the millions of dollars to create a (mostly) new tool chain.
Ditto tools for chip testing.
Chip testing of synchronous designs is easy, and there are automated tools to do it.
The common ones are based on fullscan or partial scan: You add a mux to each flop and use a test signal to string them into one or more shift registers. Pop into test mode, shift out the old state for examination and shift in a new state for the next steps of the test.
You can change the function of the pins on the chip to shift out a bunch of little chains quickly, or use one or a few long chains and shift through the JTAG port (which is really intended for "boundary scan", where you switch the pin drivers into a simialr scan mode controlled by the 4- or 5-pin JTAG port, and toss signals from chip to chip to see if all the chips got soldered onto the board correctly).
Scan works well on synchronous designs, where all the flops in each of several "clock domains" are clocked by a common signal. But in asynchronous designs, where each clock may be clocked by an arbitrary signal, this falls apart.
There IS a methodology - complete with automatic test program tools - that can test asynchronous designs as easily as synchronous. It's called the "Cross-Check Array". But it was never widely deployed in the United States and the company that did it has since been merged into another and by now may be gone. As far as I know, only Sony (which got an unlimited license as part of investing in Cross Check when it was a startup) is the only big user of it these days.
Bantam Dominique roosters crow a four-note song. Once you've heard it as "Happy BIRTHday" you can't NOT hear it that way
Correct me if I'm wrong: wouldn't a clockless chip have to be completely redesigned to see a speed increase in it?
So I ask: ok, 3 times faster, but 3 times faster than what?
Still, if it runs at whatever speed it can, I suppose it'll speed up automatically when I cool it, and slow down when it overheats. Wonder if this will eliminate burnt-out chips... riskless overclocking for the masses. Maybe I should buy shares in heatsink/fan manufacturers :-)
This is also going to make consistent benchmarking a thing of the past. You'll never get the same run twice on the same chip, let alone different chips in different environments.
Why would anyone engrave "Elbereth"?
Asynchronous hardware design is very, very difficult - Lots of pitfalls with static and dynamic hazards, to the extent that they beat the idea into of you in school that any asynchronous design was a bad idea.
But I always believed that asynchronous design was the logical way to go - all you needed was enough computing power to resolve all of the various hazard and glitch issues. It makes sense for information to travel as fast as it can, instead of as fast as the system clock will allow.
Processors will be qualified in terms of benchmark performance, instead of MHz, which is a dubious benchmark anyway. I think the marketing guys will have to get creative though...
My rights don't need management.
....that contain the words "overclock", "oc", etc., etc. etc,.... D: They'll end up like VooDoo Extreme... having barely anything to do with what they were originally started for..
I tried to respond to this post today with a meaningful message, and couldn't post it.
Earlier when I tried to read articles within threads, I got bounced back to the front page.
I'm tired of getting modded down by lamers who can't run a web site.
... and only a few dozen design engineers were institutionalized during the design process
---
Of the five but's you used, only one wasn't used to start a sentence.
How are the chips supposed to tell the time now?
this has been posted http://slashdot.org/article.pl?sid=01/09/15/133235 &mode=thread before even reference the same freekin article good job
This must be Thursday, I never could get the hang of Thursdays.
90% of the posts here are "hey, this will make for some interesting marketing" or some other BS. Listen fools: async chips are VERY hard to design and there are tons of pit traps along the way. For one, how are you going to execute your "add Rm,Rn,Ro" instruction?? Just feed Rn and Ro through the ALU and then load the result into Rm, right?? But wait, HOW THE FUCK DO YOU KNOW WHEN THE ADDITION HAD GONE THROUGH THE ALU??
A clock just makes sense. I'm sure you can think of a way to get around this problem, and for the bargain price of only two million transistors!! And add another two million for the other thousand+ write/read conditions and you have a BIG, SLOW, HOT pile of junk. This article is totally biased, the author just took what these async startup guys said and wrote it down. The async startup CEO says his chips are 3x faster than Intel's?? I'M SHOCKED!! Oh, but why can't I buy these on the market??
This isn't news for nerds, it's news for morons. Let's all try and be funny and stuff because we all have no clue about technology and reality. Just plug me up with karma. Yeah, fill me up baby, plug me harder, oh yeah.
"Let's post a bunch of techno nonsense, I'm sure it'll get me karma because moderators don't know any better."
...I knew ive seen that guys ugly mug somewhere before, OH YEAH, it was a slashdot story like a month ago...weird
What if your processor could run every possible calculation at once by occupying every moment of time simultaneously? You could find every prime number in what appeared to be a mere instant! Quantum Processing can do it. The only flaw is that Scott Bakula would probably appear on your monitor for an hour every few years, but that would be okay.
Leveling up builds character.
It's not like Intel said "Well gee, we're making good enough money off of this clocked chip so we'll stick with it."
The idea was that sure.... your clockless chip might be 3 times faster today but by the time you develop testing tools, get production costs down, ramp up for production, etc... your 3x speed advantage is no more. Now the clocked chips have passed you.
So really, the issue is the three times in an expiremental chip isn't a big enough advantage to start really producing with. By the time you get to market, you'd be behind again. They need to get something with a bigger advantage.
The problem with not being a karma whore is that you don't get karma points.
And much as I think the project is very cool the fact that many PDAs use StrongARMs and not Amulets tells a story.
From the site:
The power/performance qualities of AMULET were sufficiently encouraging to continue the line of investigation. As the performance of AMULET2 still lagged that of contemporary synchronous devices the next task was to improve the MIPS rate, without sacrificing excess power. This has been addressed by AMULET3i. This macrocell can deliver over 100 MIPS on a 0.35m commodity process - and the processor core is capable of more in the future. The first AMULET3i application is the DRACO DECT radio controller. However AMULET3 based systems will be developed for other application area; we're particularly interested in contactless smart cards for reasons which will gradually be made apparent.
100 MIPS - imagine that!
Don't get me wrong - I still think that the asynch idea is cool, but I don't think that Clockless, or asynchronous, chips work very much faster ... than their synchronous equivalents
DWR is Ajax for Java
The two concepts are different.
First, low consumption is about not putting power into inactive units. A known (and used) way of doing low consumption is to cut the clock going into inactive units, which is completely synchronous design.
Second, asynchronous circuit design is, if I'm not very mistaken, about using (correctly) a wire twice in a clock cycle, much the same as you use statements in a loop. Very hard problem, BTW.
If you happen to know good papers on async design, point me to them, please.
The only *real* benchmark, of course, is Bogomips! ;-)
Ahhh...the great dumpster continuum. Many a free computer will be found there. -- sowth (748135)
Any man distinguishable from God is not sufficiently
advanced.
What are we looking for? An easier way to sell things, or a way of improving the performance and speed of the computer? Just find a new way of rating the speed!
This change in input creates instability in the system, as all logic elements affected by the input change undergo state transitions. If the resulting stable state at the output end of the logic block is the same no matter what, it's a noncritical race. However, in some cases the output can settle in different stable states depending on the order of the flipflop state transitions within the circuit. This is called a critical race, and it is a bad thing.
Critical races mean we can't predict what the output of a circuit will be given an initial state and an input value. Therefore, the circuit is worthless.
sigs are for suckers
The article fails to note the existence of the Philco 2000, a commercial asynchronous computer available in the early 1960's.
http://ed-thelen.org/comp-hist/BRL61-p.html
"The program section has asynchronous logic which means that each operation within each instruction starts as soon as the preceding operation is campleted."
Whenever the question of asynchronous chip design comes up, everyone points out the Intel work in '97, but nobody mentions the work done by the AMULET group in Manchester. Set up in 1990 they produced the world's first asynchronous chip in 1994, based on the ARM chipset. By the time Intel got their act in order, the second generation AMULET2e had arrived, providing higher performance than a synchronous ARM chip for the same power input.
++ Say to Elrond "Hello.".
Elrond says "No.". Elrond gives you some lunch.
that the speed of a clockless chip increases as the power increases, so for benchmarking purposes, if a chip fell behind a comparible clocked chip, all one has to do is increase the voltage to perform more work/instructions. Of coarse there is probably a limit to how much voltage the pathways and transistors will be able to take, but its a novel idea for overclockers, eg. I got mine up to 12.5356 volts while yours only got to 12.2872.
I will bend your mind with my spoon
Johnniac, the famous early computer, operated asynchronously. A group of former SDC employees reminisced about the machine (in front of it, no less). When someone asked about clock speed, they said there wasn't one; completion of instructions triggered a completion signal. Glad I didn't have to debug the hardware...
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The clearance system sounds logical. It is not. It is completely arbitrary. -- John Bolton