If you keep your money in a bank, it doesn't just sit there. The bank lends it out to other people or businesses - so leaving it in a bank isn't so detrimental to society. If you are unwilling to spend it, the bank will spend it on your behalf - while paying you an interest rate for the privilege.
Here we have "Why should we release this chip now?
Because if you don't release a better chip, who will upgrade and give you more money?
The old chips are MORE expensive to produce. The 65-nm die size is about 140mm^2 and the newer 45-nm die size is about 107mm^2, so actually, the next generation chip is cheaper to make.
In the absence of AMD, Intel would still have to compete with itself, otherwise nobody would upgrade and sales would tank.
I'd be surprised if the Core-2 didn't outperform on something as integer-intensive as a kernel compile with 64 bits or 32 bits for the reasons outlined in my previous post. The microarchitecture simply gets a higher IPC.
For clues on compiler performance, you can look at the "gcc" component of the SPEC benchmark. I believe the benchmark is gcc compiling itself - but it's been a while since I've looked at it.
Now if you have a large budget and compile times are an issue, I'd invest in a compile-farm and use distcc:)
Core2 smokes the AMD64 in integer performance. See SPECint scores at www.spec.org
This is intuitive because the Core2 is wider than the Opteron - which translates into more IPC.
It has a 4 wide issue, wider fetch bandwidth, instruction fusion which makes it effectively even wider than 4, deeper reorder buffers, out-of-order load/stores, hardware prefetching into the L1 cache. I could go on and on. The performance speaks for itself. Oh and the process lead (65nm Intel vs 90nm AMD) means Intel can give you double the cache in the same amount of area. Also, the entire cache can be used by a single core, instead of the hard-partitioned AMD design.
All of this means that the fastest Core2 is 50% faster than the fastest Opteron on SPECint. You simply cannot buy a faster integer machine.
I would suggest using ICC instead of GCC if you want performance out of either Intel or AMD. Frankly, gcc isn't going to get you anywhere near icc.
It's not just SSE performance where the Core-2 shines. It's also integer. The fastest Core-2 SPECint is 50% faster than the fastest AMD SPECint. ICC was used. This makes sense because the core-2 is a 4-wide issue with instruction-fusion (which makes it look effectively even wider) - wheras the Opteron is only 3-wide issue.
It makes very little sense that the Opteron would outperform on integer code.
I don't get it.
C = di/* should be doable without branch by just bit masking and shifting */
C = C * A
C = C + 1/* now if di was 1, C is M, otherwise C is 1 */
if di was 1, then C - M, but if di was 0, the C - 0 If C - 0, you get the wrong answer.
People aren't willing to pay $300/can for tuna. Demand will drop off. There would still be an incentive to fish for tuna, but it would be relegated to a very low volume high-end market.
How many Ferraris are sold vs. Civics? Shouldn't Honda be aggressively making millions of supercars?
Oh and. IBM had 65nm ASICs in June 2005 6 months ahead of Intel.
There's a huge difference between an ASIC process and a high volume processor process. When did IBM ship a 65nm POWER processor? Did they even ship one yet? Let me call Steve Jobs.
It is 1 year. AMD only has 1 fab. So if Intel has 1 fab first, then it has the advantage first. Intel can undercut AMD on price since it benefits from the per-transistor cost advantage. Prices drop on the older N-1 process chips, and by definition, that means prices drop on AMD's N-1 process for 1 year, assuming Intel/AMD are equally efficient at using their transistors. So, for a whole year, AMD is forced into a lower-end market.
You also forgot to mention that the process isn't static. It improves on a daily basis. That's why you get faster chips released every few months on the same process. That's a 1 year advantage to tune the process as well. As more fabs come online, they also inherit this advantage. You can't port those tunings to another competitor (like AMD) when their process is so radically different. SOI presents a very different optimization problem vs. Intel's non-SOI process.
The whole business is predicated on building fabs on the latest technology as soon as possible.
Yep, that huge technological lead of a few months.
The lead is 1 year. Intel shipped 65nm in December 2005. That is HUGE. You get to offer 2x transistor density for 1 whole year. Your cost per transistor is 50% cheaper for a year. In case you missed it, Intel made about 40 Billion dollars in its last fiscal year. That's no accident. They're able to generate that massive cashflow because they are one step ahead of everyone in the industry.
Now, if you screw up the architecture, it turns out that you can be really inefficient at using those extra transistors (see Pentium 4). But that's been fixed with Core2Duo.
IMO, AMD is pretty screwed now that Intel is making better use of their transitor density advantage.
The process also improves continuously. So while AMD will have a new 65nm process in December, Intel will have a 65nm process that has been improved for a whole year. Just look at the frequency headroom that overclockers are getting with Core2Duo. Now look at the AMD 65nm roadmap. The first 65nm AMD chips will clock LOWER than the 90nm chips. This is pretty normal for a new process as the parameters need to be tuned and refined over time.
Fab 36 will be online soon with 300mm wafers and 65nm. Just going to 300mm wafers pretty much doubles capacity. Going to 65nm gets you another say 50% (anyone got a confirmed number). Getting FAB 36 and FAB 30 going doubles capacity again. So, by my calculations that is 2 x 2 x 1.5 or 6x cpacity increase for AMD in the next couple of months.
90nm->65nm is approximately a 0.7x shrink in one dimension. (90 * 0.7) ~= 65 In 2 dimensions it's (0.7 * 0.7) ~= 0.5 so yes, a 50% shrink in area.
But what you forgot to mention was that the die size doesn't stay constant across processes. Engineers tend to do useful things with this bounty of transistors - like double the cache size for example.
Of course Intel has something like 6 processro FABs all over the world that are likely larger than AMDs. Doesn't take much R&D just to build more capacity especially when you are the 800lb gorilla.
Uh...doesn't take much R&D??? How do you suppose that Intel gets to the next process step a full 1 year ahead of everyone else on the planet? Magic?
How much is AMD benefitting from Intel working out the bugs.
Not much considering that AMD is using a vastly different process. SOI vs. bulk is just one of many MAJOR differences.
Otherwise, yes, Core 2 Duo is superior at the moment. I wonder if this will last when AMD goes to 65 nm.
I'm going to have to go with a "yes" on that one. Process technology within a node improves continously. Going to the next generation lithography (ie 90nm to 65nm) usually results in equal or LOWER speeds due to the process not being optimized yet. Have a look at the AMD Q4 roadmap: http://images.dailytech.com/nimage/2665_large_q407 _roadmap.png
Notice how the 65nm parts in green are SLOWER than the 90nm parts.
By the time AMD is getting 65nm up and running, Intel has had 1 whole year to optimize their 65nm process. This means higher speeds for the Core2Duo - just look at the headroom that the overclockers are getting.
But then fanboys/hexus say things like, wait until 2007/2008... Do you think Intel will sit still during this time? It's extremely hard to overcome a process technology lead. Kudos to AMD for doing it and sticking it to Intel and their clearly inferior Netburst mark-a-tecture. But let's face it... Intel isn't going to screw it up again.
Let me throw in some other interesting tidbits: - Intel has a much better cache density on a given process node. More cache in the same area on the same process. This is probably a side-effect of the SOI process. - Intel's microarchitecture is 4-wide issue. AMD's is 3-wide issue - even for K8L. - It's even better than 4-wide since they have instruction fusion which can fuse 2 or more instructions together and issue them as a single unit - Intel has superior branch predictors - Intel has out of order loads and stores - AMD will only relax load order and ONLY on K8L and beyond - Intel is working on a point-to-point bus archtetcture (CSI) to compete with HT
AMD has Centrino envy. More specifically, they need a platform strategy.
Let's face it. CPUs are commodities. You buy price/performance. Recently, Intel has been using the platform to differentiate itself. Centrino is one example in the notebook world. You can see other examples with "advanced I/O" in the newer server platforms. Intel dictates the platform and can define it to suit their needs.
AMD has no platform strategy. It's at the mercy of various 3rd party chipset makers.
This is why this makes strategic sense. AMD wants to control a platform and use that to differentiate itself from Intel.
No no no....the newest conspiracy theory is that Ken Lay isn't really dead - He's living it up in Argentina somewhere and he faked his death to get out of jail time. Where's the body?:)
5) Any advantage Intel will gain from C/M/W will be gone when AMD does their transition to 65nm in Q4. Sooner if Intel screws up, as is reported.
Huh? Woodcrest is launching at 3GHz today. Do you think frequency will sit still for 6 months? People have been getting 4GHz overclocking results using AIR cooling today. This shows that the process has headroom to scale.
When AMD gets to 65nm in late Q4 or more likely early 2007, they won't have the process setup to clock that high initially.
That's Intel's main advantage - the process technology is 12 months ahead.
How do you get more transistors on a chip with the same area? You reduce the transistor dimensions by making it smaller - Moore's law roughly says that the transistor density follows an exponential (2x/24 months or 18 months, depending on who you ask). By making it smaller, you ALSO make it faster as a side-effect. So, in effect, the original poster is correct - clock speed increases with Moore's Law.
The problem is that power/area remains constant.
So at some point this wonderful ride will come to an end - because even with cryogenic cooling, there is a fundamental thermodynamic limit to the amount of heat you can dissipate from a solid.
I win the "my-post-is-more-pedantic-than-your-post" award.
How do you predict demand? For that matter, how do you predict supply, when you're sourcing hundreds of components from all kinds of different manufacturers? Microsoft guessed, and guessed wrong.
If you can predict demand, you can make a shitload of money. It's not easy.
*Dynamic* voltage and frequency scaling is already available in processors from both Intel and AMD. System software can take advantage of this. Look up P-states and C-states. I think Vista supports these features. I'm not sure about XP. Linux of course supports it - look up power 'governors'.
The CPU designers went through a lot of trouble to provide software with the hooks to manage the voltage and frequency. Please don't go destabilizing your systems by manually "undervolting".
Power ~ Capacitance * Frequency * (Voltage)^2
Reducing frequency reduces power linearly.
Reducing voltage is a MUCH bigger lever as it reduces power CUBICly. Reducing voltage linearly also reduces frequency linearly which is why you get a cubic relationship.
There is only so far you can go in reducing voltage. Once you hit the threshold voltage of the transistor, it won't switch properly - so at this min-voltage, all you can do is frequency scale lower.
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For 5k, you can get a laptop and a desktop.
If you're at your desk, use the desktop. Are you in meetings 8 hours a day?
When I say VNC, I also mean anything like it (remote desktop etc...)
I'm an electrical engineer and we use laptops and we VNC into linux workstations to do very compute intensive things.
If you need the computational horsepower and portability, why not have a desktop and VNC into it through your laptop?
If you keep your money in a bank, it doesn't just sit there. The bank lends it out to other people or businesses - so leaving it in a bank isn't so detrimental to society. If you are unwilling to spend it, the bank will spend it on your behalf - while paying you an interest rate for the privilege.
Here we have "Why should we release this chip now?
Because if you don't release a better chip, who will upgrade and give you more money?
The old chips are MORE expensive to produce. The 65-nm die size is about 140mm^2 and the newer 45-nm die size is about 107mm^2, so actually, the next generation chip is cheaper to make.
In the absence of AMD, Intel would still have to compete with itself, otherwise nobody would upgrade and sales would tank.
I'd be surprised if the Core-2 didn't outperform on something as integer-intensive as a kernel compile with 64 bits or 32 bits for the reasons outlined in my previous post. The microarchitecture simply gets a higher IPC.
:)
For clues on compiler performance, you can look at the "gcc" component of the SPEC benchmark. I believe the benchmark is gcc compiling itself - but it's been a while since I've looked at it.
Now if you have a large budget and compile times are an issue, I'd invest in a compile-farm and use distcc
Core2 smokes the AMD64 in integer performance.
See SPECint scores at www.spec.org
This is intuitive because the Core2 is wider than the Opteron - which translates into more IPC.
It has a 4 wide issue, wider fetch bandwidth, instruction fusion which makes it effectively even wider than 4, deeper reorder buffers, out-of-order load/stores, hardware prefetching into the L1 cache. I could go on and on. The performance speaks for itself. Oh and the process lead (65nm Intel vs 90nm AMD) means Intel can give you double the cache in the same amount of area. Also, the entire cache can be used by a single core, instead of the hard-partitioned AMD design.
All of this means that the fastest Core2 is 50% faster than the fastest Opteron on SPECint. You simply cannot buy a faster integer machine.
I would suggest using ICC instead of GCC if you want performance out of either Intel or AMD. Frankly, gcc isn't going to get you anywhere near icc.
It's not just SSE performance where the Core-2 shines. It's also integer. The fastest Core-2 SPECint is 50% faster than the fastest AMD SPECint. ICC was used. This makes sense because the core-2 is a 4-wide issue with instruction-fusion (which makes it look effectively even wider) - wheras the Opteron is only 3-wide issue.
It makes very little sense that the Opteron would outperform on integer code.
You all realize that power scales with voltage CUBED right?
So 1.42 volts / 1.35 volts ~ 9%
But 9% cubed is about 1.09^3 = 30%
So 30% more power isn't exactly marginal.
Otherwise, CPU vendors would sell the chip at 1.42 volts.
I don't get it. /* should be doable without branch by just bit masking and shifting */ /* now if di was 1, C is M, otherwise C is 1 */
C = di
C = C * A
C = C + 1
if di was 1, then C - M, but if di was 0, the C - 0
If C - 0, you get the wrong answer.
You fail at economics.
People aren't willing to pay $300/can for tuna. Demand will drop off.
There would still be an incentive to fish for tuna, but it would be relegated to a very low volume high-end market.
How many Ferraris are sold vs. Civics? Shouldn't Honda be aggressively making millions of supercars?
Oh and. IBM had 65nm ASICs in June 2005 6 months ahead of Intel.
There's a huge difference between an ASIC process and a high volume processor process.
When did IBM ship a 65nm POWER processor?
Did they even ship one yet? Let me call Steve Jobs.
It is 1 year. AMD only has 1 fab. So if Intel has 1 fab first, then it has the advantage first.
Intel can undercut AMD on price since it benefits from the per-transistor cost advantage. Prices drop on the older N-1 process chips, and by definition, that means prices drop on AMD's N-1 process for 1 year, assuming Intel/AMD are equally efficient at using their transistors. So, for a whole year, AMD is forced into a lower-end market.
You also forgot to mention that the process isn't static. It improves on a daily basis. That's why you get faster chips released every few months on the same process. That's a 1 year advantage to tune the process as well. As more fabs come online, they also inherit this advantage. You can't port those tunings to another competitor (like AMD) when their process is so radically different. SOI presents a very different optimization problem vs. Intel's non-SOI process.
The whole business is predicated on building fabs on the latest technology as soon as possible.
It's 0.7 in one dimension.
So in terms of area, it's 0.7*0.7 = 0.49 or roughly half.
Therefore you double transistor density every 2 years - a nice binary exponential.
Yep, that huge technological lead of a few months.
The lead is 1 year. Intel shipped 65nm in December 2005. That is HUGE. You get to offer 2x transistor density for 1 whole year. Your cost per transistor is 50% cheaper for a year. In case you missed it, Intel made about 40 Billion dollars in its last fiscal year. That's no accident. They're able to generate that massive cashflow because they are one step ahead of everyone in the industry.
Now, if you screw up the architecture, it turns out that you can be really inefficient at using those extra transistors (see Pentium 4). But that's been fixed with Core2Duo.
IMO, AMD is pretty screwed now that Intel is making better use of their transitor density advantage.
The process also improves continuously. So while AMD will have a new 65nm process in December, Intel will have a 65nm process that has been improved for a whole year. Just look at the frequency headroom that overclockers are getting with Core2Duo. Now look at the AMD 65nm roadmap. The first 65nm AMD chips will clock LOWER than the 90nm chips. This is pretty normal for a new process as the parameters need to be tuned and refined over time.
Fab 36 will be online soon with 300mm wafers and 65nm. Just going to 300mm wafers pretty much doubles capacity. Going to 65nm gets you another say 50% (anyone got a confirmed number). Getting FAB 36 and FAB 30 going doubles capacity again. So, by my calculations that is 2 x 2 x 1.5 or 6x cpacity increase for AMD in the next couple of months.
90nm->65nm is approximately a 0.7x shrink in one dimension. (90 * 0.7) ~= 65
In 2 dimensions it's (0.7 * 0.7) ~= 0.5 so yes, a 50% shrink in area.
But what you forgot to mention was that the die size doesn't stay constant across processes.
Engineers tend to do useful things with this bounty of transistors - like double the cache size for example.
Of course Intel has something like 6 processro FABs all over the world that are likely larger than AMDs. Doesn't take much R&D just to build more capacity especially when you are the 800lb gorilla.
Uh...doesn't take much R&D???
How do you suppose that Intel gets to the next process step a full 1 year ahead of everyone else on the planet? Magic?
How much is AMD benefitting from Intel working out the bugs.
Not much considering that AMD is using a vastly different process. SOI vs. bulk is just one of many MAJOR differences.
Process steps move forward every 2 years.
45nm in 2008
32nm in 2010
more generally:
0.7 * gate_length(N) in year(N) + 2
Thermal limits will hit hard in 10+ years. No exponential can go on forever.
Otherwise, yes, Core 2 Duo is superior at the moment. I wonder if this will last when AMD goes to 65 nm.
7 _roadmap.png
I'm going to have to go with a "yes" on that one.
Process technology within a node improves continously.
Going to the next generation lithography (ie 90nm to 65nm) usually results in equal or LOWER speeds due to the process not being optimized yet.
Have a look at the AMD Q4 roadmap: http://images.dailytech.com/nimage/2665_large_q40
Notice how the 65nm parts in green are SLOWER than the 90nm parts.
By the time AMD is getting 65nm up and running, Intel has had 1 whole year to optimize their 65nm process.
This means higher speeds for the Core2Duo - just look at the headroom that the overclockers are getting.
But then fanboys/hexus say things like, wait until 2007/2008...
Do you think Intel will sit still during this time?
It's extremely hard to overcome a process technology lead.
Kudos to AMD for doing it and sticking it to Intel and their clearly inferior Netburst mark-a-tecture.
But let's face it... Intel isn't going to screw it up again.
Let me throw in some other interesting tidbits:
- Intel has a much better cache density on a given process node. More cache in the same area on the same process. This is probably a side-effect of the SOI process.
- Intel's microarchitecture is 4-wide issue. AMD's is 3-wide issue - even for K8L.
- It's even better than 4-wide since they have instruction fusion which can fuse 2 or more instructions together and issue them as a single unit
- Intel has superior branch predictors
- Intel has out of order loads and stores - AMD will only relax load order and ONLY on K8L and beyond
- Intel is working on a point-to-point bus archtetcture (CSI) to compete with HT
In short - it doesn't look good for AMD.
AMD has Centrino envy. More specifically, they need a platform strategy.
Let's face it. CPUs are commodities. You buy price/performance.
Recently, Intel has been using the platform to differentiate itself.
Centrino is one example in the notebook world.
You can see other examples with "advanced I/O" in the newer server platforms.
Intel dictates the platform and can define it to suit their needs.
AMD has no platform strategy. It's at the mercy of various 3rd party chipset makers.
This is why this makes strategic sense.
AMD wants to control a platform and use that to differentiate itself from Intel.
No no no....the newest conspiracy theory is that Ken Lay isn't really dead - He's living it up in Argentina somewhere and he faked his death to get out of jail time. Where's the body? :)
5) Any advantage Intel will gain from C/M/W will be gone when AMD does their transition to 65nm in Q4. Sooner if Intel screws up, as is reported.
Huh? Woodcrest is launching at 3GHz today.
Do you think frequency will sit still for 6 months?
People have been getting 4GHz overclocking results using AIR cooling today.
This shows that the process has headroom to scale.
When AMD gets to 65nm in late Q4 or more likely early 2007, they won't have the process setup to clock that high initially.
That's Intel's main advantage - the process technology is 12 months ahead.
Why would quantum/bio/whatever be needed if all you want to do is run Office?
640K... I mean Office... should be enough for everybody right?
How do you get more transistors on a chip with the same area?
You reduce the transistor dimensions by making it smaller - Moore's law roughly says that the transistor density follows an exponential (2x/24 months or 18 months, depending on who you ask).
By making it smaller, you ALSO make it faster as a side-effect.
So, in effect, the original poster is correct - clock speed increases with Moore's Law.
The problem is that power/area remains constant.
So at some point this wonderful ride will come to an end - because even with cryogenic cooling, there is a fundamental thermodynamic limit to the amount of heat you can dissipate from a solid.
I win the "my-post-is-more-pedantic-than-your-post" award.
Obviously it was too cheap in **hindsight**
How do you predict demand?
For that matter, how do you predict supply, when you're sourcing hundreds of components from all kinds of different manufacturers?
Microsoft guessed, and guessed wrong.
If you can predict demand, you can make a shitload of money. It's not easy.
Reuters is a very reputable news source and they are reporting the same thing.
r ticle.aspx?storyID=urn:newsml:reuters.com:20060405 :MTFH84939_2006-04-05_22-17-54_N05357049&symbol=MS FT.O&rpc=44
http://yahoo.reuters.com/stocks/QuoteCompanyNewsA
Uhmm...Yeah cubic = 3
1) Frequency ~ Voltage
2) Power ~ Cap. * Freq * (Voltage)^2
where ~ means "proportional to"
Because of #1,
Power ~ Cap. * (Voltage)^3
You might want to design some processors before you start saying something is wrong first.
*Dynamic* voltage and frequency scaling is already available in processors from both Intel and AMD. System software can take advantage of this. Look up P-states and C-states. I think Vista supports these features. I'm not sure about XP. Linux of course supports it - look up power 'governors'.
The CPU designers went through a lot of trouble to provide software with the hooks to manage the voltage and frequency. Please don't go destabilizing your systems by manually "undervolting".
Power ~ Capacitance * Frequency * (Voltage)^2
Reducing frequency reduces power linearly.
Reducing voltage is a MUCH bigger lever as it reduces power CUBICly. Reducing voltage linearly also reduces frequency linearly which is why you get a cubic relationship.
There is only so far you can go in reducing voltage. Once you hit the threshold voltage of the transistor, it won't switch properly - so at this min-voltage, all you can do is frequency scale lower.