I can assure you that our designs are absolutely available for commercial use. That is the entire purpose. We release freely and unencumbered reference designs using components we sell. These designs (usually called appnotes) are specifically made to ease the design-in for a commercial user.
I can't imagine why a semiconductor vendor would release reference designs with limitations on commercial usage. Commercial usage is what we make a living of.
So what's new with 'open source hardware'? I work in a semiconductor company and we got lots of designs including schematics board layouts firmware and BOMs, other companies do the same thing.
The point is of course to sell our devices by having customers using our designs, but the point is that there are lots of free designs out there, and they have been made available for many years not just the last few as it has been stated in the article.
PICs and AVRs (and MSP430s) are microcontrollers. The only thing you will be adding to those if your budget is less than "$350" is software added to a development kit.
Please realize that hacking in just about any high-tech field other than software will incur significant costs. If you want to do any significant hardware hacking that is anywhere close to state of the art expect thousands of dollars in NRE. if you don't i'd claim that you only do software hacking.
"> I always viewed CEOs as salespeople" "That's a ridiculous idea"Â...Â"S/he is the highest decision maker and is responsible for envisioning and implementing the highest level strategy of the company."
Most companies strategy usually is on the form: -make some product. -Sell it
(or possible in the opposite order)
I really don't see why it so ridiculous to view CEOs as salespeople. The ultimate strategy of almost any company is to sell something.
Converters cost money and add space. Both are at a premium in modern electronics. Most consumer electronics have only a few dollars worth of parts, so adding some tens of cents to the BOM matters. Hey, even auto manufacturers will go to great lengths to shave 20c off their electronics costs.
>There's nothing quite like having a sudden unbudgeted $2000 expense. It's one of the reason my credit card is maxed out.
Hey, the norwegian tax collector have done that to me each year since 2005 due to gross increases in "wealth" tax. Just because health-care is pretty much fully covered doesn't mean you are safe.
Flash memory is 4 extra masks over a straight CMOS process, which will add complexity which you will need to debug. It makes much more sense to test a fab with regular test patterns and SRAMS (Which will be needed in the final CPU). Do they even run flash in the same fabs as CPUs?
Ahhh, but a TRUE macro lens WILL stop down to F32 or even F45 when focused at INFINITY!! Add the extension tube to that and what do you get????
A lot of diffraction blur. On modern DSLRs the imager out-resolves lenses at arounf f/16. Of cource if you must increase focal depth go ahead, but you will get to a point where it will be better to reduce magnification and just crop.
To be pedantic, he did not change the focusing distance, he moved the lens closer to the object. Focusing distance is properly measured from the sensor to the object, not from the front of the lens.
It strikes me that a pringles can must be maybe the worst imaginable thing to make a extention tube out of its insides beeing reflective...
A bellows isn't that expensive, I got a used nikon bellows for about $200 and with that I also get tilt&shift functionality, adjustable extention, focusing rail and a proper tripod mount.
For the cheapest possible macro (if you allready got the lenses), mount a wideangle backwards in front of a tele lens (A reversing adapter should not cost more than $10-20)
Actually the parent to your post is correct. Adding spacers increase the the f-stop as though the the focal length of the lens increased by the length of the spacer.
The physical aperture of a 50mm f/16 is 3.125mm. Adding the spacer gives you 100mm which get the f-number of f/32 with 3.125mm aperture.
This effect of cource also exist with normal focusing (When the whole assembly moves) but is usually too small to bother with. The exception is micro/macro lenses. Many modern micro/macro lenses will actually report this change in f-stop to the camera so the automatic metering can take it into account. (This is visible on the display on my camera, A D100 with micro nikkor 60mm f/2.8D)
Actually lenses that give you greater than 1:1 magnification are macro lenses. Up to and incluning 1:1 is micro. Nikon got their naming straight, most of the other vendors misuse the macro term though.
Shorter wires do make C a little bit smaller, but the dominant part there is the gate capacitance.
Only if you target 0.25um or older technologies. At 0.18um gatecap and wirecap is pretty similar (statistically). At 0.15um and down wires dominate.
This is due to gates getting smaller and wires getting taller. (To compensate for smaller widths the metal layers are grown taller to maintain a reasonable sheet resistance)
You must run a full test after packaging regardless of wafer level tests since you might mess up somthing during cutting and mounting of the die. Thus you only want to run wafer tests if you excpect a sufficiently low yield that the price of wafer testing is saved due to less packaged defective devices.
70 dies on a wafer is incredibly low though. That is typical only for exotic large devices like CPUs. Most chips are considerably smaller and have often yields of 500-1000 devices pr. wafer. These devices often have yields of 90-98% and will not be tested at wafer sort, neither will the small amount of discarded devices be recycled.
Since you don't appear to have any aversion against long games I would highly recomend Any 18XX games. Most readily available are 1856 and 1870. Of these two I would prefer 1856 due to it's more vicious and fast paced nature.
For those not familiar with these games, they are primarily a economic games disguising like train games. The basic idea is to be the one with the most money on hand at the end. Do note that this is not the same as generating the most money for your company. (Indeed you might want to drive a company near bankrupt then dump it on a unsuspecting opponent)
They play best with 5-6 players and take 4-8 hours (depending on experience)
For a lighter train game I would recomend Age of Steam, a very well paced game that works well for 3-6 players and take approx. 2 hours.
Also of note FFG just released Twilight Imperium 3rd ed. Which is worth a look.
Actually a real high-end sound system should have a subwoofer. It is much preferable to generate bass at a single source. Multiple bass sources tend to generate interference patterns, which leads to a very uneven bass response.
Also a good active sub can be had for much less than a high-end speaker capable of the same bass. With reduced requirements for bass in the main speakers they can become cheaper and easier to drive.
I certanly don't hold with the idea that chip design is reserved for the big boys only. There are plenty of small chip design companies out there. You don't have to be big, but you do have to be able to raise the capital to support the design and tape-out.
FPGA development is definetly closely linked to ASIC development (much more so than to software), and you can indeed do that fairly reasonably. You will still need to get a simulator, a FPGA synthesis tool (like Synplicity or Precision) and implementation and analysis tools from the FPGA vendor, which will still set you back some $10-20K. (Which is cheap considering that a decent design seat in an ASIC flow will cost approx $50-150K, assuming you share licenses for batch tools)
You might think that you can live without the simulator (bad idea), but then you are going to need something like chipscope and a supported logic analyzer which also cost a fair penny.
Also remember that you are going to pay approx 15% maintenance annualy on your EDA tools.
Don't get me wrong. L-edit is a nice enough tool for analog full custom stuff, and it also have a bit of a following in the MEMS world. It does however not have an autoplacer, autorouter or netlist capability that is required to do digital layout.
Oh sure you can do full custom digital layout in it if you like (I assume you then are also into things like whips racks, iron maidens and other instruments of torture:-) ), but you will have to do pretty much everything manually.
L-edit isn't a starting point for digital layout. Never was. It is a polygon pusher, and as such eminently capable to do analog designs like f.ex. CCDs.
Tanner has a besic DRC checker built in (It just got upgraded to understand calibre DRC rules so it is much more useful now). It isn't good enough for sign-off though so you propably want to have Calibre (or possible Hercules) as well.
Cadence is to the best of my knowledge the largest EDA house out there, but are notorious for following the philosophy 'When the going gets tough, the tough goes shopping'. As a result they have anamalgamation of tools, some which overlap other tools in their inventory and others which just don't fit very well. They are strong in Analog full custom design and silicon virtual prototyping with light place & route tasks. (I.e. Encounter)
For digital design Synopsys is generally the big dog, owning both the synthesis and STA market and are strong in pretty much every other part of the back-end analysis/verification side.
Are you saying that developing a design for a FPGA and developing software for a uC is similar? I beg to differ. The only similarity is that the final result is uploaded to a hardware device. The design process is vastly different.
FPGAs are programmed in Verilog or VHDL; it's not much different from programming a computer.
I have seen the results of software people trying to design hardware thinking HDL design is pretty much like software. It isn't, and the results weren't pretty.
If you don't realise what the hardware does, and what hardware your code will infere you will likely get a rather rude shock And crap/expensive hardware)
Also, I won't recomend using a FPGA as a development platform for something that will ultimately be an ASIC. It is OK for prototyping but for the actual development a simulator will work much better as there is much less overhead in getting up and running and much better visibility.
FPGAs are ok for prototyping though, but you will se results pretty late in the process.
L-edit is a polygon pusher. You are going to be pretty damn persistent to do anything more than a puny digital design in that.
For real digital layout you want to use Astro/Synopsys, Encounter/Cadence, Blast Fusion/Magma or Pinnacle/Sierra (Just maybe). None of these are going to cost you less than a few $100K.
Of cource before you to the point of doing layout you likely want to do synthesis (Although it is not beyond human capability to hand generate netlists). Design Compiler/Synopsys is pretty much the defacto standard but both cadence and magma has credible alternatives.
After layout you want to check your design for timing. To do this you want a Static Timing Analysis tool (Primetime from Synopsys is pretty much the only choice here for sign-off quality, though you might live with what your back-end tool has built in if you feel brave). To feed the STA tool with good data you need to extract the circuit: StarXTRC/Synopsys, Fire & Ice/Cadence, CalibreXRC are the prime contenders.
In addition you might want/need to do: - Formal verification (To verify your final netlist conforms to your design) - Rail analysis (To verify your power grid is adequate) - Thermal analysis (To check your device won't melt of fail due to too high junction temperature) - Crosstalk analysis (Check for parasitic effects on timing. Required for designs on 0.13um and better)
A complete tools suite for digital design will likely set you back $1000K. Naturally a lot of smaller designhouses will outsource the the implementation, but they will at minimum require simulators (minimum $5000 a seat) and synthesis ($100000 pr. license)
As for fabbing, $500? That would be a mighty sweet deal, even for a shared MPW run. With academic discounts and on an old process you might be able to get a slot on an MPW for $5000. On a reasonably modern process (like 0.18um) a engineering run with 6 prototyping wafers (i.e. not a MPW) will set you back somwhere between $50K to $200K
One of the reasons extolled at length for choosing one type against abother is that a DSLR has a narrow depth of field and a "standard" digital camera has a greater depth. As anyone who knows about photography would know this is total tosh.
No it's not.
DOF is not only dependent of the aperture, but also on actual focal length and how large your circle of confusion is.
While the smaller circle of confusion on compact digcams reduce the net DOF, the biggest difference is due to the very short focal lenghts these cameras use.
Since your typical digicam has a very small sensor compared to a DSLR it will use a short focal length to get a normal viewing angle. The increase in DOF due to this short focal length often makes it impossible to properly blur the background.
Of cource on DSLRs you can get optics with numerical aperture of f1.4 or even less. Good luck in finding a digicam with such a large aperture.
Cross talk is from cable to cable. That's why they are flat, so as to minimize the amount that their magnetic fields interact.
No, they are flat becuse ribbon cables are cheaper to make than round cables. Ribbon cables are lousy signal carriers. (They are pretty good antennaes though)
So unless each of the 40 data cables are [i]individually raped in a foil or copper AND grounded AT BOTH ENDS[/i] your cables are not sheilded AND you've been ripped off.
I generally prefer my cables unraped as I find raped cables to be mentally unstable;-).
Seriously you do not want to make a coax cable of each conductor as the increase in capacitance will likely kill the cable for high performance applications. Nor do you need to ground the cable at each end (if the potentials are slightly off this will actually increase noise due to the ground current)
While rounded cable for IDE rives do not perform any better than the free stuff (since these perform good enough and for this purpose that is as good as it gets), they don't neccecarily perform worse either. The twisted pair design most of these use aren't any worse than a flat cable (That would take some doing...)
First off power consumption for a processor =.5*C*V^2*F where c is capacitance, V is voltage, and F is frequency. So if you can find capacitance you can get a pretty good estimate of the processor's power needs.
That is way simplified. That would be a first order approximation for the dynamic power in a device where each node toggles at f/2. The real activity in the device must be determined (weighted by net load) and used to replace the.5 figure in the formula you wrote. In addition we have static power consumption which is quite significant at 0.18um processes and below.
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I can assure you that our designs are absolutely available for commercial use. That is the entire purpose. We release freely and unencumbered reference designs using components we sell.
These designs (usually called appnotes) are specifically made to ease the design-in for a commercial user.
I can't imagine why a semiconductor vendor would release reference designs with limitations on commercial usage. Commercial usage is what we make a living of.
So what's new with 'open source hardware'?
I work in a semiconductor company and we got lots of designs including schematics board layouts firmware and BOMs, other companies do the same thing.
The point is of course to sell our devices by having customers using our designs, but the point is that there are lots of free designs out there, and they have been made available for many years not just the last few as it has been stated in the article.
You are confusing ARMv7 (which is the ISA of the current generation cortex CPUs (M3, R4, A8, A9) and the ARM7 (Which uses ARMv3).
PICs and AVRs (and MSP430s) are microcontrollers. The only thing you will be adding to those if your budget is less than "$350" is software added to a development kit.
Please realize that hacking in just about any high-tech field other than software will incur significant costs. If you want to do any significant hardware hacking that is anywhere close to state of the art expect thousands of dollars in NRE. if you don't i'd claim that you only do software hacking.
"> I always viewed CEOs as salespeople"
"That's a ridiculous idea"Â...Â"S/he is the highest decision maker and is responsible for envisioning and implementing the highest level strategy of the company."
Most companies strategy usually is on the form:
-make some product.
-Sell it
(or possible in the opposite order)
I really don't see why it so ridiculous to view CEOs as salespeople. The ultimate strategy of almost any company is to sell something.
Converters cost money and add space. Both are at a premium in modern electronics. Most consumer electronics have only a few dollars worth of parts, so adding some tens of cents to the BOM matters. Hey, even auto manufacturers will go to great lengths to shave 20c off their electronics costs.
>There's nothing quite like having a sudden unbudgeted $2000 expense. It's one of the reason my credit card is maxed out.
Hey, the norwegian tax collector have done that to me each year since 2005 due to gross increases in "wealth" tax. Just because health-care is pretty much fully covered doesn't mean you are safe.
Flash memory is 4 extra masks over a straight CMOS process, which will add complexity which you will need to debug. It makes much more sense to test a fab with regular test patterns and SRAMS (Which will be needed in the final CPU). Do they even run flash in the same fabs as CPUs?
Ahhh, but a TRUE macro lens WILL stop down to F32 or even F45 when focused at
INFINITY!! Add the extension tube to that and what do you get????
A lot of diffraction blur. On modern DSLRs the imager out-resolves lenses at arounf f/16. Of cource if you must increase focal depth go ahead, but you will get to a point where it will be better to reduce magnification and just crop.
To be pedantic, he did not change the focusing distance, he moved the lens closer to the object. Focusing distance is properly measured from the sensor to the object, not from the front of the lens.
It strikes me that a pringles can must be maybe the worst imaginable thing to make a extention tube out of its insides beeing reflective...
A bellows isn't that expensive, I got a used nikon bellows for about $200 and with that I also get tilt&shift functionality, adjustable extention, focusing rail and a proper tripod mount.
For the cheapest possible macro (if you allready got the lenses), mount a wideangle backwards in front of a tele lens (A reversing adapter should not cost more than $10-20)
Actually the parent to your post is correct. Adding spacers increase the the f-stop as though the the focal length of the lens increased by the length of the spacer.
The physical aperture of a 50mm f/16 is 3.125mm. Adding the spacer gives you 100mm which get the f-number of f/32 with 3.125mm aperture.
This effect of cource also exist with normal focusing (When the whole assembly moves) but is usually too small to bother with. The exception is micro/macro lenses. Many modern micro/macro lenses will actually report this change in f-stop to the camera so the automatic metering can take it into account. (This is visible on the display on my camera, A D100 with micro nikkor 60mm f/2.8D)
Actually lenses that give you greater than 1:1 magnification are macro lenses. Up to and incluning 1:1 is micro. Nikon got their naming straight, most of the other vendors misuse the macro term though.
Shorter wires do make C a little bit smaller, but the dominant part there is the gate capacitance.
Only if you target 0.25um or older technologies. At 0.18um gatecap and wirecap is pretty similar (statistically). At 0.15um and down wires dominate.
This is due to gates getting smaller and wires getting taller. (To compensate for smaller widths the metal layers are grown taller to maintain a reasonable sheet resistance)
You must run a full test after packaging regardless of wafer level tests since you might mess up somthing during cutting and mounting of the die. Thus you only want to run wafer tests if you excpect a sufficiently low yield that the price of wafer testing is saved due to less packaged defective devices.
70 dies on a wafer is incredibly low though. That is typical only for exotic large devices like CPUs. Most chips are considerably smaller and have often yields of 500-1000 devices pr. wafer. These devices often have yields of 90-98% and will not be tested at wafer sort, neither will the small amount of discarded devices be recycled.
Since you don't appear to have any aversion against long games I would highly recomend Any 18XX games. Most readily available are 1856 and 1870. Of these two I would prefer 1856 due to it's more vicious and fast paced nature.
For those not familiar with these games, they are primarily a economic games disguising like train games. The basic idea is to be the one with the most money on hand at the end. Do note that this is not the same as generating the most money for your company. (Indeed you might want to drive a company near bankrupt then dump it on a unsuspecting opponent)
They play best with 5-6 players and take 4-8 hours (depending on experience)
For a lighter train game I would recomend Age of Steam, a very well paced game that works well for 3-6 players and take approx. 2 hours.
Also of note FFG just released Twilight Imperium 3rd ed. Which is worth a look.
Actually a real high-end sound system should have a subwoofer. It is much preferable to generate bass at a single source. Multiple bass sources tend to generate interference patterns, which leads to a very uneven bass response.
Also a good active sub can be had for much less than a high-end speaker capable of the same bass. With reduced requirements for bass in the main speakers they can become cheaper and easier to drive.
I certanly don't hold with the idea that chip design is reserved for the big boys only. There are plenty of small chip design companies out there. You don't have to be big, but you do have to be able to raise the capital to support the design and tape-out.
FPGA development is definetly closely linked to ASIC development (much more so than to software), and you can indeed do that fairly reasonably. You will still need to get a simulator, a FPGA synthesis tool (like Synplicity or Precision) and implementation and analysis tools from the FPGA vendor, which will still set you back some $10-20K. (Which is cheap considering that a decent design seat in an ASIC flow will cost approx $50-150K, assuming you share licenses for batch tools)
You might think that you can live without the simulator (bad idea), but then you are going to need something like chipscope and a supported logic analyzer which also cost a fair penny.
Also remember that you are going to pay approx 15% maintenance annualy on your EDA tools.
Don't get me wrong. L-edit is a nice enough tool for analog full custom stuff, and it also have a bit of a following in the MEMS world. It does however not have an autoplacer, autorouter or netlist capability that is required to do digital layout.
:-) ), but you will have to do pretty much everything manually.
Oh sure you can do full custom digital layout in it if you like (I assume you then are also into things like whips racks, iron maidens and other instruments of torture
On larger deigns it tend to choke a bit though.
L-edit isn't a starting point for digital layout. Never was. It is a polygon pusher, and as such eminently capable to do analog designs like f.ex. CCDs.
Tanner has a besic DRC checker built in (It just got upgraded to understand calibre DRC rules so it is much more useful now). It isn't good enough for sign-off though so you propably want to have Calibre (or possible Hercules) as well.
Cadence is to the best of my knowledge the largest EDA house out there, but are notorious for following the philosophy 'When the going gets tough, the tough goes shopping'. As a result they have anamalgamation of tools, some which overlap other tools in their inventory and others which just don't fit very well. They are strong in Analog full custom design and silicon virtual prototyping with light place & route tasks. (I.e. Encounter)
For digital design Synopsys is generally the big dog, owning both the synthesis and STA market and are strong in pretty much every other part of the back-end analysis/verification side.
Mentor and Cadence got better simulators though.
Are you saying that developing a design for a FPGA and developing software for a uC is similar? I beg to differ. The only similarity is that the final result is uploaded to a hardware device. The design process is vastly different.
FPGAs are programmed in Verilog or VHDL; it's not much different from programming a computer.
I have seen the results of software people trying to design hardware thinking HDL design is pretty much like software. It isn't, and the results weren't pretty.
If you don't realise what the hardware does, and what hardware your code will infere you will likely get a rather rude shock And crap/expensive hardware)
Also, I won't recomend using a FPGA as a development platform for something that will ultimately be an ASIC. It is OK for prototyping but for the actual development a simulator will work much better as there is much less overhead in getting up and running and much better visibility.
FPGAs are ok for prototyping though, but you will se results pretty late in the process.
L-edit is a polygon pusher. You are going to be pretty damn persistent to do anything more than a puny digital design in that.
For real digital layout you want to use Astro/Synopsys, Encounter/Cadence, Blast Fusion/Magma or Pinnacle/Sierra (Just maybe). None of these are going to cost you less than a few $100K.
Of cource before you to the point of doing layout you likely want to do synthesis (Although it is not beyond human capability to hand generate netlists). Design Compiler/Synopsys is pretty much the defacto standard but both cadence and magma has credible alternatives.
After layout you want to check your design for timing. To do this you want a Static Timing Analysis tool (Primetime from Synopsys is pretty much the only choice here for sign-off quality, though you might live with what your back-end tool has built in if you feel brave). To feed the STA tool with good data you need to extract the circuit: StarXTRC/Synopsys, Fire & Ice/Cadence, CalibreXRC are the prime contenders.
In addition you might want/need to do:
- Formal verification (To verify your final netlist conforms to your design)
- Rail analysis (To verify your power grid is adequate)
- Thermal analysis (To check your device won't melt of fail due to too high junction temperature)
- Crosstalk analysis (Check for parasitic effects on timing. Required for designs on 0.13um and better)
A complete tools suite for digital design will likely set you back $1000K. Naturally a lot of smaller designhouses will outsource the the implementation, but they will at minimum require simulators (minimum $5000 a seat) and synthesis ($100000 pr. license)
As for fabbing, $500? That would be a mighty sweet deal, even for a shared MPW run. With academic discounts and on an old process you might be able to get a slot on an MPW for $5000. On a reasonably modern process (like 0.18um) a engineering run with 6 prototyping wafers (i.e. not a MPW) will set you back somwhere between $50K to $200K
One of the reasons extolled at length for choosing one type against abother is that a DSLR has a narrow depth of field and a "standard" digital camera has a greater depth. As anyone who knows about photography would know this is total tosh.
No it's not.
DOF is not only dependent of the aperture, but also on actual focal length and how large your circle of confusion is.
While the smaller circle of confusion on compact digcams reduce the net DOF, the biggest difference is due to the very short focal lenghts these cameras use.
Since your typical digicam has a very small sensor compared to a DSLR it will use a short focal length to get a normal viewing angle. The increase in DOF due to this short focal length often makes it impossible to properly blur the background.
Of cource on DSLRs you can get optics with numerical aperture of f1.4 or even less. Good luck in finding a digicam with such a large aperture.
Cross talk is from cable to cable. That's why they are flat, so as to minimize the amount that their magnetic fields interact.
;-).
No, they are flat becuse ribbon cables are cheaper to make than round cables. Ribbon cables are lousy signal carriers. (They are pretty good antennaes though)
So unless each of the 40 data cables are [i]individually raped in a foil or copper AND grounded AT BOTH ENDS[/i] your cables are not sheilded AND you've been ripped off.
I generally prefer my cables unraped as I find raped cables to be mentally unstable
Seriously you do not want to make a coax cable of each conductor as the increase in capacitance will likely kill the cable for high performance applications. Nor do you need to ground the cable at each end (if the potentials are slightly off this will actually increase noise due to the ground current)
While rounded cable for IDE rives do not perform any better than the free stuff (since these perform good enough and for this purpose that is as good as it gets), they don't neccecarily perform worse either. The twisted pair design most of these use aren't any worse than a flat cable (That would take some doing...)
First off power consumption for a processor = .5*C*V^2*F where c is capacitance, V is voltage, and F is frequency. So if you can find capacitance you can get a pretty good estimate of the processor's power needs.
.5 figure in the formula you wrote. In addition we have static power consumption which is quite significant at 0.18um processes and below.
That is way simplified. That would be a first order approximation for the dynamic power in a device where each node toggles at f/2. The real activity in the device must be determined (weighted by net load) and used to replace the