If the manufacturer get a high yield in the higher grade bins, but has higher demand for lower speed grades. They may choose to marke them down rather than forcing down the price of the high-speed parts by supplying too much in excess of demand.
That is just regular die to die bonding in a multichip module.
The new thing here is to communicate only through capacative coupling avoiding having to place a huge pad and drivers for it (500-2000um^2 each). Additional bonuses is that you avoid exposing the die to the stresses of the bonding machine, you gain speed as there is much less capacitance and inductance to fight with, and possibly you can achieve a cheaper assembly method.
Modules with dies communicating this way will propably not be a end user assembly. The assemblies will still be made in a cleanroom.
And my conclusion was that raw clock speed IS the most important factor in performance, if you get your information from other sources than AMD or Apple. Because there are few applications that really use more than a small fraction of current PCs capabilities. And those applications, like AI and physics simulations, do need GHz, that is, floating-point operations per second is the most important limitation in those CPU-intensive apps.
FLOPS are not proportional to the clock frequenzy across multiple architectures. I have had a circuit simulator benchmarked on p4 vs. opterons and while the p4 3.4GHz beat a operon 2.2GHz, it did not beat it by more than 20%. By your theory it should have beat it by 50%. Also we benchmarked against a xeon 3.2GHz, which turned in a disappointing result at less than 70% of the performance.
The conclusion: For this particular application, the memory interface dominates the performance.
Note that even for applications that fits in cache, you can't just look at clock frequency as different architectures don't neccecarily retire the same amound of floating point instructions pr. clock (even under ideal circumstances)
The power-pc cores you can use in the Vertex 2 pro devices are not soft (synthesizable) cores. They exist as fixed cells on the FPGA array.
That a core is synthesizable does not just mean you can place it in a FPGA. It also means it can be targeted for any logic process.
I've frequently used soft cores in conjuction with my own logic ON asic/assp devices.
The advantage of soft cores are that they are easily retargetable to new technologies and is easier to integrate in a design as you don't need to make special provisions in floorplanning to fit it.
Xilinx and other typical FPGAs are not really designed to reconfigure on the fly. Normally they are loaded once on power-on and stay that way for the duration of their usage.
CPUs on FPGAs are a bit of an anachronism really, at least the soft cores like the one you pointed to (microblaze), as you could just as well implement your algorithm in hardware rather than make a CPU, which is an incredible slow piece of circuitry, on slow hardware (FPGAs are pretty sluggish compared to standard cell or full custom devices) then run software on it.
Modern high-end FPGAs do howeer have hard core* (no, not porn) CPUs embedded. F.ex Xilinx vertex 2 pro devices have power-pc cores embedded. These are considerably faster than what you can do on the fpga array itself.
*) hard cores are fully finished designs allready targeted to a technology. The name differciates them from soft cores which are synthisizable and can be targeted to any technology.
(I don't now anymore if the color used twice is red or blue. This increases the SNL for this color.)
It is green because it is closest to the middle of the spectrum. It does more than just increase the resolution of that color yhough. It's primary purpose is to increase the luminosity resolution. This is called a bayer pattern.
Now for each quadruple of sensors the data for one pixel is generated.
Nope each photosite generates a pixel. It's color is calculated using a demosaic algorithm which uses the surrounding photosites as well. (calling this interpolation is rather misleading)
This means the bayer sensor has a luminosity resolution close to the pixel resolution, but a chrominance resolution somewhat lower. This works out fine because your eyes has pretty much the same characteristic.
This will go on until multi-layered CCDs emerge on market. These use one spot on the chip to measure all three colors by layering the sensors.
They are allready on the market. Unfortunately they are not good enough to be competitive with traditional sensors yet. While they have the same chroma and luma resolution (which might be considered wasteful), they do have a lower resolution overall due to larger photosites. I also suspect that the precision by which these detectors ca diffreciate between wavelnghts aren't too good as they are hugely dependent on the precision of the doping of the semicondctor.
"The top line Nikon has a buffer that lets you take up to 144 pics in a row by holding down the shutter button."
You are thinking of the D70. While it is able to write fast enough to keep taking pictures in normal JPEG 3 pictures pr. second without filling the buffer, it does not have room for 144 pictures in the buffer.
Nor is the D70 the top of the line Nikon. That honor goes to the D1x or D2h depending on what you want. Those have buffers in the 40 picture range. (Depending on the resolution). With 8 pictures pr. second for the D2h, this might be useful. (The D2h can alo be equipped with a 802.11b card and set to upload pictures via FTP as they are taken)
As for using huge CF cards. I would think that most photographers would not like to put quite that many eggs in one basket. Those who require extreme capacity can also go for a X-drive or a laptop.
Then again. For sports events, as you say, there may be some purpose to this. With pro-level optics for this purpose (Super teles and Super tele zooms) costing in the $1000-$5000 range the sticker shock might be slightly less.
Highly unlikely. See, what you don't realize is that this technology will likely be utilised in memory before processors.
Not very likely. Memory manufacturing requires large volumes. This means large wafers and few process stages. Diamond wafers will not be as large as Si wafers for quite a while (200-300mm).
The first applications with these will be low volume high cost, high power applications. As the article stated RF front ends/power amps for 5-100GHz applications are likely.
(Please note that there is a lot more to achieving high clock speed of a digital circuit than just achieving high transistor frequencies. Currently transistor performance is dwarfed in importance to the limits set by interconnect and clock distribution)
1) SRAM is actually Static RAM. It's very vast but it also requires a LOT more transistors per bit than DRAM - Dynamic RAM. I do believe that SRAM also consumes more energy than DRAM (i'm not absolutly sure). Don't expect SRAM to be use in Main Memory anytime soon (unless people are willing to pay the same for 100M as they pay today for 1G - and i'm being optimistic here)
The typical SRAM structure is a 6T circuit (That is 6 transistors), while DRAM is 1T. DRAMS does however need to be refreshed with regular intervals as the capacitor that stores the bit is prone to leakage. This means the DRAM can never idle at virtually 0 power consumption.
SRAMs therefore consume a lot less power than DRAMs when there are significant idle cycles.
If there actually is a perceptible difference, it is most likely du to mismatched levels.
A volume level difference as little as 0.2dB can be percieved. You will however not percieve this as a level difference (that generally happens at around 1-2dB difference), rather it is more common to hear descriptions like 'clearer treble' or 'tighter base'.
Before you do such a comparison, make sure you match levels using somthing more precise than your hearing.
Yes they are. Ever hear the word "prototype" before?
Test and verification of prototypes are normally handled by people specialicing in that field. They do so with input from the designers, but it is not the designer that works the lab.
Right, so students need to know how to use these instruments. This falls under "laboratory skills".
If they are to do lab work, yes. If they are to do design, no. You missed the point. I was trying to illustrate that hands on in order to understand the physics is of limited value in electronics. You are allways detached from the physical result so you might as well consentrate on the theory unless you actually are trying to learn laboratory skills.
Besides you said: "understanding of design for manufacturability is required for good design engineers".
Yes, but this has nothing to do with lab skills. This deals with insuring the design works in all design corners, that you do not cause yield problems and to design so the device can be tested in a timely manner.
Just because someone knows which end of a soldering iron to hold, doesn't mean they don't know anything else
I never said that either. You are missing the point. What I said was that you do not become a better designer by knowing techicians skills.
For the record, the technicians I know are highly skilled people. It is just that the jobs we do are different.
One of the biggest problems I've seen with EE grads, is that some of them don't have any real-world experience. Sure, they can tell you the noise characteristics for a carbon resistor, but ask them to pick a 1/2 watt carbon resistor of a given value out of a bin, and they can't recognize it.
Why would he need to? Or do you suggest that MIT trains people to work on assembly lines?
While an understanding of design for manufacturability is required for good design engineers, laboratory skills is not. Illustrating the training with working examples is nice, but electronics isn't the easiest subject to illustrate in an effective manner. After all almost nothing is visible unless you use an instrument.
Approaching design with a technician mindset is in my opinion the wrong way. You do not want to fix somthing so it work, you want to find an optimum solution. No offence to technicans but design isn't the same job.
If we had some way of safely launching the waste into the sun
Now, the point was to generate usful energy, not to spend it all. Launching radioactives into the sun in itself uses a lot of energy as well as wasting the energy still present in the radioactives.
Remember that as long as it is radioactive it's energetic. Today's radioactive waste is tomorrows fuel.
Yes, in theory, LP has a high-end rolloff limited only by the equipment used - up to 40kHz is readily acheivable with a decent magnetic pick-up.
Yes you can achieve 40KHz with a lousy s/n ratio. The needle will hovever wear out and dampen HF components in the signal so after a few uses the LP will have a cutoff closer to 14-16 KHz.
Changing the sampling rate of a digital signal is non-trivial
It's not exactly hard either. It's just a matter of proper filtering.
In practice no filter can be made with a sharp enough "knee" to fit the limit, so the response typically begins to tail off around 18kHz, in line with an adult's hearing.
While this is selectable by the mastering house, there are no technical reason not to select a far steeper cutoff than that. Hell, i've designed a decimator that had flat response up to 7KHz with 16 bit resolution and 16KHz sample rate. (That is just 1KHz between passband and nyquist limit. And this was for a ultra low power, low latency application. Those are not constraints you need to take into regard in a studio environment.
(The decimator in question filtered a 2MHz/1bit DS output using a cascade of two filters with one 7th order IIR followed by a decimation by 32 followed again by a 11th order IIR and a decimation by 4. It all fit in less than 1mm^2 in 0.18um and worked on 0.9V)
Our copyright law is rather anal. Contrary to popular belieft you can't copy something for personal use at all. No exceptions.
If there are indeed no exceptions, then 'copying' must be defined rather carefully. After all to play back a CD you must make a temporary copy to the players buffer memory.
This assumes you do not exceed the technologys safe maximum voltage. High voltage in CMOS (and related) processes have other undesireable effects than just thermal problems.
Most significantly the drain-source field may become sufficiently strong to open the channel regardless of the gate voltage. When this happens the device will fail regardless of temperature.
Open GL in EDA tools? Most EDA software is mostly text-mode or at most flat graphics. There may be som e layout tools using a 3d/open GL renderer, but a few MEMS centered tools hardly qualifies the statement 'any EDA tool'.
Of cource since most EDA tools are u*ix only direct-x would be out if/when they want such a renderer.
"Or you could run FreeBSD or Linux. Or is this not Slashdot?"
The software in question runs on linux. Windows versions do not exist, though generally solaris and HP-UX versions do.
This is EDA software, for which Red Hat Linux has become pretty much defacto standard.
Don't think that just because the OS is free that the applications are. What exist of free EDA software is pretty pitiful.
To elaborate on this: A lot of slashdotters think that free software is the Answer(tm) for everyone just because the applications they know exist in good free versions. In reality this is just true for either highly mainstream applications (which also sw developers need to use) or niche software targeted at software developers or systems management. This is because the users of this software have the ability to develop these apps. (or contain people who do)
For other niches the users generally do not have the ability (or inclination) to develop software thus no free apps appear.
" Personally I think if you want to add more power just go with more machines."
That works until you realize your software licenses cost $20000 pr. CPU. That makes a couple of $100 extra to get the top of the line CPU seem kind of moot.
"Overclocking is a decent measure of hardware stability. I know I regularly look at that data when comparing hardware in reviews."
No overclocking is an indication of the margins in the particular device in the particular environment you are overclocking on.
This can be an indicator of either large process spread (That is the manufacturer has a number of devices performing better than specified but not good enough/many enough to mark them up)
It can also be an indication of the manufacturers politics w.r.t. introducing faster devices. This was particularly noticeable back before the athlon when intel had a lot less contested position. They then chose to introduce faster devices a lot slower then process technology allowed them to, resulting in larger design margins.
In the last 5-7 years the process spread has been reduced considerably, thus reducing the first effect (of cource CPUs has allways been binsorted which reduces spread in a single grade, but this also gives you another aspect where politics affect overclockability as CPUs from better bins are marked down to meet demand)
Overall I'd say the reduced yield in overclocking today is due to competition: Current CPU's are much closer to process limits than they were back in the 300A days.
Overclockers should also be aware that the 'stability' tests they commonly perform is woefully iadequate. There may be rarely used paths that fail to function in your overclocked devices. You do not have any overview of how good testcoverage your stabilitytests have but I'd be suprised if they are much better than 90%
Slashdot Mirror
Actually with parts like this (large memory arrays) they usually build them with an option to mask bad rows in memory with laserfuses.
Thus you get 2MB parts when all went peachy, and 1MB parts when some defects were detected (and masked).
There is one more reason:
If the manufacturer get a high yield in the higher grade bins, but has higher demand for lower speed grades. They may choose to marke them down rather than forcing down the price of the high-speed parts by supplying too much in excess of demand.
That is just regular die to die bonding in a multichip module.
The new thing here is to communicate only through capacative coupling avoiding having to place a huge pad and drivers for it (500-2000um^2 each). Additional bonuses is that you avoid exposing the die to the stresses of the bonding machine, you gain speed as there is much less capacitance and inductance to fight with, and possibly you can achieve a cheaper assembly method.
Modules with dies communicating this way will propably not be a end user assembly. The assemblies will still be made in a cleanroom.
And my conclusion was that raw clock speed IS the most important factor in performance, if you get your information from other sources than AMD or Apple. Because there are few applications that really use more than a small fraction of current PCs capabilities. And those applications, like AI and physics simulations, do need GHz, that is, floating-point operations per second is the most important limitation in those CPU-intensive apps.
FLOPS are not proportional to the clock frequenzy across multiple architectures. I have had a circuit simulator benchmarked on p4 vs. opterons and while the p4 3.4GHz beat a operon 2.2GHz, it did not beat it by more than 20%. By your theory it should have beat it by 50%. Also we benchmarked against a xeon 3.2GHz, which turned in a disappointing result at less than 70% of the performance.
The conclusion: For this particular application, the memory interface dominates the performance.
Note that even for applications that fits in cache, you can't just look at clock frequency as different architectures don't neccecarily retire the same amound of floating point instructions pr. clock (even under ideal circumstances)
The power-pc cores you can use in the Vertex 2 pro devices are not soft (synthesizable) cores. They exist as fixed cells on the FPGA array.
That a core is synthesizable does not just mean you can place it in a FPGA. It also means it can be targeted for any logic process.
I've frequently used soft cores in conjuction with my own logic ON asic/assp devices.
The advantage of soft cores are that they are easily retargetable to new technologies and is easier to integrate in a design as you don't need to make special provisions in floorplanning to fit it.
I think it's just the first production ZigBee chip, which, until now, has been total vaporware
Actually we (Chipcon) launched a 802.15.4 compliant device in november last year. Datasheets and reference designs are availible here .
Xilinx and other typical FPGAs are not really designed to reconfigure on the fly. Normally they are loaded once on power-on and stay that way for the duration of their usage.
CPUs on FPGAs are a bit of an anachronism really, at least the soft cores like the one you pointed to (microblaze), as you could just as well implement your algorithm in hardware rather than make a CPU, which is an incredible slow piece of circuitry, on slow hardware (FPGAs are pretty sluggish compared to standard cell or full custom devices) then run software on it.
Modern high-end FPGAs do howeer have hard core* (no, not porn) CPUs embedded. F.ex Xilinx vertex 2 pro devices have power-pc cores embedded. These are considerably faster than what you can do on the fpga array itself.
*) hard cores are fully finished designs allready targeted to a technology. The name differciates them from soft cores which are synthisizable and can be targeted to any technology.
(I don't now anymore if the color used twice is red or blue. This increases the SNL for this color.)
It is green because it is closest to the middle of the spectrum. It does more than just increase the resolution of that color yhough. It's primary purpose is to increase the luminosity resolution. This is called a bayer pattern.
Now for each quadruple of sensors the data for one pixel is generated.
Nope each photosite generates a pixel. It's color is calculated using a demosaic algorithm which uses the surrounding photosites as well. (calling this interpolation is rather misleading)
This means the bayer sensor has a luminosity resolution close to the pixel resolution, but a chrominance resolution somewhat lower. This works out fine because your eyes has pretty much the same characteristic.
This will go on until multi-layered CCDs emerge on market. These use one spot on the chip to measure all three colors by layering the sensors.
They are allready on the market. Unfortunately they are not good enough to be competitive with traditional sensors yet. While they have the same chroma and luma resolution (which might be considered wasteful), they do have a lower resolution overall due to larger photosites. I also suspect that the precision by which these detectors ca diffreciate between wavelnghts aren't too good as they are hugely dependent on the precision of the doping of the semicondctor.
"The top line Nikon has a buffer that lets you take up to 144 pics in a row by holding down the shutter button."
You are thinking of the D70. While it is able to write fast enough to keep taking pictures in normal JPEG 3 pictures pr. second without filling the buffer, it does not have room for 144 pictures in the buffer.
Nor is the D70 the top of the line Nikon. That honor goes to the D1x or D2h depending on what you want. Those have buffers in the 40 picture range. (Depending on the resolution). With 8 pictures pr. second for the D2h, this might be useful. (The D2h can alo be equipped with a 802.11b card and set to upload pictures via FTP as they are taken)
As for using huge CF cards. I would think that most photographers would not like to put quite that many eggs in one basket. Those who require extreme capacity can also go for a X-drive or a laptop.
Then again. For sports events, as you say, there may be some purpose to this. With pro-level optics for this purpose (Super teles and Super tele zooms) costing in the $1000-$5000 range the sticker shock might be slightly less.
*1 GB equals 1,000,000,000 bytes
I was thinking how can they get away with that outright lie!/i>
Actually 1 GB does equal 10e9 bytes. If you actually ment 2e30 bytes the correct term would be 1 GiB.
Highly unlikely. See, what you don't realize is that this technology will likely be utilised in memory before processors.
Not very likely. Memory manufacturing requires large volumes. This means large wafers and few process stages. Diamond wafers will not be as large as Si wafers for quite a while (200-300mm).
The first applications with these will be low volume high cost, high power applications. As the article stated RF front ends/power amps for 5-100GHz applications are likely.
(Please note that there is a lot more to achieving high clock speed of a digital circuit than just achieving high transistor frequencies. Currently transistor performance is dwarfed in importance to the limits set by interconnect and clock distribution)
1) SRAM is actually Static RAM. It's very vast but it also requires a LOT more transistors per bit than DRAM - Dynamic RAM. I do believe that SRAM also consumes more energy than DRAM (i'm not absolutly sure). Don't expect SRAM to be use in Main Memory anytime soon (unless people are willing to pay the same for 100M as they pay today for 1G - and i'm being optimistic here)
The typical SRAM structure is a 6T circuit (That is 6 transistors), while DRAM is 1T. DRAMS does however need to be refreshed with regular intervals as the capacitor that stores the bit is prone to leakage. This means the DRAM can never idle at virtually 0 power consumption.
SRAMs therefore consume a lot less power than DRAMs when there are significant idle cycles.
If there actually is a perceptible difference, it is most likely du to mismatched levels.
A volume level difference as little as 0.2dB can be percieved. You will however not percieve this as a level difference (that generally happens at around 1-2dB difference), rather it is more common to hear descriptions like 'clearer treble' or 'tighter base'.
Before you do such a comparison, make sure you match levels using somthing more precise than your hearing.
Yes they are. Ever hear the word "prototype" before?
Test and verification of prototypes are normally handled by people specialicing in that field. They do so with input from the designers, but it is not the designer that works the lab.
Right, so students need to know how to use these instruments. This falls under "laboratory skills".
If they are to do lab work, yes. If they are to do design, no. You missed the point. I was trying to illustrate that hands on in order to understand the physics is of limited value in electronics. You are allways detached from the physical result so you might as well consentrate on the theory unless you actually are trying to learn laboratory skills.
Besides you said: "understanding of design for manufacturability is required for good design engineers".
Yes, but this has nothing to do with lab skills. This deals with insuring the design works in all design corners, that you do not cause yield problems and to design so the device can be tested in a timely manner.
Just because someone knows which end of a soldering iron to hold, doesn't mean they don't know anything else
I never said that either. You are missing the point. What I said was that you do not become a better designer by knowing techicians skills.
For the record, the technicians I know are highly skilled people. It is just that the jobs we do are different.
One of the biggest problems I've seen with EE grads, is that some of them don't have any real-world experience. Sure, they can tell you the noise characteristics for a carbon resistor, but ask them to pick a 1/2 watt carbon resistor of a given value out of a bin, and they can't recognize it.
Why would he need to? Or do you suggest that MIT trains people to work on assembly lines?
While an understanding of design for manufacturability is required for good design engineers, laboratory skills is not. Illustrating the training with working examples is nice, but electronics isn't the easiest subject to illustrate in an effective manner. After all almost nothing is visible unless you use an instrument.
Approaching design with a technician mindset is in my opinion the wrong way. You do not want to fix somthing so it work, you want to find an optimum solution. No offence to technicans but design isn't the same job.
If we had some way of safely launching the waste into the sun
Now, the point was to generate usful energy, not to spend it all. Launching radioactives into the sun in itself uses a lot of energy as well as wasting the energy still present in the radioactives.
Remember that as long as it is radioactive it's energetic. Today's radioactive waste is tomorrows fuel.
Yes, in theory, LP has a high-end rolloff limited only by the equipment used - up to 40kHz is readily acheivable with a decent magnetic pick-up.
Yes you can achieve 40KHz with a lousy s/n ratio. The needle will hovever wear out and dampen HF components in the signal so after a few uses the LP will have a cutoff closer to 14-16 KHz.
Changing the sampling rate of a digital signal is non-trivial
It's not exactly hard either. It's just a matter of proper filtering.
In practice no filter can be made with a sharp enough "knee" to fit the limit, so the response typically begins to tail off around 18kHz, in line with an adult's hearing.
While this is selectable by the mastering house, there are no technical reason not to select a far steeper cutoff than that. Hell, i've designed a decimator that had flat response up to 7KHz with 16 bit resolution and 16KHz sample rate. (That is just 1KHz between passband and nyquist limit. And this was for a ultra low power, low latency application. Those are not constraints you need to take into regard in a studio environment.
(The decimator in question filtered a 2MHz/1bit DS output using a cascade of two filters with one 7th order IIR followed by a decimation by 32 followed again by a 11th order IIR and a decimation by 4. It all fit in less than 1mm^2 in 0.18um and worked on 0.9V)
Our copyright law is rather anal. Contrary to popular belieft you can't copy something for personal use at all. No exceptions.
If there are indeed no exceptions, then 'copying' must be defined rather carefully. After all to play back a CD you must make a temporary copy to the players buffer memory.
This assumes you do not exceed the technologys safe maximum voltage. High voltage in CMOS (and related) processes have other undesireable effects than just thermal problems.
Most significantly the drain-source field may become sufficiently strong to open the channel regardless of the gate voltage. When this happens the device will fail regardless of temperature.
Or any EDA tool
Open GL in EDA tools? Most EDA software is mostly text-mode or at most flat graphics. There may be som e layout tools using a 3d/open GL renderer, but a few MEMS centered tools hardly qualifies the statement 'any EDA tool'.
Of cource since most EDA tools are u*ix only direct-x would be out if/when they want such a renderer.
"Or you could run FreeBSD or Linux. Or is this not Slashdot?"
The software in question runs on linux. Windows versions do not exist, though generally solaris and HP-UX versions do.
This is EDA software, for which Red Hat Linux has become pretty much defacto standard.
Don't think that just because the OS is free that the applications are. What exist of free EDA software is pretty pitiful.
To elaborate on this: A lot of slashdotters think that free software is the Answer(tm) for everyone just because the applications they know exist in good free versions. In reality this is just true for either highly mainstream applications (which also sw developers need to use) or niche software targeted at software developers or systems management. This is because the users of this software have the ability to develop these apps. (or contain people who do)
For other niches the users generally do not have the ability (or inclination) to develop software thus no free apps appear.
" Personally I think if you want to add more power just go with more machines."
That works until you realize your software licenses cost $20000 pr. CPU. That makes a couple of $100 extra to get the top of the line CPU seem kind of moot.
Because it would get awfully crowded in the tropics if all us hairless monkeys were to move south for the winter.
Wrongo.
Heat spreaders hinder thermal dissappation, they do ot help.
What they di is to privide a measure of physical protection for the fragile core.
"Overclocking is a decent measure of hardware stability. I know I regularly look at that data when comparing hardware in reviews."
No overclocking is an indication of the margins in the particular device in the particular environment you are overclocking on.
This can be an indicator of either large process spread (That is the manufacturer has a number of devices performing better than specified but not good enough/many enough to mark them up)
It can also be an indication of the manufacturers politics w.r.t. introducing faster devices. This was particularly noticeable back before the athlon when intel had a lot less contested position. They then chose to introduce faster devices a lot slower then process technology allowed them to, resulting in larger design margins.
In the last 5-7 years the process spread has been reduced considerably, thus reducing the first effect (of cource CPUs has allways been binsorted which reduces spread in a single grade, but this also gives you another aspect where politics affect overclockability as CPUs from better bins are marked down to meet demand)
Overall I'd say the reduced yield in overclocking today is due to competition: Current CPU's are much closer to process limits than they were back in the 300A days.
Overclockers should also be aware that the 'stability' tests they commonly perform is woefully iadequate. There may be rarely used paths that fail to function in your overclocked devices. You do not have any overview of how good testcoverage your stabilitytests have but I'd be suprised if they are much better than 90%