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Stretch Announces Chip That Rewires Itself On The Fly
tigre writes "CNET News reports on a chip startup call Stretch which produces the S5000, a RISC processor with electronically programmable hardware so that it can add to its instruction set as it deems necessary. Thus it can re-configure itself to behave like a DSP, or a (digital) ASIC, and perform the equivalent of hundreds of instructions in one cycle. Great way to bridge the gap between general-purpose computing and ASICs."
GO!
Je ne se quoi?
Can you imagine the virus you could write if you could change the instruction set of the cpu?
If this doesn't rempresent the death of the megahertz as a processor-benchmark standard, I don't know what will...
/. cliche, but... imagine a cluster of these!
Effective application speed was never based on a cycle count alone, because different processors can have better instruction sets for the given application. The main breakthrough here is that this chip leaves "user-definable" space in its instruction set so they can re-optimize the instruction set on the fly. Whatever you're running, its most commonly used functions can almost slide from being code to being "on the chip" and that's sure to speed up the experienced speed.
Yeah, I know its a
Give these damn chips awhile to evolve and you'll have borg nanoprobes... Beware the nanoprobes!!
And it will ship with a free copy of Duke Nukem Forever, right?
I really hate signatures, but go to my website.
we can have only one standard assembly language? the hell with java if that's the case.
I write code.
Just imagine a Beowulf Clu...oh. Skynet. Right.
Let's not do this one.
Cue "The Fly" jokes.
cool. -One step closer to Judgement Day
... wake me up when i can buy a thousand of them for $10 a piece ...
[okay, okay, so it'll be -hell- fun to design codecs and other protocols that can switch their chipset dynamically, yeah, but i'd need 1000's of them deployed to have a real reason to do it...]
; -- the corruption of government starts with its secrets. a truly free people keep no secrets. --
"I see that you are (insert processor mumbojumbo.) Would you like me to reconfigure my instruction sets?"
How is this different from FPGA's?
Thanks
-b
If I wanted a sig I would have filled in that stupid box.
Of course, there is no such thing as a universal solution and the Stretch processor does have its limits. One significant area is in "low touch" operations such as network processors. While it can certainly do the relatively simple packet inspection and transformation that switch fabrics and network processors normally handle, it is really much better suited to the heavy-duty calculation- and manipulation-intensive tasks found in "high touch" applications such as video compression. For example, H.263/264 motion estimation is capable of producing very high-quality video from a relatively small bit stream, but requires lots (and lots) of raw processing horsepower. Happily, the Stretch processor is only too happy to oblige, churning out a SAD (sum-absolute difference) operation on a tile-full of pixels for H.263 video in 43 ns (H.264 takes 83 ns).
HIV Crosses Species Barrier... into Muppets
I think we're going to have to move the crypto benchmarks back a step when this tech comes out. Not very many of us have RISC chips that are optimized for MD5 or any of the other popular crypto formulas, but if the typical consumer PC had this technology, we could all effectively have an on-demand RISC for whatever we need at the moment sitting in our PCs.
In short, the time-to-crack using consumer technologies for almost any form of crypto is about to take a step backwards. It won't "break" anything, but the brute force combinations will be able to be examined in a faster time, meaning higher standards will be needed for the same level of protection you have today.
Not surprising, these breakthroughs will always keep coming...
startup call[ed] Stretch
As soon as Ti or intel start pumping these out I'll jump onboard but with Stretch as my only source...
Is this the only technology they managed to salvage from the android's severed hand? Any interesting gears and motors at all?
Don't blame Durga. I voted for Centauri.
How can something that normally takes "hundreds of thousands of instructions" be handled in a single instruction? Surely all the same mathematical operations must take place, except for some optimization. Or is it a matter of a certain structure for computation being created in a more permanent fashion rather than being dynamically formed upon demand? Then the operations could be performed in a single cycle. On the other hand, that portion of the processor would become useless to other tasks. Or am I misunderstanding this entirely?
I tried to do something like this once, but I kept running into the problem of differential voltages in the pulse-modulated ion core. I think they must have shunted the positrons through the floating point pathways, thus creating an artificial singularity in which the laws of EE no longer apply.
I can tell my computer to go fuck itself and it will.
IANAEE, but I was just wondering if this technology provides greater advantages to unique monolithic apps as opposed to apps targeted for virtual machines such as the JVM or CLR. Those VMs are general-purpose, and maybe apps that run on them would be "invisible" to the hardware reprogrammability... however I don't know how just-in-time native compilation might change that picture. Anyone with knowledge of this stuff care to enlighten?
Read my keyboard review.
It's called DISC, Dynamically Reconfigurable-Set Computer. It's existed for a few years now. If I remember correctly, there is a group at Berkley working in the area and have released a few nice papers on it.
At least this one doesn't claim to be bulletproof and be able to adapt to any situation conceivable instantly without loss of information or ability to continue operating. I seem to recall something like that popping up a number of years ago.
If it works in theory, try something else in practice.
I remember a project where hardware engineers setup a cpu to modify itself until it learned to do a task by itself. It got to the point where the hardware was doing the right thing, but not because the hardware was reconfigured properly, but because the software was using minute naunances in the electricity flowing through to get the job done. Even the hardware designers had no idea how it could possible be working
I like to welcome our new reprogrammed overlords...
A morning without coffee is like something without something else.
... earth to slashdoid,
...
being code to being "on the chip" and that's sure to speed up the experienced speed.
first, where exactly is code run, if it isn't 'on a chip', and second, what? speed up the experienced speed?
you mean, as opposed to something like 'pretended speed', which is what i imagine you were using to measure your rapid desire to let your undoubtedly 'speedy' fingers get through your slashdot post without thinking
'experienced speed' indeed...
; -- the corruption of government starts with its secrets. a truly free people keep no secrets. --
...I sense another Transmeta coming on...
Yes sure, rewirable chips would be cool for certain applications, but how does one go about making it deal with multiple applications with multiple needs? You'd over load the CPU with a truckload of specialized instructions - which would probably slow it down. Granted, I see uses in things like mobile phones, but for multitasking machines, a 'Jack of all trades' chip is the way to go.
From what I gathered, this allows the compiler to create an instruction that can do a lot of work in one instruction, NOT for the processor to decide to create an instruction. Think of it this way, if you know you need to do something like an array multiply many times, the compiler could create an instruction for it, and then use it as needed. The key to this is that the instruction set can be optimized on a program basis, so you don't waste gates on SSE2 instructions if you don't use them, etc.
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This would compare with FPGA's I believe in that most FPGA applications are fixed once loaded, although I know that there was talk about stargate systems on slashdot (http://slashdot.org/article.pl?sid=03/02/15/1629
using FPGA's for general processing before.
what does CNET, RISC, DSP, and ASIC stand for again?
Wow! The virus could execute arbitrary code! Just like if it could choose which of the existing instructions were executed by another processor. The core part of your virus could run faster, maybe in just one clock cycle!
It sounds interesting enough that I wouldn't mind buying one to play w/ or port an os to. Their numbers of their 300mhz chip outperforming a 2ghz chips makes sense if the instruction set has been changed for a single purpose. A coworker pointed out that task switching can't be that speedy. So a general purpose chip that can automatically tune itself to a specific purpose is how this comes across. Still, this can be useful.
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The article seems to imply that it works in manner comparable to having 2 processors. I had a box at home with a dual processor set up, and it had some problems running certain applications and just made things more difficult. It will be interesting to see if this chip works in the same way, as the article seems to say.
_____
Thank you.
The concept of a programmable hardware device isn't all that new. And the encoding and encryption they talk about speeding up is a typical application of PLD's. High end routers use similar devices to optimize their tables etc. Kuro5shin has a nice article for beginners. http://www.kuro5hin.org/story/2004/2/27/213254/152
Hardware manufacturers that need special hardware operations (IE MPEG-2 decoding) use dedicated, custom hardware for large volume production. Dynamically configurable hardware is expensive for large scales production, and small scale production will likely use FPGA for similar effect. I may be sceptical, but I doubt it'll catch on.
biopowered.co.uk - catalytically cracking triglycerides for home automotive use since 2008. Just say no to big oil!
wasnt there something like this in the movie hackers?
Okay... so you're saying it now takes 5 trillion years, and if you could do it 1000 times as fast, it'll take 4 trillion years...
LEARN BASIC MATH
This is evolutionary, not revolutionary. Many chipmakers have offered microcontrollers and microprocessors with FPGA on chip. Often it is an extension of the I/O built into the processor, so it's not much different than an external FPGA on the processor bus. Please note that this is NOT like processors that run on the FPGA itself - these are seperate from the FPGA portion of the chip.
Stretch is different in a few ways:
It pulls the FPGA closer to the core, so that it can be utilized almost as part of the pipeline. I say almost because of the following statement in the article:
Inside the chip, the ISEF is coupled to the rest of the circuit by 128-bit buses and has 32 128-bit registers. It runs in parallel with other areas of the processor, effectively becoming a fully reconfigurable co-processor, and can be reprogrammed for new instructions at any time during operation.
So it's still fairly seperate from the processor core.
But the core itself is high performance (fast clock, a little faster than the average FPGA) and it has a very fast memory bus (again faster than the average FPGA)
The downsides are likely to be:
1) Power cost and dissipation. Since it's a slow clock, the dissipation probably won't be bad, but it's not going into a small portable machine.
2) Time to reconfigure. This isn't meant to be a general processor with task switching. Context and task switching is going to be expensive and if you plan on running two concurrent tasks which both require special instructions the entire processor will likely perform, on average, much worse than it would without the reconfigurable portion. Unless, of course, the processes were created to use the same set of special instructions so the context switch isn't more expesnsive than it is for today's processors.
So they are targetting it correctly, it seems. Specialized areas with, in general, only one task/program running at a time. Multimedia players, for example, would be great here. A digital recorder/player would work well if both the encoding and decoding portions of the code were compiled so the special instructions created wouldn't have to be changed for either application to allow playback while recording.
-Adam
I ran your "Je ne se quoi?" through the Google translator and I got "I what?".
WTF are you trying to say you stupid frog?
This sounds vaguely like the dream solution for developers. The article says:
Does that mean it can handly booting multiple OSes simutaniously? If so, how long before someone writes an app that bridges multiple OSes, allowing the equivalent of emulation, without the emulation? I don't know about the rest of you, but the potential of this chip sounds like a dream come true. And at $35-$100 per chip... it's cheaper than the processor for most systems anyway.
Anyone else smell hype and unfulfilled promises?
How long does this chip take to change itself? How often can it do it?
Might make for an interesting SMP situation.
The first processor that can add to its instruction set while operating? I think there were a few microprogrammed processors in the 70s/80s with writable control store that could do exactly that. Anybody remember PERQ workstations? Now this new gadget appears to be able to extend itself by means of an embedded FPGA, instead of plain old microcode, so it's a bit like the Xilinx Virtex II PRO series (PowerPC core with big FPGA on one chip). The really innovative thing is that you don't have to program the FPGA in VHDL or Verilog, but the C++ compiler takes care of that.
This is basically an FPGA married to a RISC processor. So if you have a bit of RISC code that can be simulated using the FPGA portion, and you have enough spare cells to add it, and it takes 10 clock cycles for the FPGA "user instruction" to dispatch, but it takes 200 to do it outright in the original RISC instructions, then you're experiencing a 20 to 1 speed increase for that bit. You speed up the function without overclocking. Actually what you've done is "trade off".
He could have posted clearer, if he wasn't trying for first post.
THIS THING CAN TURN ON A DIME, MACROSSZERO STYLE ALSO FUCK BETA, ~NYORON
One of the best applications for this chip is a programmable Graphics card.
Imagine the optimizations that you could do for the next release of the Doom engine. They could own the market for GPUs that optimizes itself for specific games. Could be amazing.
Sunny
Be my Friend
There is a much, much better article with lots more detail on EETimes.com.
I can just see this processor, mixed with a bit of Mark Tildens analog AI research to really advance Artificial Intelligence. For the uninitiated Mark Tilden discovered that by tying a group of only four or so transistors and sending a regular analog signal through it he could get small robots to walk, and indeed do an amazing number of things, including optimize it's path and even remember it's solution for a small amount of time(about 3 or 4 seconds). Not only that but when given a certain stimulus need (example make them solar powered and have only one are of light they would compete with other bots to gain access to better light. Indeed a lot of the behavior that these little bots produce is so complex and life like that he has spent a long time just documenting behaviour. Now give a set of these bot's circuits the ability to "optimize" the speed of the signal, and a few stimuly and let it play. If the stimulous was for "human approval" some input from a human indicating good or bad.... Heck what do I know, I'm non AI researcher but it always sounded cool to me :-)
For more information on Mark Tilden go to
BEAM Online
This is not a sig
reminds me of Starbridge and this and this previous slashdot stories. I have always been interested in the subject, unfortunately in most of the cases similar products end up as vaporware
I thougt they made sneakers.
We suffer more in our imagination than in reality. - Seneca
AKA Where are they now?
It's curious. When I was looking at semi companies a few years back, there seemed to be lots of scrappy startups with reconfigurable dreams. I looked at companies that could take c++ code and turn it into silicon, companies that had tools to integrate IP from multiple providers easily, and FPGA producers that wanted to grow beyond the primarily telecom market that they were in.
The idea was plausible, the market and the VCs (at least in Europe) agreed, and lots of money was thrown at the problem.
But if I look at this company, I can't help but feel that it's a bit of deja vu.
Which begs the question, if reconfigurable computing is such a good idea why has it not become as common as the general purpose CPU? I suspect it's because the general purpose CPU is:
1. cheap
2. well understood
3. cheap
Simply put, it's often cheaper to just write code for one of the myriad existing parts or, in the case that you want to have something that's got a custom core, just have it fabbed.
Am I missing something here?
EE Times has an article here. Apparently this chip has a competitor. There's also more details about the chip itself.
(Anonymous because logging in at work)
This is a start up. This is their first product. They've called it the S5000. Wtf?
How about the S1, S0 or something?
I do wonder how they deal with heat dissipation. :-)
That insanely complicated piece of software that can automatically figure out what it needs the chip to do at any given time for its own survival --
oh yeah, we have those... PEOPLE! Now, can I get those neural processor connects and graft this thing to my head already?
stuff |
Nothing radically new..
The ability to dynamically reprogram on the fly in-circuit sounds cool though.
---- Booth was a patriot ----
looks like we'll have skynet operational anytime now...
e.
Build Your Own PVR/HTPC news, reviews, &
Or maybe the world is just running out of good project names.
Project STRETCH
http://en.wikipedia.org/wiki/IBM_7030
Wait a minute. Didn't I say that on the other side of the record? I'd better check
The chip combines an existing RISC (reduced instruction set computing) architecture with a large reconfigurable area of programmable logic called the Instruction Set Extension Fabric... I don't get it. It seems to me as if what gets put into the "large reconfigurable area" would almost be a macro that would still call the standard instruction set of the RISC processor. So what makes it so much more efficient?
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Pretty skimpy blurb - I suspect that the product is either a) vapourware or b) a lot more limited than is discussed in the article.
From the article, I presume that the processor's microinstruction memory can be updated with special information embedded in the executable file. This is not as unique as you might think: virtually all Intel and AMD processors have the ability to have their microinstruction memory updated during the boot process - this is used up upload microinstruction updates/corrections without requiring a new chip. What's implied in the article's title (note, not in the text), is that this memory can be updated on the fly which, I presume, means that the instruction set changes for each process that is loaded.
The immediate questions that I have are:
1. How is this accomplished in a multi-process (ie Linux) operating environment where the op-codes given to the custom instructions in one process are the same as another? Does this mean that the microinstruction memory must be reset during task switch to avoid this problem? What is the task switch latency penalty for this process?
I suspect that only one process with custom instructions can be run at any one time and this is why the device is designed for embedded applications.
2. How do you debug these new instructions? Again, I don't read anything about the debugger in the article (part of the "Company's own C/C++ compiler"). I would expect the debugger to be critical to understanding whether or not the custom instructions work the way that is expected.
I would never consider a part which did not have simulator/emulator support and I don't know of too many people who would either, so this is a pretty important question.
3. Where is the data showing "performing encryption or digital video processing on blocks of data, can be executed in single clock cycles"?
In my experience, unless very small blocks of data are being processed, the biggest bottleneck is memory speed/latency, not the number of instruction cycles.
4. How much space is there in the microinstruction memory for the custom instruction definitions?
This has implications on the number of custom instructions that can be implemented along with the total number that can be implemented.
I can see some advantages to having custom instructions optimize specific operations in a single process embedded controller (such as the ones used in a router, in camera video compression and basic cyptography).
I don't see it being a significant threat to the current Xeon, Opteron or Itanium processored systems.
myke
Mimetics Inc. Twitter
This will be useful in places that they mentioned. Places where you do a lot of processing that takes many generic instructions but can be translated into a single string of descrete instuctions.
The more I think about it, this is the direction processors are going. We keep moving processors towards RISC based cores. We keep adding specialized paths for things such as multimedia. Eventually we WILL have half the processor being a purely RISC core and half being programmable hardware for specialized computational intensive instructions. I retract my initial view.
I do wonder though, what the life is on the hardware side. How many times can you reprogram the hardware before it starts to die. What is the error rate in reprogramming it? What happens when a few programmable transistors die?
I do security
Perhaps the most notable (in its conception, at least) was Seymour Cray's attempt at a Pentium Pro core + reprogrammable extensions (via FPGA or the like) at his post-Cray Research company. More recently, IBM licensed PowerPC cores for use by Xilinx. Up to four of those cores get thrown on the die with a Virtex-II FPGA (?); each of the cores has the ability to add opcodes in FPGA land.
Even more recently was my last company's valiant effort at something similar (and even cooler). RIP, SiliconMobius.
Thinking of starting a business in Minnesota? Me too! mnsmall.biz
Can it hammer a six inch spike into a 2x4 with it's penis?
Short answer: FPGAs let you build using basic gates and (very small) lookup tables. This lets you build anything you please, and fully optimize the number of functional units of each type that you have, but has a speed and size penalty.
This chip is basically a RISC processor with an FPGA-type fabric bolted on as a co-processor, as far as I can tell from the detail-poor press release. By implementing most of the instruction pipeline as fixed, optimized hardware, it runs without any of the penalties of a purely FPGA-based implementation. When you have a number-crunching task that would benefit from a custom logic implementation enough to offset the performance penalty of implementing it in programmable logic blocks, the compiler configures the programmable logic into a suitable coprocessor which is stuck in as an extra branch of the instruction pipeline.
How much benefit you get from this depends on what you're doing. Modern general-purpose microprocessors have enough vector instructions to handle most DSP-ish tasks without an abysmal speed penalty (just a large size and power penalty over a purely DSP-based implementation). Most computing tasks aren't limited by processing horsepower at all - they're either waiting for memory accesses to complete (even cache accesses are very slow compared to register accesses), or they're waiting for the target address of a branch to be decided (speculation and BTBs don't address this perfectly by a long shot). A reconfigurable processor would suffer from much the same type of problem. While using the programmable logic path for slice processing could remove some of the branching penalties (by following all paths and selecting the desired result), this would be at an even greater area and power cost.
For specialized applications, it would be quite useful, of course.
A quick glossary of terms being thrown around, for anyone confused:
This is a combination of lookup tables, sum-of-products combinational logic blocks, and scratch-pad SRAM that you can hook up in nearly arbitrary ways to produce custom circuits at a gate level. Bulky and slow, but good at implementing algorithms efficiently. Configuration information is loaded from a serial PROM chip at startup, letting you change it relatively easily.
Like an FPGA, but stores configuration information internally, so you need to take out the CPLD and burn it to change configuration instead of re-burning the configuration PROM.
Little cousin to CPLD. This is what you played with in second or third year. Typically these are just a sum-of-products combinational logic block with a register stuck on the end to latch the output. Useful as glue logic.
This is an integrated circuit that's half-made. A number of gates and registers and so forth have been fabricated on the chip, and the lowest few metal layers have been used for internal routing for these, but you get to define the upper metal layers to form arbitrary connections among these (either as the last fabrication step, or by laser-cutting a pre-fabricated wiring mesh to leave the geometry you want). Works much like a CPLD, but the design is decided at fabrication time and cannot be changed. Faster and less bulky than a CPLD implementation.
This is a custom-fabricated integrated circuit that uses cells from a standard library of components, usually automatically placed and routed from a VHDL or Verilog description of what you want the chip to do. Faster than an ASIC if you have good place and route software, but more expensive in small quantities because you're making what amounts to a full custom chip. Design time is much less than a fully custom design would be, though (but verifying that the design description is correct is a royal pain).
I hope this clears things up for anyone who was confused.
Natural questions come to mind like how quickly does the chip configure itself to optimize for the application, does the configuration only occur at start of the application, how many chip-configuring applications can it run concurrently, will it optimize for interpreted languages, can some configurations be made "permanent" to accommodate the OS used. I can see how this chip would optimize some specialized tasks, but I don't know if it will run well in an evironment where many different types of tasks are expected to run at the same time.
Another issue relating to the gaining acceptance is whether Stretch releases specs so that others can write their own compilers. Is Stretch pursuing a pure hardware strategy (not trying to sell compilers, create their own OS, etc)?
well sorta.
Star Bridge Systems has been selling computers that reconfigure their own logic (with the help of compilers) for about 5 years now. True, their solution isn't a single chip, but the idea of reconfigurable computing is not at all new, and Star Brigdes implementation appears to be even more flexible.
General purpose CPUs are fast, ubiqutous, and cheap. While compelling, this new approach is in no sense a slam-dunk in the market. Stretch will have to show a compelling case why this is a faster and cheaper alternative to the x86 (compatible) hegemony.
Sounds like this would be a perfect processor for emulating consoles such as the SNES, XBOX, GameCube, PS2, etc etc or pretty much any other processor.
Any new processing alternative has to show better price/performance than what people can get today. Remember Transmeta? While they have had small successes, by no means have they take considerable share from Intel and AMD.
It better be extremely well engineered, or these new instruction sets might raise the power usage of the processor beyond whatever's in place to provide it, or even to wick it away.
tasks(723) drafts(105) languages(484) examples(29106)
This reminds me of Field Programmable Gate Arrays. Can someone explain the difference?
The same way you detect a virus on any machine that has been compromised, with another machine and or a thorough understanding of normal operation and running processes. Nothing new here. Evaluate the harm done by a potential compromise and take steps accordingly.
There is no practical difference between a hardware and a software compromise and the remedy is the same. Indeed, for critical purposes, there's little difference between a hardware compromise and a simple failure. You should anticipate it and not get burnt. The bottom line is know your shit and be in control when strange things happen.
Security is a process and must be applied system wide. If you don't have reasonable configuration control, you are already lost. If you run junky closed software that's full of bugs and does not keep track of uid, pid or processes themselves you are always in for a rough ride. The trouble given you there will distract your operators, like it did for the last big blackout. Every piece has to be taken considered in context. It's not hard, it just takes time, organization and judgment.
I hate how Ludites always look at any new tool and cry out, "look how awful [insert wonderful new power] is!"
Friends don't help friends install M$ junk.
Looking at their brochure, it is based on Tensilica Xtensa technology (www.tensilica.com) which I know has been around for atleast 3 years. Nothing remarkable. Many companies have developed similar products.
It takes a normal program and magically morphs it into the least efficient program for the specific CPU you are using via JIT.
I seem to recall that Microsoft and some other companies were looking at using a complex operation to be computed out before an email were sent to slow down spam operators. Wouldn't this enable those same spammers to dedicate physical hardware towards completing those puzzles in a matter of nanoseconds.
Back to the drawing board for Old Billy...
I remember a project where hardware engineers setup a cpu to modify itself until it learned to do a task by itself. It got to the point where the hardware was doing the right thing, but not because the hardware was reconfigured properly, but because the software was using minute naunances in the electricity flowing through to get the job done. Even the hardware designers had no idea how it could possible be working
Then they let it take control of planes and stuff and eventually it woke up and tried to take over the world and kill everyone and even figured out time travel. It even made several clones of the Governor of California. People saw this as a bad thing, but in the end it was also able to create hyperflexible super hot women. People eventually destroyed it in their ignorance, but that was wrong. They were destroying a tool because of how it was improperly used in the past - instead of mass producing indestructable female love bots.
Why can't we just get intel/amd to up the on chip cache to something like 64mb?
If a p4 2ghz cost around $100, can one with 64mb cache cost only $10 more?
Further on, can we get a chip with 512mb cache for an extra $100?
halt;
What's sky net? Terminator reference? Huh?
I'm in the hole of the broadband donut.
Again Star Trek is becoming reality. STTNG had an episode with little robo-tools called Exocomps(sp) they were supposed to be able to build new neural pathways within themselves and become better tools as they practiced with specific tasks.
Eventually they generated so many pathways they becaume aware, and intelligent. I doubt we have to fear that from chips at this junkture but its comming.
Repeal the 17th Amendment TODAY! Also Please Read http://www.gnu.org/philosophy/right-to-read.html
Time to reconfigure. This isn't meant to be a general processor with task switching. Context and task switching is going to be expensive and if you plan on running two concurrent tasks which both require special instructions the entire processor will likely perform, on average, much worse than it would without the reconfigurable portion. Unless, of course, the processes were created to use the same set of special instructions so the context switch isn't more expesnsive than it is for today's processors.
May we see the return of co-processors? This could be great for personal computers, to dynamically help the CPU with various tasks...
Of course, that was only a little over 20 years ago.
FYI: Since somebody is going to ask... The original Z80000 design was killed when Zilog stalled out as a general purpose processor maker and moved into embedded processors after the bugs in the initial run of Z8001 chips and IBM's selection of the Intel 8088.
Taking more time to encrypt/decrypt isn't a problem (does anyone here notice the differance between 2.5ms and 5ms?)
I for one would notice the difference between 500 users and 250 users on an SSL server. If crypto runs at near wire speed, there goes another argument against using crypto on high-capacity servers.
If ever there was an article for one of those goatse guys to post something, THIS would be it.
I mean come on... stretch?
I need to die for posting this.
Slashdot still doesnâ(TM)t support Unicode after it was added to the HTML standard in 1997.
Does this mean that if I have a process that is caught in an infinite loop, that this processor will reprogram itself to make the infinite loop process even faster?
Good security is based upon reality and common sense. Common sense is a function of having common knowledge.
Isn't this how SkyNet got started?
What you have described for ASICs is infact Structured ASICs. ASICs are fully hardwired implementation that are synthesized from scratch - no pre-fabrication etc.
dont know why but i have allways belived that when we have a computer that can reprogram itself it will become a AI sometime in the future, just leave it alone so it can try to prosess the world.
so, what are we looking at here? the great granparent of skynet or smith?
comment first, facts later. http://chem.tufts.edu/AnswersInScience/RelativityofWrong.htm
This a power hungry chip and it is not clear what market it targets.
Both Tensilica and ARC Tech, offer processors with customizable ISAs. Since most embedded system designers know what the range of applications that will run on the system are, they statically profile these applications and customize the ISA for Tensilica.
However, it is not clear when one would want to dynamically reconfigure/customize the ISA - why do it dynamically -- especially since it makes the chip much larger (in area), much more power hungry, and more expensive.
Conceptually very interesting, but are there going to be any big buyers ??
It seems Stretch is not the only company that announced such a product today: EE Times article.
Also, keep in mind, customizable ISAs have been around for a while -- in Tensilica and ARC processors. These guys do it dynamically.
See this project, published in 1997, started a few years earlier. Also had a compiler project that targeted it with C code.
This is a simple FPGA stuck onto the processor, which is fine. You can make as much logic as you have room for on the FPGA.
The problem comes in with speed comparisons. The FPGA is NEVER going to be as fast as the logic designed onto the CPU, and it will be larger/more power hungry than the dedicated logic. It'll be more useful for DSP and matrix operations *if* you have enough room on the FPGA and enough cooling to make it worthwhile.
Otherwise, forget it.
It would be:
I, for one, welcome our new self rewirable chip Overlords!
16,777,216 comments ought to be enough for any forum!
I'm currently working on modular multiprocessor systems implemented on FPGAs, so this field is something I know something about.
Altera produce an FPGA with one or more built in ARM processors. This sounds very similar to the Scratch system, but the ARM processors are limited in connection into the fabric of the FPGA by the not particularly fast bus used with the processor. Scratch appear to have made the data transfer rate between the two parts of utmost importance, which is essential in high throughput applications like this.
Altera have also developed a softcore processor, that is one implemented entirely on an FPGA. It is highly configurable - instructions can be added, cache and memory behavior altered, buses adapted, etc. Coupled with things such as the DSP blocks (trees of multiply accumulates), a 50Mhz processor can process data in a specific task at the same rate as a general purpose processor running at 10 times the speed.
The work I'm doing is investigating the use of many of these processors on one fpga. Levels of optimisation that cannot be done with conventional multiprocessor systems will be possible. Changing the memory system to deal with specific algoriths, or bus widths between certain processors will allow much better performance.
Scratch also seems to be making a difference by claiming to have easy to use and working development tools, which is one thing that Altera cannot really claim to have done.
What is interesting is that the code compiler would do the hardware synthesis at compile time straight from the high level language. This way an mucky muck with a CS degree could program up of of these things.
It is about time to market. Network processors allow small teams of generic software designers to do the work of large skilled ASIC teams. FPGAs allow board level designers to do the work of large ASIC teams. (power and size penalties for both of these) This is just one step further.
Nothing breathtaking- but technology is driven by incremental steps.
Just imagine the speed increase!
"That's so plausible, I can't believe it!" - Leela
I'd say this is pretty old news. FPGAs have been around for quite some time, as well as other reconfigurable device technologies.
Don't become a regular here, you will become retarded. -- Yoda the Retard
How can this be 'news' ?
Though not the same as this, the Xilinx Vertex II Pro combines an FPGA and PowerPC risc core on the same chip.
The Altera Excalibur does something similar with an ARM processor core and programmable logic.
Both of these have been around for a while...
The human brain is implemented as a genetic algorithm. It probably runs on all sorts of nuances and things, which won't work if you copy and paste the design into another brain, which make it impossible to understand.
Xilinx was already offering chips that combined a processor core with an FPGA.
-jcr
The only title of honor that a tyrant can grant is "Enemy of the State."
DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century (1994)
Reconfigurable Architectures for General-Purpose Computing (1996)
Transit Note 118 Notes on Coupling Processors with Reconfigurable Logic
It takes 80-100us to reconfigure, and can be divided in half -- one half can be reconfigured while the other half is running. Note that the reconfigurable portion runs at 100MHz while the core runs at 300.
Although it's hard to imagine an embedded application that would need to have multiple simultaneous tasks with different configurations, I don't think it would be a problem to reconfigure the chip a hundred times per second if need be.
aQazaQa
An FPGA with a 603 core attached - Motorola has been shipping them for atleast 18 months. I don't remember the series number and I am not going to look it up.
They also have a 603 core with a specialized matrix computation unit attached.
I want a chip/pc that acts like a Radioshack 1000-in-one electronics kit...only better. I could program a receiver and transmitter, ...and a matter materializer.
-- Each tock of the Planck clock is a new world and here we are still life. --
Are you talking about the AMD 2901 bit (4 bit) slice
CPU's ?
AMD 2901 bit slice CPU was micro-programmable and
I have know of it at least since early 80's
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