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PCI 3.0 Coming; Intel gets the Green Light.
pjbass writes "This story on ZDnet discusses the next I/O subsystem planned for PC's. It will be PCI 3.0 once making it to the consumers, but it is now known as Arapahoe, or 3GIO. Intel Corp. is responsible for making the technology, and boast its performance will be about 6 times that of PCI2.x, getting up to speeds of 6.6 gigabytes per second of bandwidth initially, with promises to scale more once the technology is mainstream."
It is done by a consortium, led by Intel - but not run exclusively by them - even AMD are on board with it. I think you can safely assume that a published spec will be available (if one is not already around?).
One thing I was wondering though - is what use is HyperTransport? I always thought that it was marketed as a replacement bus architecture, but I guess not given that they want 3GIO as well!
Reading it closely makes me feel as if AMD is trying to curry favor with Intel
or maybe AMD realizes that Intel owns the market and to not support PCI 3.0 would mean PITA for hardware vendors and suicide for AMD.
cpeterso
AMD also voted for this too so we'll expect support for future Athlons (or more likely the Hammer). In the meantime Hypertransport is here for us to enjoy
---
Don't confuse Hypertransport functionality with PCI 3.0, as an eetimes article explains AMD's logic for voting to support the new intel standard, http://www.eetimes.com/story/OEG20010803S0080
Reading it closely makes me feel as if AMD is trying to curry favor with Intel for some odd reason while at the same time promoting their own technology.... They do overlap in a few areas, but I am curious if their support for the new PCI 3.0 standard will make it harder for them to sell HT as they will have to work to differentiate it.
* Winners compare their achievements to their goals, losers compare theirs to that of others.
Actually, it is possible... Ever hear of multifunction cards? (i.e. quad ethernet) Then again, they probably just use their own PCI bridge chips to give them more bus...
Not to quibble, but while this might have been true a long time ago, it's certainly not true today. In a Sun Fire 6800 you can't write from memory to PCI space at more than 150 MB/sec, which is really terrible for a 64/66 PCI bus. (The PCI to memory speed in that same machine is about 370 MB/sec.)
Supposedly their next PCI controller chip will fix this problem, but that's what they said about the last one...
The last update I heard, was that AMD already had a new PCI bus (I thought it was PCI 2.0??), and the FCC was waiting on Intel. Because Intel was getting all upset that AMD had already made the standard and they weren't going to get their $$$. This was about 3 months ago, and I don't recall were I read it or I'd post it. I know the numbers are still the same (speed wise anyways), but what happened to AMD's new PCI? Did they even have one in the first place?
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You need to remember that AGP is PCI!
The AGP standard was derived from the PCI bus, but AGP is a port meaning only 1 device is hooked to the controller.
There may be a new AGP spec based on PCI 3.0, or due to it's point-to-point nature, it may not be even necessary to have a special device interface just for graphics.
In response to other posts, AGP 4X maxes out at 1.1GB/s while PCI 3.0 is initially proposed to go to 6.6GB/s and will go higher than that once the technology matures.
All in all this new spec is a Good Thing (tm)
AntiFA: An abbreviation for Anti First Amendment.
Call it "New PCI" or "Super-Duper PCI" or "Extra Whizzy PCI (not compatible with any computers made before 2001)". Please!
And don't even get me started on the trouble I've had explaining why people's "innovative" cheap storage solutions are flawed (Zip disks don't work in regular floppy drives, you can't overwrite normal music CDs now matter how good your burner is etc.).
Oh great a new architecture. How long will it take before we get PCI 3.0 2x, 4x and 8x ?
Still waiting for that fibre-optic bus. Still waiting.
Weevil
ghaa.
Besides, as long as the 3D card can render it, you can send many more polygons/second if you have 6.6 GBps of bandwidth
Another thing that comes to mind is Video Capture and processing of HDTV signals.
> I remember when I was a kid, seeing some article on Usenet circa 1990 about how it was impossible for any computer to do 30 FPS in 24-bit
If you drop it from high enough, any computer will do 30 fps before it hits the ground, without regard to its bitness.
Sheesh, evil *and* a jerk. -- Jade
Yep we will see boards with both slots. It will kind of be like boards nowadays having both ISA and PCI. It really won't be that big of a deal, the industry has done this slot switching stuff before without that much of a problem.
The nine committee members [...] had voted July 27 to take another week for company lawyers to review the standard.
WTF? Since when are lawyers qualified to decide on technology issues? I'd understand if they were to review the legalities of the standard (patents and all that crap), but the standard itself?
Next time I need to design a computer bus I'll ask my mother (a law professor). But first I'll teach her how to use scrollbars...
How about 10 Gbit ethernet? A few such interfaces should put some load on the bus, so maybe a router working with 10 Gbit could need the bandwidth.
Phobos - Greek word for fear or flight
If PCI 3.0 is going to be so much faster, what effect will that have on AGP. Will I have to go but a PCI videocard when I upgrade, or can I keep my AGP one?
I agree that motherboards will have fewer lines and thus be simpler because of the serialization of parallel lines. However, the serialization means that higher frequencies will be required for one wire to do what many parallel wires had done before. The result when moving to higher and higher frequencies is more cross-talk on the lines that are left. A good example is Rambus. From what I hear, there are lots of difficult issues with the cross-talk on the narrow bus.
JOhn
Campaign for Liberty
"The key message is that PCI software and device drivers do not have to change to be supported in the base level of Arapahoe," Tipley said. "As far as the actual link level, how electrons get across the wires, that's quite different, and obviously won't be the same PCI pins. It will be very similar to what a link would look like for 10 Gigabit Ethernet or InfiniBand, that kind of signaling."
I am not surprised that patents for one bus technology are reused in another bus. But that does not make the second bus a variant of the first bus. It makes sense to reuse good ideas!
EV6 IS NOT the same bus as HyperTransport. They are not even similar, except maybe for some low-level things.
EV6 does not use LVDS.
EV6 is not a bidirectional (full duplex) bus (X data lines one way, and Y data lines the other way), instead all of the data lines are use for communications in both directions (half-duplex).
EV6 is a processor (Alpha or Athlon/Duron) to northbridge bus. Hypertransport is a chip interconnection technology for the future.
EV6 is not packet driven, unlike HyperTransport.
EV6 is a point-to-point bus. Hypertransport can have 32 devices on a single bus, via a hub architecture (i.e., you could say it is a lot of point-to-point busses connected together, but the addressing allows for 32 devices)
and there are such a lot of other things that are different.
You're so far off base it's incredible. And you have the specifications? Have you thought of reading them? If your job requires you to work with these busses, and you do not even know the difference between them, then I feel sorry for your employers.
One Good Thing that the article failed to mention is that fewer wires also means it is easier to design a motherboard, and expansion cards, thus lowering the overall prices of both items (once the required chipsets get into mass-production, of course). You should also be able to get more spacing between the circuit paths, which should lead to a lower possiblity of cross-talk, and better reliability.
Where's my lobbyist? Right here.
grease ----> squeaky wheel
;)
Good point. But if you maintain the wheel properly, it will probably never squeak in the first place.
rLowe
----- rL
I remember when 6 GB hard drives first hit the market. I thought to myself *no one* needs this much space. How I have been shown up.
Lawrence Lessig is my personal hero.
Here's a little suggestion...
Read the article.....
It at least answers your first question....
And I really doubt that Intell will prevent VIA from using it.....it would sort of defeat the purpose, it's intended to REPLACE PCI....and the only way it'll do that, is if it can be used in every PC....
Currently PCI is used not just in Intel machines, but Macs, Sparc workstations and others....
Advanced users are users too!
Thank you very much for that horribly uninsightful comment. There is of course no reason why it could not be backwards compatible just because it's serial.
Ir probably will not be simply because it's such a change from previous PCI that I seriously doubt that Intel wants people confused about what cards will work in what (as someone else mentioned, there are a lot of people out there would would try to shoe-horn a new card into a Pentium 75...)
Also, because it's intended to be more of a port, not a bus, one goal is to try to prevent conflicts, sharing, noise, and other things that severely limit current PCI technology.
There is no sound reason to assume that PCI 3.0 is "Foul Crap" except that you probably don't like Intel.
Get over it.
"Everything you know is wrong. (And stupid.)"
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> Reading it closely makes me feel as if AMD is trying to curry favor with Intel for some odd reason while at the same time promoting their own technology.... They do overlap in a few areas, but I am curious if their support for the new PCI 3.0 standard will make it harder for them to sell HT as they will have to work to differentiate it.
Maybe they're hoping to saddle Intel with a standard that can't compete with their own proprietary solution?
Sheesh, evil *and* a jerk. -- Jade
Tech Dept: This product is a high speed add on.
Marketing: It is the future in computing and a replacement for all your other hardware
Tech Dept: Nope, its complimentary
Marketing: It doesn't sound so good if we say that
Jumpstart the tartan drive.
Hypertransport is a variable width, bi-directional bus. It can transfer up to 12GB/s. It can be used for many things - CPU - Northbridge (as it will be used for the upcoming Hammer CPUs), Northbridge - SOuthbridge, Northbridge - RAM, GPU - RAM, Southbridge - RAID controller, etc.
Hypertransport is packeted. EV6 isn't. AMD license EV6 from Alpha, AMD designed Hypertransport.
Is this enough to convince you that EV6 and Hypertransport are different?
Intel=Evil Corp.
therefore
PCI 3.0 = Bad
Conformity is the jailer of freedom and enemy of growth. -JFK
I remember when I was a kid, seeing some article on Usenet circa 1990.....
It makes me chuckle to hear these young'uns talk about 1990 being a long time ago.
Back in 1980, I remember when a 40 MB drive was so big (and expensive) it was only used in a multi-user system. Now I have individual files that easily exceed that. Sometimes by several times.
So I hope nobody makes any statements to the effect "640K, that ought to be enough for anybody."
On my bookcase, I've got the drive mechanism from an old 5MB drive. It is about 40 % larger than your typical 5 inch drive mechanism today. It's 5 MB. It sounded like a jet engine starting up. And it cost --- $3000 when new. And that was the "new", "low-cost" technology.
I hope the lessons here are obvious and don't need explaining. The time will come when 6 GB/Sec will seem so limiting. After all, a holographic projection needs way more bandwidth than this. I look at the progress of the last 20 years, and I am hopeful to see where computers will be in 2010.
I'll see your senator, and I'll raise you two judges.
Which 3?
ISA is effectively dead (I know some people still use it, but more and more motherboards simply don't have a slot).
PCI 2.x is the current "legacy"
Between PCI 3.0 and HyperTransport... If PCI 3.0 is not backwardly compatible then I would expect a motherboard to probably support PCI 2.x and ONE of the other standards (most likely dependant on whose CPU the MoBo supports).
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So will the connector be backwards-compatible? Or will we return to the days of three different bus connectors? (I'm not counting AGP, since there's always just one of those).
"Ancillary does not mean you get to rule the world." --U.S. Circuit Judge Harry Edwards, speaking to the FCC's lawyer
The P4's bus is quite bandwidth hungry if I remember correctly. It isn't as efficient as the EV6. Anyway, the P4 is slowed down badly by high RDRAM latency.
Of course, the P4's FSB will be updated to be 533MHz (133x4) next year, thus getting over 4GB/s bandwidth, with faster RDRAM with more bandwidth. However DDR ram then will be faster and have even lower latencies. Imagine a dual channel DDR chipset for the Athlon that support PC2700, aka nForce 2 coming next year. A total of 5.4GB/s of bandwidth between memory and the system.
I haven't read the spec: Are there any provisions for hardware copy protection systems in this thing?
Intel's been working on hardware copy protection for IEEE 1394, so it wouldn't surprise me if they managed to sneak that garbage into PCI 3.0.
Schwab
Editor, A1-AAA AmeriCaptions
Why does a consumer machine need this when PCI 64 bit, or 66mhz hasn't gotten into the market? The 3 types of machines I ever see these slots on are servers, very high end workstations, and Apple systesm.
Also, where does PCI-X fit into all this?
Well when you have that kind of bandwidth on the PCI bus, doesn't it seem a little redundant to have the AGP port expense on the the bridge chips?
Will everyone who bought AGP 4X graphic cards have to abandon them again like they left the PCI platform before? Anyway I'm still plugging along with an old PCI card and maybe I'll be glad I stayed there.
"a powerful and unexpected ally..."
One word: graphics.
I mean, this kind of bandwidth is at least in the same league as what today's graphic chips have to their local (on-board) memory. If a board could have >6GB/s bandwidth to system RAM, that might make it feasible to do unified memory systems again. I'm not saying that would necessarily be better, but it's at least possible and might even be cheaper in some cases. Also, I for one would enjoy a world where PCs don't have a single one-of-a-kind AGP connector for the graphics board, but where I could plop in as many boards as desired with at least reasonable bandwidth.main(O){10<putchar(4^--O?77-(15&5128 >>4*O):10)&&main(2+O);}
One thing the ZDnet story doesn't mention is that unlike PCI 2.x, 3GIO will use point to point connections instead of a shared bus.
I belive that HyperTransport is better suited for connecting northbridge-southbridge-CPU together. 3GIO is for connecting add-in cards (sound-cards etc.). They do the same thing but in different areas.
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Here is a link to a FAQ about AMD's HyperTransport technology.
It works at 6.4GB/sec and looks to me like a direct competitor.
this is just getting the spec out the door
no silicon yet so many companies do not even have access to what it is
their are no third partys supplieing interfaces or anything BUT lots of archs with bus problems i.e. Bandwidth problems
EV^ aka hypertransport is here right now and their is third part silicon SUN and apple will use it to link AGP Memory CPU because it is just faster !
nice but intel still have bandwidth problems now and look to drop their prices by up to 50 % today on the P4
the BUS is the problem for them and thats where AMD rules
SUN has also had faster machines simply because the BUS was faster
oh well
regards
john jones
It's just you :-)
'Arapahoe' is likely named for where the engineers wish they were instead of slaving over design terminals in fluorescent lit rooms. The Arapahoe Basin is a ski area in Colorado:p .
http://arapahoebasin.com/contact/content.shtml#ma