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PCI 3.0 Coming; Intel gets the Green Light.
pjbass writes "This story on ZDnet discusses the next I/O subsystem planned for PC's. It will be PCI 3.0 once making it to the consumers, but it is now known as Arapahoe, or 3GIO. Intel Corp. is responsible for making the technology, and boast its performance will be about 6 times that of PCI2.x, getting up to speeds of 6.6 gigabytes per second of bandwidth initially, with promises to scale more once the technology is mainstream."
It is done by a consortium, led by Intel - but not run exclusively by them - even AMD are on board with it. I think you can safely assume that a published spec will be available (if one is not already around?).
One thing I was wondering though - is what use is HyperTransport? I always thought that it was marketed as a replacement bus architecture, but I guess not given that they want 3GIO as well!
Reading it closely makes me feel as if AMD is trying to curry favor with Intel
or maybe AMD realizes that Intel owns the market and to not support PCI 3.0 would mean PITA for hardware vendors and suicide for AMD.
cpeterso
AMD also voted for this too so we'll expect support for future Athlons (or more likely the Hammer). In the meantime Hypertransport is here for us to enjoy
---
Don't confuse Hypertransport functionality with PCI 3.0, as an eetimes article explains AMD's logic for voting to support the new intel standard, http://www.eetimes.com/story/OEG20010803S0080
Reading it closely makes me feel as if AMD is trying to curry favor with Intel for some odd reason while at the same time promoting their own technology.... They do overlap in a few areas, but I am curious if their support for the new PCI 3.0 standard will make it harder for them to sell HT as they will have to work to differentiate it.
* Winners compare their achievements to their goals, losers compare theirs to that of others.
Actually, it is possible... Ever hear of multifunction cards? (i.e. quad ethernet) Then again, they probably just use their own PCI bridge chips to give them more bus...
Not to quibble, but while this might have been true a long time ago, it's certainly not true today. In a Sun Fire 6800 you can't write from memory to PCI space at more than 150 MB/sec, which is really terrible for a 64/66 PCI bus. (The PCI to memory speed in that same machine is about 370 MB/sec.)
Supposedly their next PCI controller chip will fix this problem, but that's what they said about the last one...
The last update I heard, was that AMD already had a new PCI bus (I thought it was PCI 2.0??), and the FCC was waiting on Intel. Because Intel was getting all upset that AMD had already made the standard and they weren't going to get their $$$. This was about 3 months ago, and I don't recall were I read it or I'd post it. I know the numbers are still the same (speed wise anyways), but what happened to AMD's new PCI? Did they even have one in the first place?
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You need to remember that AGP is PCI!
The AGP standard was derived from the PCI bus, but AGP is a port meaning only 1 device is hooked to the controller.
There may be a new AGP spec based on PCI 3.0, or due to it's point-to-point nature, it may not be even necessary to have a special device interface just for graphics.
In response to other posts, AGP 4X maxes out at 1.1GB/s while PCI 3.0 is initially proposed to go to 6.6GB/s and will go higher than that once the technology matures.
All in all this new spec is a Good Thing (tm)
AntiFA: An abbreviation for Anti First Amendment.
3GIO is a serial bus while PCI is not... That alone is enough to make that foul crap known now as 3GIO from being compatable with existing cards.
we are all invisible unless we choose otherwise
Put them in a decent system with 66MHz PCI slots and/or multiple PCI busses and the computer will keep up.
fiber can be done and for a reasonable price. but intel and such are in the milking business you know.
:T:R:A:N:S:
Call it "New PCI" or "Super-Duper PCI" or "Extra Whizzy PCI (not compatible with any computers made before 2001)". Please!
And don't even get me started on the trouble I've had explaining why people's "innovative" cheap storage solutions are flawed (Zip disks don't work in regular floppy drives, you can't overwrite normal music CDs now matter how good your burner is etc.).
If Intel tried something like that, then Intel would lose tons of market share and then AMD would capitalize on it. And it would totally segment the marketplace, which is desirable to nobody.
If AMD tried something like that, almost nobody would buy it and AMD would go bankrupt trying it.
It has to be done in incremental fashion. It's safer for the consumer that way, and that is what the typical consumer has historically wanted.
Oh great a new architecture. How long will it take before we get PCI 3.0 2x, 4x and 8x ?
Still waiting for that fibre-optic bus. Still waiting.
Weevil
ghaa.
Besides, as long as the 3D card can render it, you can send many more polygons/second if you have 6.6 GBps of bandwidth
Another thing that comes to mind is Video Capture and processing of HDTV signals.
As far as I know, AGP video cards have the capability of using system RAM for graphics needs. If this new PCI doesn't support that, the AGP may stick around.
Where did my trusty PCI-X that doesn't require all new cards & was finalized over a year ago, go?
we are all invisible unless we choose otherwise
> I remember when I was a kid, seeing some article on Usenet circa 1990 about how it was impossible for any computer to do 30 FPS in 24-bit
If you drop it from high enough, any computer will do 30 fps before it hits the ground, without regard to its bitness.
Sheesh, evil *and* a jerk. -- Jade
Yep we will see boards with both slots. It will kind of be like boards nowadays having both ISA and PCI. It really won't be that big of a deal, the industry has done this slot switching stuff before without that much of a problem.
you know you've had too much physics when you read that comment and start calculating in your head...
"...through this door all my dreams come realities, and all my realities become dreams..."
Dude, PCI 3.0 is not yet available. Take a look at http://www.hypertransport.org/ AMD's new alternative to current BUS technologies. All you bus are belong to hypertransport. 12.8 GBps. Intel has been beaten on this.
The nine committee members [...] had voted July 27 to take another week for company lawyers to review the standard.
WTF? Since when are lawyers qualified to decide on technology issues? I'd understand if they were to review the legalities of the standard (patents and all that crap), but the standard itself?
Next time I need to design a computer bus I'll ask my mother (a law professor). But first I'll teach her how to use scrollbars...
No I don't like Intel, not even a little... But that has nothing to do with why I know that it would have to use new cards...
If you've looked at the spec it calls for an entirely serial approach to everything... & you see modern PCI cards are parrelel with the ability to send 32 or 64 bits every cycle... This is where we get a problem... You either have to use a buffer to handle parellel requests in a serial fashion (adds $ to use) or you have logic added to each card so that it can communicate in either Serial or Parellel mode (which doesn't work for existing cards). Think about it for awhile & you should realize that I'm right about it...
& frankly Intel has never cared if what they do forces a user to upgrade, heck Intel is the king of forcing upgrades on people just to make more money... They've used that tactic since the 386 days...
we are all invisible unless we choose otherwise
How about 10 Gbit ethernet? A few such interfaces should put some load on the bus, so maybe a router working with 10 Gbit could need the bandwidth.
Phobos - Greek word for fear or flight
If PCI 3.0 is going to be so much faster, what effect will that have on AGP. Will I have to go but a PCI videocard when I upgrade, or can I keep my AGP one?
I agree that motherboards will have fewer lines and thus be simpler because of the serialization of parallel lines. However, the serialization means that higher frequencies will be required for one wire to do what many parallel wires had done before. The result when moving to higher and higher frequencies is more cross-talk on the lines that are left. A good example is Rambus. From what I hear, there are lots of difficult issues with the cross-talk on the narrow bus.
JOhn
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erm I think you will find hypertransprt IS the bus that durons and athlons use
regards
john jones
Right, because you've actually done any of these comparisons yourself, and you're not just yammering about something someone else said about this subject that you know absolutely nothing about.
Daniel J. Kelly
"The key message is that PCI software and device drivers do not have to change to be supported in the base level of Arapahoe," Tipley said. "As far as the actual link level, how electrons get across the wires, that's quite different, and obviously won't be the same PCI pins. It will be very similar to what a link would look like for 10 Gigabit Ethernet or InfiniBand, that kind of signaling."
Hypertransport has nothing to do with the EV6 bus that is used by the Athlon and Duron. Hypertransport is an interconnect technology for on-board components. PCI (2|3) can do this, but also has a physical interface definition, the "PCI slot". Hypertransport is better than PCI2.x by a mile and more...
Very probably the computers using this bus will also have a PCI2 bus for older cards, just as today's computers have a few ISA slots.
I am not surprised that patents for one bus technology are reused in another bus. But that does not make the second bus a variant of the first bus. It makes sense to reuse good ideas!
EV6 IS NOT the same bus as HyperTransport. They are not even similar, except maybe for some low-level things.
EV6 does not use LVDS.
EV6 is not a bidirectional (full duplex) bus (X data lines one way, and Y data lines the other way), instead all of the data lines are use for communications in both directions (half-duplex).
EV6 is a processor (Alpha or Athlon/Duron) to northbridge bus. Hypertransport is a chip interconnection technology for the future.
EV6 is not packet driven, unlike HyperTransport.
EV6 is a point-to-point bus. Hypertransport can have 32 devices on a single bus, via a hub architecture (i.e., you could say it is a lot of point-to-point busses connected together, but the addressing allows for 32 devices)
and there are such a lot of other things that are different.
You're so far off base it's incredible. And you have the specifications? Have you thought of reading them? If your job requires you to work with these busses, and you do not even know the difference between them, then I feel sorry for your employers.
Is this Hemos finally responding to this? Geez, took him long enough. :)
----- rL
PCI
This comment is guaranteed*
*not guaranteed
One Good Thing that the article failed to mention is that fewer wires also means it is easier to design a motherboard, and expansion cards, thus lowering the overall prices of both items (once the required chipsets get into mass-production, of course). You should also be able to get more spacing between the circuit paths, which should lead to a lower possiblity of cross-talk, and better reliability.
Where's my lobbyist? Right here.
It would be nice to have a full 64 bit computer that doesn't have any of the 8 bit/16 bit left in it so we can get away from the limiting backwards compatability.
Doing this bit and piece at a time is just dragging out the process and going to get people more confused than if they just switched to a non-self-bottlenecking set of standards.
Or am I just dreaming?
DanH
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I remember when 6 GB hard drives first hit the market. I thought to myself *no one* needs this much space. How I have been shown up.
Lawrence Lessig is my personal hero.
Here's a little suggestion...
Read the article.....
It at least answers your first question....
And I really doubt that Intell will prevent VIA from using it.....it would sort of defeat the purpose, it's intended to REPLACE PCI....and the only way it'll do that, is if it can be used in every PC....
Currently PCI is used not just in Intel machines, but Macs, Sparc workstations and others....
Advanced users are users too!
Thank you very much for that horribly uninsightful comment. There is of course no reason why it could not be backwards compatible just because it's serial.
Ir probably will not be simply because it's such a change from previous PCI that I seriously doubt that Intel wants people confused about what cards will work in what (as someone else mentioned, there are a lot of people out there would would try to shoe-horn a new card into a Pentium 75...)
Also, because it's intended to be more of a port, not a bus, one goal is to try to prevent conflicts, sharing, noise, and other things that severely limit current PCI technology.
There is no sound reason to assume that PCI 3.0 is "Foul Crap" except that you probably don't like Intel.
Get over it.
"Everything you know is wrong. (And stupid.)"
Moderation Totals: Wrong=2, Stupid=3, Total=5.
> Reading it closely makes me feel as if AMD is trying to curry favor with Intel for some odd reason while at the same time promoting their own technology.... They do overlap in a few areas, but I am curious if their support for the new PCI 3.0 standard will make it harder for them to sell HT as they will have to work to differentiate it.
Maybe they're hoping to saddle Intel with a standard that can't compete with their own proprietary solution?
Sheesh, evil *and* a jerk. -- Jade
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Marketing: It is the future in computing and a replacement for all your other hardware
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Marketing: It doesn't sound so good if we say that
Jumpstart the tartan drive.
Will you be able to sneak your old PCI cards into this newfangled technology or no? I don't remember seeing anything in the article about that... If not, I think that it will hamper the transition to this new standard...
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I remember when I was a kid, seeing some article on Usenet circa 1990 about how it was impossible for any computer to do 30 FPS in 24-bit
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Device drivers and HAL (hardware abstraction layer).
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Oh baby baby BABY!!!
Who's you super computer, who's your super computer...baby!!!
Can't wait for these to hit the market and build a network of 3.0 spec motherboards!
-hack
PS: Gonna have to sit down now....I feel dizzy.
Got Geometrodynamics? Awe, too hard to figure out? Too bad.
Hypertransport is a variable width, bi-directional bus. It can transfer up to 12GB/s. It can be used for many things - CPU - Northbridge (as it will be used for the upcoming Hammer CPUs), Northbridge - SOuthbridge, Northbridge - RAM, GPU - RAM, Southbridge - RAID controller, etc.
Hypertransport is packeted. EV6 isn't. AMD license EV6 from Alpha, AMD designed Hypertransport.
Is this enough to convince you that EV6 and Hypertransport are different?
Intel=Evil Corp.
therefore
PCI 3.0 = Bad
Conformity is the jailer of freedom and enemy of growth. -JFK
because currently, the north and southbridge communicate with each other through PCI/PCI-X. (correct me if I'm wrong here guys).. HyperTransport is specifically designed to be the communications bus between the two chipsets, not to replace PCI for adapter cards, etc. All those devices would still talk to the chipsets through PCI, but all the 'internal' stuff would happen through HT, making the system reponse much faster since the bus isn't being choked off by some PCI card that needs the bandwith. :)
hmmmm... ok, that sounds good.. you may now start the replies if I f'd up somewhere in there. :)
Oh god... not again.
I could be wrong, but...
:)
I've read quite a number of technical reviews of both the athlon and p4 and for some reason I remember reading more than once that the bus the p4 uses has 3.2GB/sec of bandwidth whereas the EV6 bus tops out (at least right now) at 2.1GB/sec.
Doesn't this mean that the bus is more a problem now for AMD than it is for Intel? Or am I totally wrong?
Perl - $Just @when->$you ${thought} s/yn/tax/ &couldn\'t %get $worse;
Kindof like M$ holding back our technology for 4 years.
HyperTransport = chip to chip
PCI/3GIO = motherboard to expansion cards
InfiniBand = box to box
Each of these technologies are designed with differenct applications in mind and therefore different constraints and complexity. There is no such thing as a "one size fits all" bus.
"...representatives of Advanced Micro Devices [ok], Broadcom's ServerWorks division [ok], Compaq Computer [ok], Hewlett-Packard [ok], IBM, Intel [ok], Microsoft [what the hell are they doing there ?!??!?!], Phoenix Technologies [ok] and Texas Instrument [ok]."
Some big players are missing but is Microsoft doing there ???
Which 3?
ISA is effectively dead (I know some people still use it, but more and more motherboards simply don't have a slot).
PCI 2.x is the current "legacy"
Between PCI 3.0 and HyperTransport... If PCI 3.0 is not backwardly compatible then I would expect a motherboard to probably support PCI 2.x and ONE of the other standards (most likely dependant on whose CPU the MoBo supports).
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So will the connector be backwards-compatible? Or will we return to the days of three different bus connectors? (I'm not counting AGP, since there's always just one of those).
"Ancillary does not mean you get to rule the world." --U.S. Circuit Judge Harry Edwards, speaking to the FCC's lawyer
Ok, there seems to be some confusion here as to what EV6 actually is.
/Bill
EV6 is the code name for the 21264 Alpha. (Yes, EV67 is the code name for 21264A and EV68 is the code name for 21264B. And of course, EV7 is the code name for the upcoming 21364.)
AMD licensed the EV6 Bus from DEC for use with K7.
I hope this clears everything up.
The P4's bus is quite bandwidth hungry if I remember correctly. It isn't as efficient as the EV6. Anyway, the P4 is slowed down badly by high RDRAM latency.
Of course, the P4's FSB will be updated to be 533MHz (133x4) next year, thus getting over 4GB/s bandwidth, with faster RDRAM with more bandwidth. However DDR ram then will be faster and have even lower latencies. Imagine a dual channel DDR chipset for the Athlon that support PC2700, aka nForce 2 coming next year. A total of 5.4GB/s of bandwidth between memory and the system.
I haven't read the spec: Are there any provisions for hardware copy protection systems in this thing?
Intel's been working on hardware copy protection for IEEE 1394, so it wouldn't surprise me if they managed to sneak that garbage into PCI 3.0.
Schwab
Editor, A1-AAA AmeriCaptions
Why does a consumer machine need this when PCI 64 bit, or 66mhz hasn't gotten into the market? The 3 types of machines I ever see these slots on are servers, very high end workstations, and Apple systesm.
Also, where does PCI-X fit into all this?
nForce is a north/south bridge chipset that combines video, audio, and a few other features into 2 chips.. It's not the same as a new PCI standard.
"Every computer Crashes, cause Every OS Sucks.. Everything since Apple/DOS..Just a bunch of crap"
ok
I am preaching to people who should understand this
hypertransport is the same thing bought ready to go for AMD
arrrch read the spec if they tell me its differant why does the same patent end up in both ?
regards
john jones
You won't have a *good* computer until you can insert 6 PCI Cards *and* an AGP card without having an IRQ conflict...
--guru
Well when you have that kind of bandwidth on the PCI bus, doesn't it seem a little redundant to have the AGP port expense on the the bridge chips?
Will everyone who bought AGP 4X graphic cards have to abandon them again like they left the PCI platform before? Anyway I'm still plugging along with an old PCI card and maybe I'll be glad I stayed there.
"a powerful and unexpected ally..."
Does this mean no more AGP?
Life is the leading cause of death in America.
Together with IA-64, this will finally make the PC platform a "good" computer. ;)
A monkey is doing the real work for me.
Glad my comment spawned the funniest exchange i've ever read on /.
ghaa.
Then why does AMD's website always compare HyperTransport to PCI/PCI-X etc., rather than current motherboard interconnect technology (whatever that is?)
One thing the ZDnet story doesn't mention is that unlike PCI 2.x, 3GIO will use point to point connections instead of a shared bus.
That's what I was meaning - the fact that HyperTransport is considered a direct competitor to 3GIO, but yet AMD supports 3GIO as well - seems like a conflict of interests. Are they planning on dropping HyperTransport, or marketing it in some sector that 3GIO won't be used (though given the prevelance of PCI2.x, I'd be surprised with this kind of move!)
From what I can see about the 2 systems is that they can and in the future probably will coexist on system motherboards. Each providing its strengths. This will probably make for a really fast system architechure. With hypertransport being used internaly in chipsets ala the nvidia nforce and the pci3 of course for external buss communications.
I belive that HyperTransport is better suited for connecting northbridge-southbridge-CPU together. 3GIO is for connecting add-in cards (sound-cards etc.). They do the same thing but in different areas.
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Here is a link to a FAQ about AMD's HyperTransport technology.
It works at 6.4GB/sec and looks to me like a direct competitor.
this is just getting the spec out the door
no silicon yet so many companies do not even have access to what it is
their are no third partys supplieing interfaces or anything BUT lots of archs with bus problems i.e. Bandwidth problems
EV^ aka hypertransport is here right now and their is third part silicon SUN and apple will use it to link AGP Memory CPU because it is just faster !
nice but intel still have bandwidth problems now and look to drop their prices by up to 50 % today on the P4
the BUS is the problem for them and thats where AMD rules
SUN has also had faster machines simply because the BUS was faster
oh well
regards
john jones
Is it just me, or does it sound a little bit like "a rappa ho".
Inside joke or poor planning?