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Printing Chips
batty writes :"Nature has this article about a process that uses a quartz die and a laser to mechanically print features onto chips instead of photo-etching them. The article mentions engraving a silicon wafer with features only 10 nanometres in size, as opposed to 130 nanometres using photlithography, and the process is quicker, simpler, and more environmentally friendly than current processes. Which is nice."
will be featuring different advertisements?
How nice.
You keep posting articles that have already been here!
READ OTHERS' ARTICLES!
This sounds great, but how do they make the mold, what kind of wear and tear is the mold subject to? My guess is that one of these 'nano-imprint' molds is not going to last all that long.
I am assuming they are relying on something like electron beam lithography to create the imprint mold, certainly this would be a cost/time improvement over direct e-beam litho, but it all depends on longevity of the molds.
instead of photo-etching them
...
With the current technology, the photons are not used directly to etch the silicon, but it is used to act on a photo-sensitive compound, which will then protect (or not) the silicon against acid etching, ion implant,
Opus: the Swiss army knife of audio codec
... four days ago. But thanks for the link to the Nature article.
Take note of that third section: no nasty chemicals, they claim. If their claim holds, a company using this tech could make a lot of political capital from it.
Natural questions arise: just how dirty is the current process? Will the details of the method really prove to be as clean as they say?
This sounds great, but how do they make the mold, what kind of wear and tear is the mold subject to? My guess is that one of these 'nano-imprint' molds is not going to last all that long.
I am assuming they are relying on something like electron beam lithography to create the imprint mold, certainly this would be a cost/time improvement over direct e-beam litho, but it all depends on longevity of the molds.
The author of this article from Princeton was reported in the BBC as saying he thinks he can outstrip Moores Law with this new technology!
Its one damn thing before another. (Dick Bird 1999)
"It gives an unsurpassed combination of speed and resolution and isn't limited by physical laws."
Also, the tecnique will be used for a myriad of other things, including spaceships made entirely of silicon, allowing them to be freed from laws of gravity and friction.
When you hear about CPUs... they quote it in microns.. So instead of 0.13 microns (latest intel P4), it can acheive 0.01 micron. But will the circuitry actually WORK at that size? I've heard 0.01 micron is about the limit of what semiconductors will work at until quantum effects step in and ruin the party ;-)
The whole process takes just 250 nanoseconds - nearly a million times faster than the blink of an eye.
Thanks for the meaningful comparison.
In other news, computers can add 2+2 three trillion times faster than you can commute to work. More at 11.
I've had enough abrasive sigs. Kittens are cute and fuzzy.
No... this talks about using fricken' "LASER BEAMS"... ;-)
Déjà vu?
Site & blog: http://www.mayaposch.com
When you hear about CPUs... they quote it in microns.. So instead of 0.13 microns (latest intel P4), it can acheive 0.01 micron. But will the circuitry actually WORK at that size? I've heard 0.01 micron is about the limit of what semiconductors will work at until quantum effects step in and ruin the party ;-)
From previous BBC article
Besides, I wouldn't want to have Intel printing out whole motherboards on pieces of paper.
I'm the Devil the Windows users warned you about.
I did a google search and found this interesting link. Nature has this article about a process that uses a quartz die and a laser to mechanically print features onto chips instead of photo-etching them.
sheesh...
Quoth the article:
Tomorrow's microprocessors could be laser printed.
You think my HP can do it?.. Still I didnt think that the paper is pin compatible.
are you sure? i havent heard anything.
jokes are funny
And let Big Brother spy on my thoughts at all times.
You can't judge a book by the way it wears its hair.
Great, you've done the transistors at 10nm. Now how do you do the circuitry? You know, metalization, inter-layer dielectric, interconnects...
You still have to connect the damn dots. And on top of that, your first metalization layer has to be the same "feature size" as your transistors (or else it can't connect them!). So unless they figure out how to get 10nm photo masking for metal deposition, or figure out some other way to put the first metal layer down at 10nm, this is useless.
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To understand recursion, one must first understand recursion.
Try reuters.
..you've done the transistors at 10nm. Now how do you do the circuitry? You know, metalization, inter-layer dielectric, interconnects...
You still have to connect the damn dots. And on top of that, your first metalization layer has to be the same "feature size" as your transistors (or else it can't connect them!). So unless they figure out how to get 10nm photo masking for metal deposition, or figure out some other way to put the first metal layer down at 10nm, this is useless.
0.13um was last year flik. TSMC have a shuttle run for 90 nanometer process this june. Its only for digital circuit or RAM and I am pretty sure there is some yield issue but at least it WORK. Next year they will be at 75 nano I am sure... Dont give up on the old photolitho just now...
The new Scientific American magazine has a brief
article on Chou's work and related work by Willson. Has info on the men as well as the techniques.
used for 3D volume lithography replication,
wiring, circuits, xerography, storage, photonic
molecular switches, video, and many more
applications.
http://colossalstorage.net/colossal.htm
once again scientist are still thinking of
2D area flat concepts instead of 3D Volume,
maybe someday thinking might evolve !!
...which one of you fuckers killed Daryl Kile?
But is it more cost-effective? Otherwise chipmakers won't use it, and we will be stuck with a polluting and inferior technology.
Please correct me if I got my facts wrong.
she valkz
she talkz
she roundz up jews!!!!
With cheaper (more environmentally friendly) fabs, hardware will become even more commoditized which will lend to the ubiquity of digital devices in our lives.
In the current manufacturing method, the entire wafer is coated with a photosensitive material (photoresist), and then the desired image is sequentially shined onto small areas of the wafer to pattern a few die at a time (usually a 2 or 4 die group known as a field, depending on the chip size). To complete the patterning of a single wafer can take several minutes, as the stepper/scanner machine has to custom align and expose each field individually.
This patterning is done using a reticle, which is a quartz plate with the desired pattern printed on it with a chrome layer. The reticle between the light source and the photosensitive wafer surface. The reticle patterned surface never physically touches any surface, so that no defects are created. Even a single spec of dust on the chrome side of the reticle will kill all die patterned using this reticle.
Once the sequential patterning of the entire wafer surface has been completed, the wafer is sent to a developer, where the exposed photoresist is stripped off the wafer using a chemical, leaving photoresist only in the areas which were not exposed to light (areas which were under the chrome parts of the reticle).
Now let's consider the direct printing methods: One applies a polymer, similar to the photoresist but without the photosensitive chemical additives. The desired pattern is physically pressed into the polymer using a mask. This patterning stamping is repeated for each die, until the entire wafer has been processed, and then the wafer is sent on for processing (implant, etch, whatever). There is no develop process, as the image was stamped directly onto the wafer surface.
Another method uses a quartz contact surface and a laser to transfer the pattern to the wafer. This is an important distinction, between optical and direct contact patterning... the reference pattern **directly contacts the surface to be patterned**. Let's assume there are 100 fields on the wafer which need to be patterned. Now let's be optimistic and say that the stamper can last for 500 stampings. That means that every 5 wafers, you'll need a new stamper. Replacing a stamper is not going to be a simple process... and time is definitely money in the semiconductor industry. Having a tool sit idle after every 5 wafers patterned is simply unacceptable. Also, the direct contact between the stamper and the surface will result in polymer adhering to the stamper, which will cause pattern to be blocked. Think of a cookie cutter with a closed top surface... how many cookies can you stamp out before it gets clogged with dough? All it takes is for one or two features on the stamper to be clogged, and then every die patterned after that will be dead. So, if the stamper get's corrupted after 50 stampings, the remaining 450 fields in the 5 wafer patterned set will be useless. That's 200 good chips, and about 20,000 bad chips. Now take into account that modern processors have 15-20 layers of patterning required for each chip, meaning that each chip must get perfectly stamped 20 times... what are the odds of getting even 1 good die? The answer is slim to none.
As for the chemical savings, the only chemical in the photo process which is not used in the stamping process is the developer solution. Developer solution for photolithography is usually a strong basic solution (tetramethyl ammonium hydroxide is a very common developer solution, as it is water soluble). So you don't use one of the chemicals. That's like saying that by getting rid of the power steering in your car, you are saving on all that power steering fluid getting into the environment. In the big scheme of things, this is a non-issue.
Another issue is the overlay to previously printed layers. The pattern must be *precisely* aligned to the layer underneath, otherwise the electrical connnections won't be correct. Using optical patterning, the corrections can be made by tilting/rotating the reticle, varying scan speeds, and the image can be optically expanded/shrunk for scaling corrections. With direct patterning, the stamped features cannot be corrected for other than the most gross alignment issues.
In short, the use of direct patterning is interesting for the laying down of a single layer of small holes a couple of times, but getting a yielding device from it? Get real. It ain't gonna happen. The best that it could be used for is the production of things like diffraction gratings or similar single layer non-critical patterning where small defects will not affect the overall image.
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*shakehead* editing around here has the reliability of an unmodified '74 Pinto in a rear-end crash.
You have a number of implicit assumptions in your comment which I would like to query. As well as the /. article, I have read the The Economists take on the same research.
Point 1 - they are not talking about a single-die stamper. Actually they were talking about a whole-wafer stamper, created by e-beam lithography, If, as you suggest, a single stamper is good for only 500 stamps, this gives a 500:1 power boost to e-beam - good going.
Point 2, the stamping is not purely mechanical. A laser beam at a frequency at which the quartz stamper is transparent but the silicon isn't is shone through the stamper. This softens the silicon, so the stamper presses into it. No photoresist, and far less mechanical wear on the stamper. Quartz is pretty damned hard stuff, whereas softened silicon is (I guess) not - so I would guess a lifetime in the thousands or tens of thousands for the stamper, not hundreds.
Consciousness is an illusion caused by an excess of self consciousness.
This was slashdotted on June 19th !!.
click here to read the article
Lets stop the threads HERE.
Yeah, I can see where this'd be useful.
Actually, I was gonna cut off my comment ther, butt I figgered I cood right mor abowt thiz. So heer it iz. Printin' chips cood bring the price down and allow finer resolution or whatever, making it possible to put a million billion tranziztorz on a dam chip, making it possible to make chips so complicated that a program to printf "hello world" will be like a thousand gigabytes, because there'd be like 999 gigabytes of setup code to get all the transistors pointing in the right direction or something, and then like a gigabyte of code to actually do the work, and the whole damn thing'll get executed in like five days or something. It'll have like a million billion exahertz internal clock, so they'll sell it by that number and people will buy, but in reality, they'll've broken each operation into like 500,000,000,000,000,000,000,000,000 separate stages in the processor, so when it comes down to it, it'll take up like a trillion gigawatt-hours of electricity to power this processor for like a picosecond, and then the whole damn grid will meltdown, leaving us in the stoneage or something. Ooooooooooooooh well.
Yeah, you should've let me stop at that first sentence where I originally planned to stop, but, you know, whatever.
Also, let's say that the stamper can do 1 stamp per minute (aggressive, but ya gotta make some assumptions). How do you determine when the first little imprinter point snaps off, and every subsequent stamp creates a dead die. If it happens during the first several hundred wafers patterned, and the stamper isn't changed for thousands of stamps, there's going to be an awful lot of non-yielding die at end of line. That's a real bummer, because nobody buys the chips that fail sort/etest for anything more challenging than pretty keychains/ornaments.
Another problem is going to be that the surface of a wafer is *not* flat. Run a wafer through a diffusion furnace, and it warps like an album left in the sun (ok, so I'm dating myself... but the analogy is valid). Let's assume that the wafer bows up at the edges, relative to the center. If you try to press the entire wafer at once, you are going to get excessive pressures at the edges, while the center of the wafer isn't yet touched by the stamper. As a result, the center of the wafer isn't going to get any pattern, and so the center of the wafer won't yield usable die. Bummer.
Another issue is that *all* wafers end up with particles on the surface, be it aluminum, stainless steel, tantalum, or just plain old dust. What happens to the little imprinter fingers when you try to press them into a hunk of steel? I'll give you a hint, it'll be like holding your fingers out straight and punching a bowling ball... your fingers are gonna break. How well are your fingers going to be at pressing anything after that? On the wafer scale, any stamper which hits a die that has a surface defect will result in that die being defective on all subsequent pressings. More keychain ornaments, but less working chips and much less profitable.
In closing, let's consider one other little issue. In patterning, the goal is to have the sidewalls as nearly perpendicular to the surface as possible. A cross section view of a line should look like a skyscraper, with vertical sides, and not like a pyramid/trapezoid. In order to stamp and be able to extract the stamper from the imprinted surface without ripping off teeth, the impresser has to be tapered to minimize friction effects. Etchers and implanters really don't do well with tapered sidewalls on the pattern... you lose resolution of the resultant structures/implants.
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From what I know about micro-electronics (not much), the pathways would be too small to permit effective use. Something about electrons jumping pathways.
While it isn't limited by the width of a photon, it is still limited by things like the width of an atom.
Nature's article stated that a laser was used to 'liquify' silicon and then the quartz mask was pressed into the resulting mush. This doesn't make sense because (a) heat is something you dont want when doing fine patterning - thermal expansion tends to cause everything to shift by microns, and you want to work with nanometers. (b) Melting silicon and then quickly re-cooling it tends to destroy the crystal structure which is needed for semiconductors to work. Making a single Si crystal requires long, SLOW cooling. (c) Even if the previous items could be overcome, so what? Pressing a pattern into liquid Si and then cooling it gives you lumpy silicon - not a transistor. Transistors are made by putting small amounts of impurities (Phosphorus and Arsenic mostly) into the Si which changes the conductivity and the dominant charge carriers.
Sooo... Assuming that Nature really boned this one up, here's how the Scientific American version works: A thin layer of polymer (like a photoresist) is spread over the wafer, then the mask is carefuly aligned to any existing structures and placed in contact with the wafer/polymer combo. The laser is then used to cause a photochemical reaction that hardens the polymer in places where it isn't protected by the mask. The remaining soft polymer is then removed (I'm guessing there's a solvent step here - so much for the no chemical use idea) and the result is the pattern of whatever you're trying to make left in the hardened polymer. From here, you can etch, implant, or whatever other normal Si processing step you want. The main difference seems to be that the contact mask in the new process and the thin polymer layers give a higher resolution.
If anyone has more specific info or a link to a technical paper, please post it. Right now it appears that we have two major science magazines in conflict, and from my experience (I once had to build a mask generator in grad school - amazing what you can do with LabView and some old photography equipment) the SciAm version makes a heck of a lot more sense.
>I've heard 0.01 micron is about the limit of ;-)
>what semiconductors will work at until quantum
>effects step in and ruin the party
Near that point you no longer need wires for current to flow just separated metal plates that they can use as steeping stones.
The message on the other side of this sig is false.
Bah... And I thought I was going to find out how to print some food. I'm starving.
If you're religishitty, KILL YOURSELF!
metal plates? they're talking about metal atoms. There's no distinction between a "plate" and a "wire" at that small of level. It's just one atom, two atoms, three atoms, etc.
I love how in the final quote the creator says his new chip is "not limited by any physical laws".
I curious how we are going to keep these 10 nanometer machines cool. I doubt a 'sink and fan could do it reliably. Look like our future PC's are going to be housed in mini fridges.
Regjected because the defect rate was too large. What has changed?