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100x Denser Chips Possible With Plasmonic Nanolithography
Roland Piquepaille writes "According to the semiconductor industry, maskless nanolithography is a flexible nanofabrication technique which suffers from low throughput. But now, engineers at the University of California at Berkeley have developed a new approach that involves 'flying' an array of plasmonic lenses just 20 nanometers above a rotating surface, it is possible to increase throughput by several orders of magnitude. The 'flying head' they've created looks like the stylus on the arm of an old-fashioned LP turntable. With this technique, the researchers were able to create line patterns only 80 nanometers wide at speeds up to 12 meters per second. The lead researcher said that by using 'this plasmonic nanolithography, we will be able to make current microprocessors more than 10 times smaller, but far more powerful' and that 'it could lead to ultra-high density disks that can hold 10 to 100 times more data than today's disks.'"
what ever happened to smart chips?
he who controls the spice controls the universe
The problem is this: when will it be cheap enough to be used as a process for the chips we use now?
They're using their grammar skills there.
every great new technology is 5-10 years away i belive
A question for the physics people out there.
At what point does Brownian motion become a serious consideration? What about tunneling electrons and other quantum-ish effects?
Job? I don't have time to get a job! Who will sit around and bitch about being broke and unemployed then?
This is Roland at his finest...
oh no it's roland
These thin chips keep breaking off in my salsa.
Ginga no Rekshiya Mata Each page.
Do current chip manufacturers like Intel and AMD work on new lithography techniques, or do they focus more on architectural changes?
It seems that they shrink their process at a fairly slow rate, and both companies seem to do it at about the same speed.
Also, if they both have been just advancing the standard techniques using high frequency light to etch all the chips, how easily could they change their manufacturing process over to something radically different?
Seeing chips with 100 times more density would offer incredible benefits for speed and power savings, seeing the recent changes that the 65nm to 45nm process has brought. Hopefully we'll actually be able to see this process being used inside the next 10 years though.
Just think... we'll be able to have 198 cores doing nothing, now!
Oh, you're not stuck, you're just unable to let go of the onion rings.
I thought that the real problem now wasn't our ability to get feature sizes small, but rather that at those sizes, quantum effects really start to matter.
So how does being able to produce such small features really help us?
100x Denser Chips
I thought Dorito's were dumb...
Was this developed at the Gizmonic Institute?
jsut athnoer menagiensls ltitle psrhae for you to dcoede. Why do we wtsae our tmie dnoig tihs?
One of the difficulties with a scanning technology like this is throughput -- with mask-based lithography you can expose dice with great speed, while something like this will have to scan across the entire surface of the wafer. It sounds like there's good potential for parallelization (the article mentions packing ~100k of these lenses onto the floating head), so this technology won't necessarily be as slow as electron-beam lithography, but I can't imagine it'll be cheap either. Furthermore, the software and hardware involved must be much more complex than a conventional stepper; now you've got to modulate your light-source very rapidly, rotate your wafer, and keep track of the write-head's position to sub-nanometer precision. Tool design and maintenance costs will be pretty high, I imagine.
Well, that's kinda the whole point. Given that today's transistors are 45nm or so, 10 times smaller would be 4.5nm, or about 15 silicon atoms IIRC. I think we can worry about that already.
A polar bear is a cartesian bear after a coordinate transform.
Nano-something you say? Can it possibly be used in the production of biofuels to increase homeland security against bioterrorism? If so I have a big check for you to pick up.
Not that it matters, but that's off-topic, not flamebait.
Why does it get compared to an "old-fashioned LP turntable?" It looks much like a hard drive's head in the illustration and then there's that part about air bearings later in the article.
Anyway, beside denser chips, I can already see this change how chips are made the same way digital presses changed printing. Just load a file into a computer and you're ready to go.
TBH you sound like a fruitcake, talking like that. But the paper is quite interesting. Ever heard of Robin's Theorem, by any chance? Don't see that covered.
I just had 2 fail over the weekend. I didn't lose anything vital because I had backups but everything I considered non-essential is gone (mostly just lots of VMWare images of various distros). At some point it beocmes a bitch to manage so much data.
These posts express my own personal views, not those of my employer
I just had 2 fail over the weekend. I didn't lose anything vital because I had backups but everything I considered non-essential is gone (mostly just lots of VMWare images of various distros). At some point it beocmes a bitch to manage so much data.
How old were they? I would have thought that drives young enough to be around that capacity would be nowhere near their MTBF*. Is this a reflection of a general decline in manufacturing standards? Are manufacturing standards decreasing with increased capacity? Or is there something else about these high capacity drives that reduces their reliability?
* Yes I understand that the M stands for mean and that some units fail earlier than most in order to make up that particular average. Still, a few years is well below the 100's of 1000's of hours usually quoted for modern high capacity drives.
Ahh - My eye!
The doctor said I'm not supposed to get Slashdot in it!
Don't forget the space elevator, which, according to the late Arthur C. Clarke will get built 50 years after it stops getting modded funny.
I'm a sci-fi vegan: I don't want the aliens to think we have as much right to live as the fried chickens we eat.
Meh, just found out the only reason it looked interesting, is because it's a cut-and-paste job of other peoples' abstracts. Get a life.
This is completely untrue, if a transistor fails on a CPU, that's it, there's no routing around the damage as you seem to imply.
If you'd actually read the article you referenced when queried by someone else, you'd see that was a three year study initiated in 2006, so even if that study bears fruit it'd be 5-10 years at least before it showed up in the CPUs you buy from Intel or AMD.
Do they have a solution for controling overlay error between processing layers to less than 1.25nm?
If the answer is no, this technology is dead in the water as far as IC fabrication goes. (but may have very useful applications in other nanotech fields)
As someone who works in litho, I enjoy reading about any advances in resolution, but know that any advance in resolution must be accompanied by an even larger improvement in the non-insignificant task of placing each of the 10 to 50+ patterns needed to build an IC perfectly on top of each other across the various and ever changing film layers that make up todays chips.
30 years to develop a hydrogen infrastructure. Go Chevy Volt etcetera .
the researchers that make 200-400GHz transistors today DO in fact worry very much about tunneling. (I'm thinking of InP/InGaAsP transistors)
Quantum wells are around 5-10nm wide, so anything approaching ~20nm would at least have to account for that sort of quantum effect. So density may have a difficult limit to breach, but smaller lithography certainly makes high speed transistors easier to implement on CMOS.
(EE, not physics)
As usual, the industry thinks that Moore is better.
What a depressingly stupid machine.
80 nm line width?
12 meters/second?
assume 5x5 mm die size
31250 80-nm lines spaced 80 nm apart can be laid on this die in one direction; twice that if the orthogonal direction is involved
each of these lines is 5 mm long, so their total length is 312.5 meters
at 12 m/s this will take 26 seconds per die
a 450-mm wafer, on the other hand, if treated as one big die, would take 31.5 minutes to cover in crossing lines.