Where I live they just posted the local university salaries in the paper. The president was 4th after the football coach, the assistant football coach, and the basketball coach. All of them are way over paid but I am most angry about the fact that the football coach made 4x what the president made.
I am pretty sure sure OP is referring to the fact that "4G" networks and devices that are sold come nowhere near the ITU-R's definition for a fourth generation wireless network. I know I do not get speeds anywhere near the low end of the 100Mb/s spec and getting 1Gb/s is completely impossible on my "4G" network.
Contrary to what the AC said subwavelength is not technobable. I am a lithographer. Its basically referring to being able to resolve images smaller than the wavelengths of light you are doing the imaging with. You cannot see a virus through a microscope because the visible light emitted from it has a wavelength that is too large to allow enough diffraction orders into the lens to allow it to resolve any valid features at your eye. This is the Rayleigh resolution criterion in action. In practical lithography cases we add in a K1 factor to Rayleigh's equation to quantify how difficult an imaging case is for a given wavelength and NA.
Subwavelength imaging has been around in semiconductor processing for decades with people using tricks such as off-axis illumination and phase shifting masks to allow a 365nm light source to print 200nm features or a 193nm light source to print 45nm features. If you have used a computer in the last 20 years odds are most of the critical layers were imaged using subwavelength imaging.
Looking at the pictures in the slides this looks very similar to a carbon nanotube memory process I worked on at my last job (we might have even been licensing some of the IP from these guys). We were looking for a way to shrink our microcontroller die by moving the EEPROM cells up into the metallization stacks. An additional benefit to this memory was that we would be able to increase the EEPROM memory size 2x (with a second layer of cells) with the addition of just 5 more masking layers and almost no increase in die size.
The process I worked on was nowhere near volume production when I left; but I do know we did have completely functional die with carbon nanotube memory. The one part of the process that was most challenging was dealing with the carbon nanotube spin on process. It took forever to get the right thickness uniformity and once you had it at the correct thickness you were rewarded with a material that had filled in your lithography alignment structures to the point they were almost worthless for the next patterning step. It was pretty cool tech to work on, I am glad it looks like somebody is getting it to work.
Its interesting that you say that. As somebody who works in fabs, I have always heard horror stories about the working conditions in zilogs fabs. Pretty much all of them are focused on the completely unrealistic (for semiconductor manufacturing) expectations of oil executives as to what process yields and cycle times should be. This was combined with managers that felt it was OK to stand on an employees desk and scream at them.
I work in semiconductor manufacturing. The very first place I worked out of college ran the manufacturing execution system on OpenVMS. It was a bit of an shock to get a log in to the VMS cluster on my first day as this was in the 2000s and I had only learned about VMS in my operating systems classes as a historical example. I have also noticed that the older Nikon imaging tools have OpenVMS running the main application controlling the tool.
I found OpenVMS to be a great zero frills system for doing this type of work. I am sure there are plenty of manufacturing sites that will be interested in the port to x86 so they can get some more modern (and reasonably priced) hardware to support their mission critical applications without having to start from scratch with a new system.
The article makes me think of the Hancock Tower in downtown Boston. It had all sorts of issues with the wind including the large glass panels falling from the building to the streets below.
This is just the latest round of lawsuits on this I assume they are trying to get as much cash as possible before it expires. I went to BU for my undergrad (even took solid state physics from Theodore Moustakas) and there was a similar undisclosed settlement in 2001-2002 about the same manufacturing process. The patent is not so much about having a blue LED but having a economical way to manufacture them on a mass scale.
There will also be a cost reduction from the more efficient use of the ARC (anti-reflective coating), top coats, and Photoresist applications on the larger wafers. Coat dispense volumes do not go up significantly with larger wafers in a spin coat application so you effectively get more imaging for the same volume of chemical. Seeing as many of the lithography materials are some of the most expensive in the process this benefit can be very significant. Of course controlling these thicknesses to within a few angstroms across essentially a medium pizza will be a major challenge.
Also I was pretty sure the SEMI standard was for 450mm wafers. It will be interesting to see how many people adopt the new equipment for 450mm production, because the up front costs will be astronomical.
I am not saying our extremely high incarceration rate is the primary cause for the reduction in crime. But in spite of what is commonly reported about America, crime is actually improving. I would expect if we did a similar reduction in sentences for drug offenders, and have some better support for those getting out of jail we would have gotten a bigger reduction probably at a lower cost, but being "soft on crime" does not help anyone win elections
As somebody who works in Lithography, I can let you know that they have not been using visible light for a long time. All fine resolution lithography is designed around as close to a monochromatic light source as possible. Having a significant spread in the light spectrum was just not consistent to do much below the 1.0 um feature size. This is because of the diffraction spread is very dependent on the wavelength and the fact that the photons have different energies thus reacting differently (or not at all) in the photoresist on the wafer.
Thus broadband lithography gave way to g-line (465nm visible blue) which gave way to i-line (365nm Ultra-Violet); Next was deep UV (248nm), Now 193nm is still used in state of the art systems today with lots of tricks such as immersion (where the light goes into water before it hits the wafer to increase the NA of the system) and double patterning (splitting up the image into multiple images that are combined in the etch processes after). Extreme UV is 13.5nm light is the next step but it is a very difficult light source to work with and the systems outrageous sums of money even for this industry.
What you are completely correct about is the importance of connectivity. I went from working in a dying 1xx nm CMOS fab this year to a thriving 1.0+um fab that makes wireless components. The lithographic part of the process (and just cramming more and more transistors on a die) is not the key value to our customers; its the exotic materials that we use to target more and more bands of wireless connectivity. I expect there will always be a demand in the market for more and faster transistors for pure computation. Its unfortunately no longer where the market growth is; thus the ROI on developing these technologies is looking more and more risky for businesses. What I have found interesting is that just about everybody working on the high end of the industry is pretty confident that the transistors will work at the 5nm-7nm node so there is still an incentive to head in that direction for now. After that will require some radical re-thinking about the materials used in computational machines.
My cycling experience in Colorado has been the same (ditched my car in 2010). I frequently have cars shocked that I actually stopped at a stop sign when I am commuting to work, because all of the drivers here are so used to most cyclists blowing through them without stopping. I have also had far more close calls on the biking only trails in town with people not paying attention while riding than on the streets. The right mindset for riding is "being right doesn't bring you back" so always assume all other vehicles are going to do something dangerous when on the road.
In the discussions I have had with other people that I work with in the semiconductor industry, the primary case against FD-SOI was business not technical. FD-SOI is very expensive as a starting material and the sourcing of the stuff was iffy at best when Intel decided to go FinFet. It was also questionable if it would scale well to 450mm wafers, something that TSMC and Intel really want.
Not completely true. You can get one from OWC . You will pay more for it and it is a pain in the butt to do the work but you can replace them. I do remember when working on mac hardware was easy and quick but those days are long gone.
The price has nothing to do with the lack of leverage for the fab. In semiconductors, there has been a massive consolidation of vendors as tools become more and more specialized (and thus far more expensive to design).
For example if you want to buy an immersion ArF lithography tool, you have exactly two vendors to choose from. Both 1 2 of these vendors will charge you tens of millions of dollars for a single tool, and both will make no promises about software upgrades, unless you pay for a service contract.
At the next generation if you want to buy an EUV lithography tool, you have exactly one vendor, with a nice long waiting list (of your competitors) to get a tool. So good luck trying to negotiate on the software patches for the PC attached to it. Also the last quote I heard about for one of these tools was actually over 100 Million USD.
I had the same shock seeing something from the RC journal on slashdot. I am glad they are getting the lab up and running as it was all just proposals when I moved away from Rapid City.
I hope going with ARM is successful for them; maybe enough to get them to try to make something to compete with the Tegra in the mobile space eventually.
I frequently try to talk the more technically inclined high school kids in my family/friends group into seriously thinking about an engineering degree instead of IT or Comp Sci. I got a Computer Engineering degree and initially did some work in the mixed signal design area of emphasis; but finally settled in a career doing the optics for chip fabrication. Having studied engineering fundamentals first, then moving on to how they applied to computing machines has opened up so many more job opportunities than I believe I would have had if I had gone Comp Sci.
I work in the USA for a company that makes chips for Samsung amongst others. Our normal shift is 12 hours on your feet in the fab. (on a compressed schedule, 4 days on 3 days off and then 3 days on and 4 days off, and yes I know China is doing 6/7 days a week as the norm but I also know the quality can/will suffer as we are still cheaper than our outsourced competition for their lack of quality and consistency on a cost per good die metric). Its great money for those of us who work it and many of us sign up for overtime on our days off.
Also more to the point of the article, if you are doing inspections for 12 hours in a row on anything complex, you will suck as an inspector and I would hope Samsung would not accept this as a practice in China (or anywhere for that matter) for the interest of QA for their products but maybe I am asking too much.
I saw a presentation a couple years ago at SPIE that has Intel showing cross sections from a sub 10nm process. They had completely wrapped the gate around the device to get those to work so the transistors were just tubes. In the same presentation, they were also showing that the current / voltage improvements between the 32nm node and the 22nm node were much more like the improvements from the 130nm to the 90nm nodes (65nm to 45nm to 32nm have all leaked too much to get much bang for the buck on the shrinks), so theoretically the next generation 22nm Haswell may see some clock improvements again but we will have to see as there are significant challenges in shrinking the 1st layer of metal interconnect that may sink any improvements in the transistor performance.
Also at this same conference the TSMC CEO was very confident that they could make devices that worked well at 7-8nm; the real question was could you manufacture those in a cost effective way as EUV lithography is too slow and going to triple pattern 193nm immersion is going to to be very expensive.
This story strikes me as more gloomy for Global Foundries. AMD is effectively paying to get out of their stake in the company. Last I knew Global had ST and AMD for major customers only. Now with AMD obviously unhappy with the line yields and slow execution on advanced processing nodes we can only assume that they will at least in the short term be looking to TSMC. If Global is not able to quickly back fill with orders from somewhere else their cost situation is only going to get worse. The only bright point for Global I can see is the 2012 contract not being pay for good die only, something I have never heard of in any other supply agreement in the industry. (I have seen price breaks for yield dips or non-acceptance of yields below a certain point, but nothing like pay for good die only).
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Where I live they just posted the local university salaries in the paper. The president was 4th after the football coach, the assistant football coach, and the basketball coach. All of them are way over paid but I am most angry about the fact that the football coach made 4x what the president made.
I am pretty sure sure OP is referring to the fact that "4G" networks and devices that are sold come nowhere near the ITU-R's definition for a fourth generation wireless network. I know I do not get speeds anywhere near the low end of the 100Mb/s spec and getting 1Gb/s is completely impossible on my "4G" network.
Contrary to what the AC said subwavelength is not technobable. I am a lithographer. Its basically referring to being able to resolve images smaller than the wavelengths of light you are doing the imaging with. You cannot see a virus through a microscope because the visible light emitted from it has a wavelength that is too large to allow enough diffraction orders into the lens to allow it to resolve any valid features at your eye. This is the Rayleigh resolution criterion in action. In practical lithography cases we add in a K1 factor to Rayleigh's equation to quantify how difficult an imaging case is for a given wavelength and NA.
Subwavelength imaging has been around in semiconductor processing for decades with people using tricks such as off-axis illumination and phase shifting masks to allow a 365nm light source to print 200nm features or a 193nm light source to print 45nm features. If you have used a computer in the last 20 years odds are most of the critical layers were imaged using subwavelength imaging.
Looking at the pictures in the slides this looks very similar to a carbon nanotube memory process I worked on at my last job (we might have even been licensing some of the IP from these guys). We were looking for a way to shrink our microcontroller die by moving the EEPROM cells up into the metallization stacks. An additional benefit to this memory was that we would be able to increase the EEPROM memory size 2x (with a second layer of cells) with the addition of just 5 more masking layers and almost no increase in die size.
The process I worked on was nowhere near volume production when I left; but I do know we did have completely functional die with carbon nanotube memory. The one part of the process that was most challenging was dealing with the carbon nanotube spin on process. It took forever to get the right thickness uniformity and once you had it at the correct thickness you were rewarded with a material that had filled in your lithography alignment structures to the point they were almost worthless for the next patterning step. It was pretty cool tech to work on, I am glad it looks like somebody is getting it to work.
Its interesting that you say that. As somebody who works in fabs, I have always heard horror stories about the working conditions in zilogs fabs. Pretty much all of them are focused on the completely unrealistic (for semiconductor manufacturing) expectations of oil executives as to what process yields and cycle times should be. This was combined with managers that felt it was OK to stand on an employees desk and scream at them.
I work in semiconductor manufacturing. The very first place I worked out of college ran the manufacturing execution system on OpenVMS. It was a bit of an shock to get a log in to the VMS cluster on my first day as this was in the 2000s and I had only learned about VMS in my operating systems classes as a historical example. I have also noticed that the older Nikon imaging tools have OpenVMS running the main application controlling the tool.
I found OpenVMS to be a great zero frills system for doing this type of work. I am sure there are plenty of manufacturing sites that will be interested in the port to x86 so they can get some more modern (and reasonably priced) hardware to support their mission critical applications without having to start from scratch with a new system.
The article makes me think of the Hancock Tower in downtown Boston. It had all sorts of issues with the wind including the large glass panels falling from the building to the streets below.
This is just the latest round of lawsuits on this I assume they are trying to get as much cash as possible before it expires. I went to BU for my undergrad (even took solid state physics from Theodore Moustakas) and there was a similar undisclosed settlement in 2001-2002 about the same manufacturing process. The patent is not so much about having a blue LED but having a economical way to manufacture them on a mass scale.
There will also be a cost reduction from the more efficient use of the ARC (anti-reflective coating), top coats, and Photoresist applications on the larger wafers. Coat dispense volumes do not go up significantly with larger wafers in a spin coat application so you effectively get more imaging for the same volume of chemical. Seeing as many of the lithography materials are some of the most expensive in the process this benefit can be very significant. Of course controlling these thicknesses to within a few angstroms across essentially a medium pizza will be a major challenge.
Also I was pretty sure the SEMI standard was for 450mm wafers. It will be interesting to see how many people adopt the new equipment for 450mm production, because the up front costs will be astronomical.
Actually crime in the USA is also down.
I am not saying our extremely high incarceration rate is the primary cause for the reduction in crime. But in spite of what is commonly reported about America, crime is actually improving. I would expect if we did a similar reduction in sentences for drug offenders, and have some better support for those getting out of jail we would have gotten a bigger reduction probably at a lower cost, but being "soft on crime" does not help anyone win elections
As somebody who works in Lithography, I can let you know that they have not been using visible light for a long time. All fine resolution lithography is designed around as close to a monochromatic light source as possible. Having a significant spread in the light spectrum was just not consistent to do much below the 1.0 um feature size. This is because of the diffraction spread is very dependent on the wavelength and the fact that the photons have different energies thus reacting differently (or not at all) in the photoresist on the wafer.
Thus broadband lithography gave way to g-line (465nm visible blue) which gave way to i-line (365nm Ultra-Violet); Next was deep UV (248nm), Now 193nm is still used in state of the art systems today with lots of tricks such as immersion (where the light goes into water before it hits the wafer to increase the NA of the system) and double patterning (splitting up the image into multiple images that are combined in the etch processes after). Extreme UV is 13.5nm light is the next step but it is a very difficult light source to work with and the systems outrageous sums of money even for this industry.
What you are completely correct about is the importance of connectivity. I went from working in a dying 1xx nm CMOS fab this year to a thriving 1.0+um fab that makes wireless components. The lithographic part of the process (and just cramming more and more transistors on a die) is not the key value to our customers; its the exotic materials that we use to target more and more bands of wireless connectivity. I expect there will always be a demand in the market for more and faster transistors for pure computation. Its unfortunately no longer where the market growth is; thus the ROI on developing these technologies is looking more and more risky for businesses. What I have found interesting is that just about everybody working on the high end of the industry is pretty confident that the transistors will work at the 5nm-7nm node so there is still an incentive to head in that direction for now. After that will require some radical re-thinking about the materials used in computational machines.
But this is Slashdot, NOBODY is going to actually RTFA.
My cycling experience in Colorado has been the same (ditched my car in 2010). I frequently have cars shocked that I actually stopped at a stop sign when I am commuting to work, because all of the drivers here are so used to most cyclists blowing through them without stopping. I have also had far more close calls on the biking only trails in town with people not paying attention while riding than on the streets. The right mindset for riding is "being right doesn't bring you back" so always assume all other vehicles are going to do something dangerous when on the road.
In the discussions I have had with other people that I work with in the semiconductor industry, the primary case against FD-SOI was business not technical. FD-SOI is very expensive as a starting material and the sourcing of the stuff was iffy at best when Intel decided to go FinFet. It was also questionable if it would scale well to 450mm wafers, something that TSMC and Intel really want.
Not completely true. You can get one from OWC . You will pay more for it and it is a pain in the butt to do the work but you can replace them. I do remember when working on mac hardware was easy and quick but those days are long gone.
The price has nothing to do with the lack of leverage for the fab. In semiconductors, there has been a massive consolidation of vendors as tools become more and more specialized (and thus far more expensive to design).
For example if you want to buy an immersion ArF lithography tool, you have exactly two vendors to choose from. Both 1 2 of these vendors will charge you tens of millions of dollars for a single tool, and both will make no promises about software upgrades, unless you pay for a service contract.
At the next generation if you want to buy an EUV lithography tool, you have exactly one vendor, with a nice long waiting list (of your competitors) to get a tool. So good luck trying to negotiate on the software patches for the PC attached to it. Also the last quote I heard about for one of these tools was actually over 100 Million USD.
I had the same shock seeing something from the RC journal on slashdot. I am glad they are getting the lab up and running as it was all just proposals when I moved away from Rapid City.
I hope going with ARM is successful for them; maybe enough to get them to try to make something to compete with the Tegra in the mobile space eventually.
Robert McNamara had a good quote about this in the Fog of War. If I remember he listed it as a "rule" for a life in politics.
"Never answer the question that is asked of you. Answer the question that you wish had been asked of you."
I always considered the day people stopped using Rubylith to be when we stopped doing layouts "by hand".
I couldn't agree with you more.
I frequently try to talk the more technically inclined high school kids in my family/friends group into seriously thinking about an engineering degree instead of IT or Comp Sci. I got a Computer Engineering degree and initially did some work in the mixed signal design area of emphasis; but finally settled in a career doing the optics for chip fabrication. Having studied engineering fundamentals first, then moving on to how they applied to computing machines has opened up so many more job opportunities than I believe I would have had if I had gone Comp Sci.
Also more to the point of the article, if you are doing inspections for 12 hours in a row on anything complex, you will suck as an inspector and I would hope Samsung would not accept this as a practice in China (or anywhere for that matter) for the interest of QA for their products but maybe I am asking too much.
I think it might make the world a better place.
I saw a presentation a couple years ago at SPIE that has Intel showing cross sections from a sub 10nm process. They had completely wrapped the gate around the device to get those to work so the transistors were just tubes. In the same presentation, they were also showing that the current / voltage improvements between the 32nm node and the 22nm node were much more like the improvements from the 130nm to the 90nm nodes (65nm to 45nm to 32nm have all leaked too much to get much bang for the buck on the shrinks), so theoretically the next generation 22nm Haswell may see some clock improvements again but we will have to see as there are significant challenges in shrinking the 1st layer of metal interconnect that may sink any improvements in the transistor performance.
Also at this same conference the TSMC CEO was very confident that they could make devices that worked well at 7-8nm; the real question was could you manufacture those in a cost effective way as EUV lithography is too slow and going to triple pattern 193nm immersion is going to to be very expensive.
This story strikes me as more gloomy for Global Foundries. AMD is effectively paying to get out of their stake in the company. Last I knew Global had ST and AMD for major customers only. Now with AMD obviously unhappy with the line yields and slow execution on advanced processing nodes we can only assume that they will at least in the short term be looking to TSMC. If Global is not able to quickly back fill with orders from somewhere else their cost situation is only going to get worse. The only bright point for Global I can see is the 2012 contract not being pay for good die only, something I have never heard of in any other supply agreement in the industry. (I have seen price breaks for yield dips or non-acceptance of yields below a certain point, but nothing like pay for good die only).