Ever since 65nm, it isn't even "tiny" anymore -- well, relatively speaking. We're talking ~2 uW for an AO22 gate. But again, that's the high-performance processes.
The lack of a junction is not unique, ever heard of a MOSFET, "There is no pn junction, so there is no depletion region."
I would assume the article means there's no P-N barrier. MOSFETs don't have a gate-junction but they do have 2 sets of wells. From what I could read in the article, this seems like a single sliver of silicon.
Gate leakage is an issue but the true bane of transistor power consumption is Rdson (resistance drain to source when transistor is on). The reason for the massive heat sinks and fans on processors today is not due to gate leakage its due to the resistance of the transistor channels and the various interconnects.
Yes and no. In modern high-performance ASICs -- that is, the ones that run massive heatsinks -- the leakage current is actually close to matching the dynamic current; worst case dynamic current to boot. In 45nm HP, it actually overtakes dynamic current for realistic chip operation on something like a microprocessor; since most of such a chip is idle even at full load.
Granted the future is mobile silicon and those will invariably use thick-gate processes where leakage is, once again, only a small fraction of switching current but that's at a significant sacrifice to switching frequency.
The thing to keep in mind is that dynamic current only occurs for a fraction of the clock period; leakage is constant. With clock-gating being used on just about every chip out there, it's even less of an issue.
The article itself suggests this. I'm not familiar enough with lithography to comment on the equipment -- it could very well be prohibitive -- but the actual structure of the transistor would be far simpler; making it easier in the sense that there will be less variation in process to deal with.
With no need for two junctions, there will be no danger of latch-ups; less source/drain capacitance and most importantly, the smallest feature size will no longer be just part of the transistor.
Not having access to the full article, I'm not entirely certain of the details of how this FET is constructed but from the description, it sounds like a piece of silicon surrounded by thin oxide and attached to a metal. This, in principle, is similar to dual-gate FETs, only it takes it a few steps further.
What struck me is that the article mentioned that no doping is required; which would be odd considering polysilicon isn't a semiconductor by itself.
The A8's theoretical maximum is 2 DMIPS/MHz. The P3's theoretical maximum is 3 DMIPS/MHz. In reality, I suspect the P3 is a bit ahead as it is OoO and -- if code is scheduled right -- can actually achieve the equivalent of ~5 ARM instructions (one complex instruction, 2 simple instructions can be decoded each cycle) each cycle.
The ARM is in-order and can decode/issue only 2 ARM ops per cycle. Of course, the A8 uses far fewer transistors than even the earlier P3's without its cache.
As others have said, it's better just to use the coax cable to rewire the house. Ethernet at high data rates requires a differential and high frequency cable twisted pair. Coax does not give you any of this. There's also the problem that the impedance of a coax cable is orders of magnitude greater than cat5, so you'll either have to have a high-powered driver and matching terminator at both ends or a modem.
All in all, it's not worth the effort unless someone out there has already designed something like that.
That whole philosophy went out the window when Intel couldn't make a compiler good enough to make Itanium work well in all situation; which to this day -- despite having more software engineers than silicon guys -- they still don't.
Scheduling things beforehand will only get you so much. It sounds good on paper in a "look how much silicon we save" kind of way but the reality is, explicit parallelism and static scheduling simply aren't good in this day of variable memory latencies, multi-tiered caches and people no longer programming in assembly.
There is no 3GHz ceiling; but 3GHz is the sweet spot right now. The current i7's turbo-clock themselves to near 4GHz (3.9 in some of the Lynnfields I believe) but is limited by the power envelope of its target applications (desktops).
Frequency will not be scaling much more in CMOS beyond this as transistors are not going to be getting much faster.
Power7 is also 130W+. IBM couldn't deliver a power-efficient mobile chip that was on par with Intel's offerings both in performance and power consumption, so Apple cut it. You can only false-advertise so much before people realize what BS backdrop commercials are.
Lynnfields TDP at ~65W and most of the time less, yet offers performance on low thread-counts (1-4) similar to higher end server processors. That's saying something.
As a former circuit designer, and still a CPU engineer, I can say without hesitation that I don't care about graphene. The transistors aren't the big factor anymore. Sure, smaller transistors are good to increase transistors per die, and reduce the distance between them, but wire RC delay is the big deal. Even if the Ioff goes down and Ion goes up, the speed of the chip isn't going to change much.
Sure it does. Current circuit speed is still (despite predictions) dominated by capacitance. This includes both load capacitance on the transistors themselves (which, mind you, is still not trivial compared to interconnect) and load capacitance on the metal itself.
To decrease rise and fall time you can either decrease capacitance (shorter wires) or increase the drive current, which faster transistors do.
And while transistor frequency scaling isn't overwhelmingly dominant as they were back in 0.35um, they still play a large role today. Even at 28nm (the characterization data and models are still pretty rough), net-delay for say, a fast adder is still about ~50% of the total delay.
Things aren't going to get much better than copper -- it's very good already. Even if they upgraded to slightly lower resistance silver (and talk about a reactive metal!), the delay wouldn't change much. Lower K dielectric would help too. There are some minor improvements that can be done, but we're probably talking 5% here and there, and they probably don't add up to 20%.
Graphene and Carbon NanoTubes can also be used as interconnects. When their alignment is made for them to be a pure conductor they reach near-superconductor levels of conductance at room temperature.
The problem is that processing power doesn't scale linearly with number of transistors you can fit in an area. That's the primary concern over the frequency scaling of silicon. You can cram more transistors in some space but if they can't run faster, your options are: 1. more cache 2. dual core 3. more specialized functions.
None of these will universally speed up computing like frequency scaling will.
Not really. You can have switching without reaching saturation. It just happens that we like to have digital circuits in saturation because it helps noise immunity.
Remember that there's always an upper clamp: your supply voltage.
[quote]Again, that's very easy to say in retrospect. I believe this is an almost identical situation: we have a very complex set of interactions from which we derive one number: "transistor switch speed". We believe we understand those relations well enough that we can derive a fastest speed any possible silicon design can give.[/quote]
No. We know the fastest speed of a MOSFET made with current fabrication technologies. The problem is that MOSFET (specifically CMOS topologies) has very very good characteristics that we like and the fabrication infrastructure (and tooling industry) exists amortizing the cost. There are many many other circuit topologies and manufacturing methods (silicon germanium, GaAs, etc.) that produce faster transistors. But moving to those are 1. expensive and 2. comes with their own limitations.
Graphene isn't perfect either. Aside from the difficulties in fabricating it, there's also the problem that unlike MOS, there's isn't a way (yet) to make a good graphene PFET. CMOS circuits are the way they are today because using a PFET-NFET topology works really really well for digital circuits.
Graphene (and carbon nanotubes) also have the problem that they don't really have an "off" state. There's less conductive and more conductive. CMOS at small geometries may leak current but nothing like CNT's and Graphene do. The circuits made from them are very power hungry (at least with current circuit topologies).
There's a lot of research trying to come up with better circuits to utilize the incredible on-current states without tunneling power between VDD and GND during the "off" state.
Before Ungerboeck's work, information theory seemed very clear about the fastest possible rate at which data could be reliably sent on the frequencies that would "stay on the wire" without bandwidth bleedover. Ungerboeck just demonstrated that there were artificial assumptions underlying the information coding theory on which that speed was based.
Shannon Theory very well laid out the maximum data rate that could be transmitted over a medium and Trellis Modulation did not exceed that. The fundamental limits were well known and not wrong. Implementations that existed then simply couldn't come close.
Ultimately, home internet connectivity still required a new infrastructure (thick copper lines). There were fundamental physical limitations of phone wires; those wires were replaced.
The situation with silicon is similar. We've gotten to the point where FETs can't get any thinner (and therefore, faster). Changing the semiconductor material allows better current per area but it has its own complications as well.
Well there are a few reasons the current "unlocked" market doesn't work.
1. The unlocked phones are not powerful phones. People buying these types of phones are the "I'll take anything that's cheap and works" buyers. They just want something to call someone with. Obviously, to these consumers, subsidized phone + contract is better than unlocked phone that you pay for. 2. They only work with certain networks. As you mentioned, even when you buy an unlocked phone, you're still limited by either GSM/UTMS or CMDA.
The phone Google seems to want is not a Razr-class phone; it's an iPhone class phone. This targets people who are perfectly willing to pay $300+ for their smartphone. I know I'm one of these people. I paid $300 for an iPhone and wouldn't mind paying $400 for an unlocked one that works with any carrier.
And that brings us to the question of carrier network compatibility. Luckily, this isn't a problem anymore since Qualcomm released their universal hybrid chip that works with any network in the world. I believe it's rumored that the upcoming iPhone -- a version that'll work with Verizon -- will use this.
If Google does utilize the latest and greatest hardware and actually builds an iPhone class phone with software that matches, there will be geeks lining up to shell out multiple hundreds of dollars for it.
We've been at roughly ~200ps per circuit operation for quite some time and yet processors are still getting faster. Parallel computation, what a novel idea.
With the sheer amount of tech in something like Star Trek, making it all scientifically plausible would've been very time-consuming. And it isn't necessary to what it was: political and social allegory.
There are movies that do get the science right (Sunshine) but those were science-y movies. Their purpose was to show off the science.
Star Trek was about something else entirely and complaining about how its science is inaccurate is like complaining that Dante's version of hell wasn't like how the Bible described it or that the king in The King and I didn't behave like a east-asian despot would. It simply wasn't the focus of the show.
Slashdot Mirror
Ever since 65nm, it isn't even "tiny" anymore -- well, relatively speaking. We're talking ~2 uW for an AO22 gate. But again, that's the high-performance processes.
The lack of a junction is not unique, ever heard of a MOSFET, "There is no pn junction, so there is no depletion region."
I would assume the article means there's no P-N barrier. MOSFETs don't have a gate-junction but they do have 2 sets of wells. From what I could read in the article, this seems like a single sliver of silicon.
Gate leakage is an issue but the true bane of transistor power consumption is Rdson (resistance drain to source when transistor is on). The reason for the massive heat sinks and fans on processors today is not due to gate leakage its due to the resistance of the transistor channels and the various interconnects.
Yes and no. In modern high-performance ASICs -- that is, the ones that run massive heatsinks -- the leakage current is actually close to matching the dynamic current; worst case dynamic current to boot. In 45nm HP, it actually overtakes dynamic current for realistic chip operation on something like a microprocessor; since most of such a chip is idle even at full load.
Granted the future is mobile silicon and those will invariably use thick-gate processes where leakage is, once again, only a small fraction of switching current but that's at a significant sacrifice to switching frequency.
The thing to keep in mind is that dynamic current only occurs for a fraction of the clock period; leakage is constant. With clock-gating being used on just about every chip out there, it's even less of an issue.
The article itself suggests this. I'm not familiar enough with lithography to comment on the equipment -- it could very well be prohibitive -- but the actual structure of the transistor would be far simpler; making it easier in the sense that there will be less variation in process to deal with.
With no need for two junctions, there will be no danger of latch-ups; less source/drain capacitance and most importantly, the smallest feature size will no longer be just part of the transistor.
Not having access to the full article, I'm not entirely certain of the details of how this FET is constructed but from the description, it sounds like a piece of silicon surrounded by thin oxide and attached to a metal. This, in principle, is similar to dual-gate FETs, only it takes it a few steps further.
What struck me is that the article mentioned that no doping is required; which would be odd considering polysilicon isn't a semiconductor by itself.
The A8's theoretical maximum is 2 DMIPS/MHz. The P3's theoretical maximum is 3 DMIPS/MHz. In reality, I suspect the P3 is a bit ahead as it is OoO and -- if code is scheduled right -- can actually achieve the equivalent of ~5 ARM instructions (one complex instruction, 2 simple instructions can be decoded each cycle) each cycle.
The ARM is in-order and can decode/issue only 2 ARM ops per cycle. Of course, the A8 uses far fewer transistors than even the earlier P3's without its cache.
As others have said, it's better just to use the coax cable to rewire the house. Ethernet at high data rates requires a differential and high frequency cable twisted pair. Coax does not give you any of this. There's also the problem that the impedance of a coax cable is orders of magnitude greater than cat5, so you'll either have to have a high-powered driver and matching terminator at both ends or a modem.
All in all, it's not worth the effort unless someone out there has already designed something like that.
That whole philosophy went out the window when Intel couldn't make a compiler good enough to make Itanium work well in all situation; which to this day -- despite having more software engineers than silicon guys -- they still don't.
Scheduling things beforehand will only get you so much. It sounds good on paper in a "look how much silicon we save" kind of way but the reality is, explicit parallelism and static scheduling simply aren't good in this day of variable memory latencies, multi-tiered caches and people no longer programming in assembly.
There is no 3GHz ceiling; but 3GHz is the sweet spot right now. The current i7's turbo-clock themselves to near 4GHz (3.9 in some of the Lynnfields I believe) but is limited by the power envelope of its target applications (desktops).
Frequency will not be scaling much more in CMOS beyond this as transistors are not going to be getting much faster.
Power7 is also 130W+. IBM couldn't deliver a power-efficient mobile chip that was on par with Intel's offerings both in performance and power consumption, so Apple cut it. You can only false-advertise so much before people realize what BS backdrop commercials are.
Lynnfields TDP at ~65W and most of the time less, yet offers performance on low thread-counts (1-4) similar to higher end server processors. That's saying something.
Not all computational workloads are memory-bound. Some are, some aren't.
As a former circuit designer, and still a CPU engineer, I can say without hesitation that I don't care about graphene. The transistors aren't the big factor anymore. Sure, smaller transistors are good to increase transistors per die, and reduce the distance between them, but wire RC delay is the big deal. Even if the Ioff goes down and Ion goes up, the speed of the chip isn't going to change much.
Sure it does. Current circuit speed is still (despite predictions) dominated by capacitance. This includes both load capacitance on the transistors themselves (which, mind you, is still not trivial compared to interconnect) and load capacitance on the metal itself.
To decrease rise and fall time you can either decrease capacitance (shorter wires) or increase the drive current, which faster transistors do.
And while transistor frequency scaling isn't overwhelmingly dominant as they were back in 0.35um, they still play a large role today. Even at 28nm (the characterization data and models are still pretty rough), net-delay for say, a fast adder is still about ~50% of the total delay.
Things aren't going to get much better than copper -- it's very good already. Even if they upgraded to slightly lower resistance silver (and talk about a reactive metal!), the delay wouldn't change much. Lower K dielectric would help too. There are some minor improvements that can be done, but we're probably talking 5% here and there, and they probably don't add up to 20%.
Graphene and Carbon NanoTubes can also be used as interconnects. When their alignment is made for them to be a pure conductor they reach near-superconductor levels of conductance at room temperature.
The problem is that processing power doesn't scale linearly with number of transistors you can fit in an area. That's the primary concern over the frequency scaling of silicon. You can cram more transistors in some space but if they can't run faster, your options are: 1. more cache 2. dual core 3. more specialized functions.
None of these will universally speed up computing like frequency scaling will.
Graphene in its conductive state has a much lower resistance/area than silicon semiconductors. There's also far less scattering.
This means more electrons can move through a piece of graphene than a piece of silicon of the same size per second.
Not really. You can have switching without reaching saturation. It just happens that we like to have digital circuits in saturation because it helps noise immunity.
Remember that there's always an upper clamp: your supply voltage.
[quote]Again, that's very easy to say in retrospect. I believe this is an almost identical situation: we have a very complex set of interactions from which we derive one number: "transistor switch speed". We believe we understand those relations well enough that we can derive a fastest speed any possible silicon design can give.[/quote]
No. We know the fastest speed of a MOSFET made with current fabrication technologies. The problem is that MOSFET (specifically CMOS topologies) has very very good characteristics that we like and the fabrication infrastructure (and tooling industry) exists amortizing the cost. There are many many other circuit topologies and manufacturing methods (silicon germanium, GaAs, etc.) that produce faster transistors. But moving to those are 1. expensive and 2. comes with their own limitations.
Graphene isn't perfect either. Aside from the difficulties in fabricating it, there's also the problem that unlike MOS, there's isn't a way (yet) to make a good graphene PFET. CMOS circuits are the way they are today because using a PFET-NFET topology works really really well for digital circuits.
Graphene (and carbon nanotubes) also have the problem that they don't really have an "off" state. There's less conductive and more conductive. CMOS at small geometries may leak current but nothing like CNT's and Graphene do. The circuits made from them are very power hungry (at least with current circuit topologies).
There's a lot of research trying to come up with better circuits to utilize the incredible on-current states without tunneling power between VDD and GND during the "off" state.
Before Ungerboeck's work, information theory seemed very clear about the fastest possible rate at which data could be reliably sent on the frequencies that would "stay on the wire" without bandwidth bleedover. Ungerboeck just demonstrated that there were artificial assumptions underlying the information coding theory on which that speed was based.
Shannon Theory very well laid out the maximum data rate that could be transmitted over a medium and Trellis Modulation did not exceed that. The fundamental limits were well known and not wrong. Implementations that existed then simply couldn't come close.
Ultimately, home internet connectivity still required a new infrastructure (thick copper lines). There were fundamental physical limitations of phone wires; those wires were replaced.
The situation with silicon is similar. We've gotten to the point where FETs can't get any thinner (and therefore, faster). Changing the semiconductor material allows better current per area but it has its own complications as well.
Well there are a few reasons the current "unlocked" market doesn't work.
1. The unlocked phones are not powerful phones. People buying these types of phones are the "I'll take anything that's cheap and works" buyers. They just want something to call someone with. Obviously, to these consumers, subsidized phone + contract is better than unlocked phone that you pay for.
2. They only work with certain networks. As you mentioned, even when you buy an unlocked phone, you're still limited by either GSM/UTMS or CMDA.
The phone Google seems to want is not a Razr-class phone; it's an iPhone class phone. This targets people who are perfectly willing to pay $300+ for their smartphone. I know I'm one of these people. I paid $300 for an iPhone and wouldn't mind paying $400 for an unlocked one that works with any carrier.
And that brings us to the question of carrier network compatibility. Luckily, this isn't a problem anymore since Qualcomm released their universal hybrid chip that works with any network in the world. I believe it's rumored that the upcoming iPhone -- a version that'll work with Verizon -- will use this.
If Google does utilize the latest and greatest hardware and actually builds an iPhone class phone with software that matches, there will be geeks lining up to shell out multiple hundreds of dollars for it.
If they're concentrating on fixing/improving Windows 7...will they stop?
If they're not going to stop fixing/improving Windows 7, what's the difference?
It's like the little penny tray. The pennies are for everyone. And we're just taking fractions of a penny here.
I can see so many of them freaking out cause of this.
I'm surprised there haven't been any "sounds like my ex-wife" jokes yet.
If all you're worried about is making calls and storing numbers, Google Voice is your solution.
1. You would get frostbite. Water forms crystals when pressure decreases even when temperature remains constant.
We've been at roughly ~200ps per circuit operation for quite some time and yet processors are still getting faster. Parallel computation, what a novel idea.
With the sheer amount of tech in something like Star Trek, making it all scientifically plausible would've been very time-consuming. And it isn't necessary to what it was: political and social allegory.
There are movies that do get the science right (Sunshine) but those were science-y movies. Their purpose was to show off the science.
Star Trek was about something else entirely and complaining about how its science is inaccurate is like complaining that Dante's version of hell wasn't like how the Bible described it or that the king in The King and I didn't behave like a east-asian despot would. It simply wasn't the focus of the show.
HydroQuebec's transmission system is AC. The equivalent power loss over 11k km with a DC current would be insane.