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NAND read disturbs are well understood by the NAND vendors and SSD controller manufacturers. SSD drives from reputable vendors are engineered to deal with it, just like they are engineered to handle NAND wear-out, and bad-blocks. Micron published a document a decade ago discussing it (see TN-29-17 )

PCM is not limited to re-writable Blu-Ray, it is actually used in memory chips.

Micron used to manufacture PCM memory chips and dropped them in 2014. There are also some debate regarding whether IMFT's 3D XPoint is also PCM or not.

The real innovation in IBM's work is turning PCM into a TLC, and that is really impressive.

Isn't Micron a step ahead with their 384Gb NAND chip?: http://www.micron.com/about/in...

Data sheets now days are not avalable to the public

Datasheets ARE publicly available. However, they're for the actual DRAM ICs themselves, and not of the modules.

There are only a few DRAM manufacturers out there - Samsung, Hynix, Elpida, Micron are among them.

Samsung Computing DRAM (they also have Graphics DRAM and others). Some of their newest chips don't have datasheets yet, but that'll be forthcoming. The older ones in production do, however.

Hynix

Micron (and Elpida).

These are all generally available. Since the only real difference between them is a few timing numbers, they're not generally a huge secret - it's all governed by JEDEC standards anyhow.

Memory modules are just collections of these chips so they can be generalized to what you buy in the store for your PC.

I understand all that - in the past, I worked on multi chip memory packages, where we'd stack NOR, DRAM and NAND flash: this was particularly for the handset makers. The whole thing about that business was that margins were wafer thin, in a manner of speaking. Which is why AMD spun off Spansion, and Intel spun off Numonyx.

I don't see how putting multiple NAND chips into an SSD makes it more cost competitive, unless their prices have really come down. Although I do see Micron offering up to 128Gb in TSOPs, so one would need 8 of them to make a 128GB drive. To get a 1TB drive, you'd need 16 of those chips (talking about die: looking at their product lineup, it looks like they put several of their 128Gb die to come up with 2Tb flash in a single MCP). So divide the price of an SSD by that, and that's what the price of the flash would have to be to be profitable.

Incidentally, any idea of what exactly are 3D NAND drives?

Google: flash read disturb

The Micron presentation is rather old, but gives a good overview of how Flash works.

50us? 50-100MHz? 1/50E-6 = 20KHz, not 50MHz.
http://download.micron.com/pdf/datasheets/flash/nand/2_4_8gb_nand_m49a.pdf -> Sequential READ: 30ns
I.E. half the speed of 15ns DRAM.

Parallel read stuff is a bit slower, but not a lot. You can pay more for faster and you can always wire it up in parallel.
http://download.micron.com/pdf/datasheets/flash/qflash/MT28F640J3.pdf

SRAM speed depends entirely on the context, of which there are many. The on chip ones I use take less than 1ns to read on a modern silicon process.

50us? 50-100MHz? 1/50E-6 = 20KHz, not 50MHz.
http://download.micron.com/pdf/datasheets/flash/nand/2_4_8gb_nand_m49a.pdf -> Sequential READ: 30ns
I.E. half the speed of 15ns DRAM.

Parallel read stuff is a bit slower, but not a lot. You can pay more for faster and you can always wire it up in parallel.
http://download.micron.com/pdf/datasheets/flash/qflash/MT28F640J3.pdf

SRAM speed depends entirely on the context, of which there are many. The on chip ones I use take less than 1ns to read on a modern silicon process.

I specifically had SLCs in mind when I ran the numbers.

Why? SLC NAND is only found in enterprise grade SSDs. The vast majority of SSDs purchased by consumers are 2-bit MLC. The tiny but growing fraction which isn't is 3-bit MLC instead. SLC is irrelevant to consumers who might need the kind of "advice" you tried to give.

As for the enterprise side of things, even there SLC is already essentially irrelevant to future products outside of specialty niches. And enterprise certainly doesn't need the likes of you telling them "don't worry be happy". They can just look up manufacturer's specifications for the write lifespan of any given enterprise SSD. That being the smart way to go about it, as opposed to pulling bullshit numbers out of your ass as you seem to prefer.

As for the 100k writes I used my original calculations, I took those from this PDF here: http://www.datasheetcatalog.org/datasheets2/16/1697648_1.pdf - see section 1.5, it lists "Endurance : 100K Program/Erase Cycles"

Great, you know how to read. Unfortunately, you don't know how to think. That datasheet is dated July 20, 2005. It's from more than 7 years ago. Do you seriously think any SSD still on the market today uses ancient NAND chips?

Even if the date didn't clue you in, the density should've. The smallest part in that datasheet is 1 gigabit, the largest is 4 gigabits (yes, bits not bytes, if they meant bytes they would've used capital-B not lowercase). 4Gb = 0.5 GBytes per package. Typical 2.5" SSDs contain no more than 16 NAND packages. That'd make an 8 gigabyte drive. There's a reason why SSDs weren't a big thing in 2005.

As for the 1M write cycles: http://investors.micron.com/releasedetail.cfm?ReleaseID=440650 - that one came out in 2008, so using it as a baseline for "newer" SLCs didn't seem that far off.

Let me break this to you in a not so gentle way: you have no idea what the fuck you're talking about. It is not in any way "reasonable" to use a 4 to 5 year old spec as a "baseline" for newer chips. NAND write cycle endurance has reliably gone down on every process shrink in recent times. Error rate keeps going up too.

Good job slashvertising yourself though, man! You knew exactly where to go for clueless editors who'd happily expose you to a huge clueless audience.

I'll have to revise the article to include those links methinks...

Just delete it all and replace it with an acknowledgement that you are the worst possible person to be giving advice, the kind who's learned just enough about a topic to be really incompetent at explaining it to others. You are a case study in the Dunning-Kruger effect.

For example, from your blogpost, some idiocy which seems to underpin the silly graphs you invented:

As for the "10% Threshold" line, that's because SSDs typically contain about 10% of spare blocks hidden from the OS and used to replace dead blocks on the drive transparently. You typically won't find dead blocks in your fsck before that threshold is reached.

Uh, no. That's not how it works. Unlike HDDs, the X% space held in reserve (X varies by drive) is not for simple sparing. Understanding why requires a bit more in-depth knowledge of NAND.

The granularity of NAND flash erase operations is much coarser than the write granularity. For example, using made up numbers, you might have to erase 512K chunks while being able to individually write 4K sub-blocks inside a 512K chunk. This means that when the host computer writes a single 4K filesystem block (almost all FSes use 4K block granularity right now), a naive SSD controller would use read-modify-erase-write on the whole erase block to write in place.

But that results in horrendous write ampl

It's not flamebait because following the link would provide you with as many citations as you care to look at. Here's one since you're too lazy to click the link and choose a result:
http://www.micron.com/products/nand-flash/slc-nand

"Durable: At 100,000 PROGRAM and ERASE (P/E) cycles, our SLC NAND is one of the most robust and reliable NAND technologies available."

Now you have your citation. You can stop giving knee jerk responses that ignore the fact that there's more than one type of flash memory out there.

I specifically had SLCs in mind when I ran the numbers. As for the 100k writes I used my original calculations, I took those from this PDF here: http://www.datasheetcatalog.org/datasheets2/16/1697648_1.pdf - see section 1.5, it lists "Endurance : 100K Program/Erase Cycles" As for the 1M write cycles: http://investors.micron.com/releasedetail.cfm?ReleaseID=440650 - that one came out in 2008, so using it as a baseline for "newer" SLCs didn't seem that far off. I'll have to revise the article to include those links methinks...

I smell FUD, and that's kinda bad in view of the power consumption figures being explicitly stated in *easily* publicly available datasheets

Let's see how much supply current is needed to self-refresh a 1 terabyte of DDR3L SDRAM.

Let's look at 8 gigabits MT41K1G4 chips from Micron. The chip takes 28mA max at 1.35V. That is 37.8mW per 8 gigabits. A terabyte has 8000 gigabits, or 1000x as much -- that's 38W or about as much cooling as a CPU found in someone's desktop PC might dissipate.

If powering and cooling one CPU is "substantial power supply and cooling", then, well, obviously we've got different points of view on this stuff.

Do notice that those chips dissipate more power only if you access them, so 38W is the idle state but even if you *do* access them, you don't dissipate all that much more -- you'll be probably only accessing a couple of chips at a time. The worst case all banks interleaved read current on those chips is 320mA, so if you access 4 chips at a time, that's still only 1.8W of extra power on top of refresh power.

Of course the logic used to piece together all the chips into a storage device will also use up power, but that logic is in idle low-power state when the chips are not being accessed, so it's a big deal.

Youre not going to tell me a voltage drop from 1.5v to 1.35v on a laptop with discrete graphics is worth $1000. I doubt you would even notice the difference, TBQH.

From http://download.micron.com/pdf/technotes/ddr3/TN41_01DDR3%20Power.pdf
It looks like peak current is around 120mA, which means the reduction from 1.5v to 1.35v nets you a savings, at maximum, of a whopping 18mW. Thats not even considering that that is PEAK draw, and over time its proabbly closer to 10mW.

This, in a box drawing a total of probably 40W, which means a savings of 0.25%. WOOOOOOO! THAT will extend the battery life a whole bunch!

http://investors.micron.com/releasedetail.cfm?ReleaseID=646118

And how did my +1 Informative mod from earlier today end up listing this comment as funny?

I'll take my mod points back by replying to this article and see if someone can explain this to me...

Micron's Website: http://www.micron.com/
What Micron is: A company that is in the business of designing and building some of the world’s most advanced memory and semiconductor technologies.

http://investors.micron.com/releasedetail.cfm?ReleaseID=646118

Micron has SLC chips that do 1 million cycles as of 1.5 years ago.

Storage is often given in bits. For example, the size of every one of the NAND Flash ICs listed in Micron's online part catalog is given in gigabits.

The GP could have checked the article before commenting, but it is perfectly reasonable to wonder whether the submitter intended "1Tb" to be one terabit (exactly 125 * 10^9 bytes), as written, or one terabyte (about 1.0737 * 10^9 bytes, or exactly 2^30 bytes).

No, you're not missing anything. I used Google to calculate the number:
135 GB.

However, I did have to do a bit of checking up, and I found out what was wrong:
1.06 TB

Capitalization isn't just important in husbandry.

when I did my 135 GB calculation, I checked their website and found that their lowest capacity unit was 150 GB, so I expected that I was right and the kb vs kB error hadn't crossed my mind.

I did just check Wikipedia though:

SLC Floating Gate NOR Flash has typical Endurance rating of 100K to 1,000K cycles (Numonyx M58BW 100K; Spansion S29CD016J 1000K)

, so that would of course be an option, but Pliant's own website says:

Flash Memory Technology SLC NAND

They don't say 180,000+ IOPS though, but "only" 160,000+ so that doesn't affect the math much.

I looked around a bit, and Micron says about their "Enterprise NAND":

Enterprise NAND is a high-endurance SLC NAND device that offers an endurance rate of 1 million WRITE/ERASE cycles. Thats 10 times the 100,000-cycle average for SLC. Our Enterprise NAND is optimized for intensive storage applications where device life is the top priorityapplications like high transaction data servers (banking) or enterprise SSDs.

So, while my math was off by a factor of 8 (or a bit shift, as the shift key should have been pressed), it turns out that there are actually SLC NAND chips available that increases write endurance by a factor of 10. This reduces the minimum space required to 108 GB.

But very nice catch. And informative - made me go find out if it was still possible.

Actually you do.

Yeah, because of the fifty busiest ports in the world, Canada has one on the list (Vancouver) and the United States has six and five of them move more cargo than Vancouver.

The only ports that freeze are in the great lakes, you know the ones that ship out the majority of the grain to the rest of the world.

This confuses me. Not the freezing ports part, but the grain shipping, because the US exports twelve times as much grain as Canada. With 22% going via California, and the next 16% going via Washington and New York.

It means that if you throw a hissy fit, we simply say 'our market is now europe' and they buy our goods, or japan, or anyone else.

Yeah, because Asia is going to totally want to import goods from a half way around the world where it's twice as expensive to produce the goods, than they will from multiple countries right next door where labor is cheaper. I mean why import goods from Malaysia into Japan when you can ship stuff from Canada.

And yeah, I agree, it's going to be totally trivial for Canada to find new markets for 80% of their total exports. Not.

While you're very good at consuming our goods, and tell me something do you even have the manufacturing base left to make anything?

I don't know. Maybe air planes, heavy equipment, trucks, microprocessors, DRAM & flash. Then of course we have things like tanks, airplanes & submarines, aircraft carriers, fighter planes & submarines. And there are vaccines and medicines.

But, hey, we import our socks, so yeah, I can totally see why you'd think the US isn't capable of producing anything.

The only reason the US imports manufactured goods is because it's cheaper. Barring protectionist policies, every industrialized country does the same.

Apparently wear leveling is no panacea. Some devices wear-level only within a zone, and so a lot of activity in a hot zone can still burn that zone out. I guess such an algorithm only really works well when writes are distributed across zones evenly.

See page 5 in this document for a description of zone-based wear leveling.

A laptop in S3 does need to keep SDRAM powered but you can put the SDRAM chips into a mode called Self Refresh. As the name suggests they refresh themselves internally. Refresh is quite a slow process, you need to refresh the entire chip every 64ms. In self refresh you could make the chip sleep for 64ms, wake up and do a refresh cycle and then go back to sleep. The external interface can stay powered down because in self refresh mode you can't access the SDRAM contents from the outside world. Because of these possibilities and furious competition to make low power chips modern SDRAM tends to be pretty low power in self refresh mode. These chips use 5mW -

http://download.micron.com/pdf/technotes/TN4810_B.pdf

That's each, an a typical laptop SIM might have 8 chips on it, so maybe you need 40-100mW for the whole laptop which is by no means negligable, but bear in mind an active laptop needs tens of watts. So a laptop in S3 is plausibly using 1% of the power of a laptop which is on.

Looking at the parent post you can actually work out the percentage. He said he left the laptop on for a weekend, say 30 hours and it was 20% depleted. That means he could have left it for 150 hours before it was completely depleted. An average laptop manages around 2 hours battery life, so you can see S3 is about 1% of the power of an active laptop.

So if you want to sleep for less than a week, S3 is quite safe. Vista has a hybrid sleep mode that writes the memory to disk and then goes into S3. If you press the power button before the battery runs out it does an S3 resume which is very quick. If the power fails it does an S4 resume i.e. it reads the memory contents back from disk which takes a bit longer.

Look at the articles date its for real. Also http://www.micron.com/about/news/pressrelease.aspx?id=0D8D6CD8EFA2B68E

Sad but true.

Which Flash memory manufacturers were you thinking of?

The Flash memory integrators who are using Flash chips for storage devices are using the same notation that the hard drive manufacturers are using. The chip manufacturers themselves however are using the notation that the semiconductor memory manufacturers are using except they do not count the area reserved for error correcting data in the actual storage capacity.

In some respects this is a little odd because the actual number of bits stored in the array is not a power of 2 when you count the extra error correcting bits (64 bytes per 2048 byte block) but that is only at the lowest level and the pages and blocks themselves are addressed in powers of 2. It is just the page size itself which is not a power of 2.

I guess the lesson here is that it is the interface that matters. This is especially the case for low pin count parallel interfaces (DRAM and SRAM) where initially the chip organization was driven more by the cost of the package pins then chip layout considerations. If your interface relies on powers of 2, then a kword (whatever the word size happens to be) is 1024 of something. Maybe the hard drive manufacturers should have switched to binary coded decimal.

A typical bulk NAND Flash device is specified like this: (copied from a Micron datasheet)

Page size x8: 2,112 bytes (2,048 + 64 bytes)
Block size: 64 pages (128K + 4K bytes)
Plane size: 2,048 blocks
Device size: 4 Gb: 4096 blocks; 8 Gb: 8,192 blocks; 16 Gb: 16,384 blocks

So for this device not counting the page level error correcting bytes:

4 Gb = 4096 blocks x 64 pages/block x 2048 bytes/page = 4294967296 bytes

You might also note that the block size of 128K is equal to 131072 bytes.

I remember when the hard drive manufacturers switched to base 10 notation and I do not remember anybody who thought it was done for anything except marketing reasons. It made their own drives look larger then the drives of their competitor's who had not switched yet.

http://download.micron.com/pdf/datasheets/flash/na nd/4gb_nand_m40a.pdf
promises data retention of 10 years. I would guess that it will function longer than that, but only if you refresh the data.

http://download.micron.com/pdf/datasheets/flash/na nd/4gb_nand_m40a.pdf
Says 100,000 program/erase cycles right on the first page (though I do note they only 'guarantee' 1k writes for the first block).

arbuably, just installing 8 GB of RAM or whatever might be more economical and effective

I wonder if we in the near future will see hybrid systems with flash-based drives for applications and swap space, and hard disk drives for data storage.

so what would consume more 32gb SRAM or 32gb disk?

MK3006GAL: 1.8" HD, 0.01W/GB, 1.1W power consumption during operation 0.4W idle, 0.07W sleep.

Now, SRAM is a different story. I only checked digikey for SRAM, and the biggest one they had was 128Mbit, but it was actually DRAM that is accessed like SRAM. With 128Mbit chips, you are looking at over 1800 chips! Even with the "low power" chip I found, those 1800 chips consume 375mA in standby mode (not including the insane amount of support chips required to drive 1800 chips!) To actually use the RAM, each chip has an "initial access" power rating of 35mA, making a whopping combined 65A, talk about some thick PCB traces!

I don't have time right now to look up the power requirements of 32GB of flash or SDRAM. There is a link somewhere in the comments for this article to a device that supposedly lasts up to 100 hours on batteries. It is a sort of large, palm os based device with only 16MB of memory, but can run on AAs. perhaps that would suit your needs for now.

Exactly. So why the need for this 1024 shit?

Because 2^10 = 1024, not 1000.

You're already talking about units in multiples of what's "native" to the machine/software.

Which is my point. Addressing of data is done in base two, not base ten.

The switch to base ten, was a marketing tactic of the hard drive manufacturers. It is dishonest and deliberately misleading.
If you look at other things like RAM, a 1Gb RAM chip gives you 1073741824 bits (2^30).
It's that way today, and it was that way twenty years ago.

1 Kb = 1000 bits is the brainchild of sleazeball marketers.

Just a side note... the price issues with RDRAM were (admitted in court) a result of a DRAM consortium using monopolistic tactics to undercut RDRAM and keep the prices high.

The problem with this? Latency goes up as you put in more DIMMs. Why? Because data from the 4th DIMM has to pass through (not just by) the 3rd DIMM, 2nd DIMM and 1st DIMM to get to the CPU.

This sounds contrary to "point-to-point" as mentioned at Micron. What you describe is that the FB-DIMMs are in serial. The data is transmitted serially but the topology of the FB-DIMMs is point-to-point, which means (potentially) parallel access to all FB-DIMMs (point-to-point implies a switched topology).

Also, by your arguments... it seems you'd prefer PATA HDDs over SATA HDDs (the same arguments apply there as well). I think many review sites tend to like SATA drives for a variety of reasons. I suggest reading up on a lot of the discussion about parallel data transfers vs. serial data transfers (in relation to buses) and see the advantages and weaknesses of each, particularly at high clock frequencies.

Micron makes DRAM.

Ummm, mostly correct.

Micron also makes flash, but it is a small portion of their revenue.

In fact, Intel just partnered with them to increase Intel's access to flash product. The new company is called IM Flash:
http://www.micron.com/news/corporate/2005-11-21_na nd.html

scrub

I've looked at a few datasheets, and they all say 100 thousand read-write cycles.

Looks like Micron NAND flash is the same.

I read something about getting > 100k cycles out of an EEPROM, so some applications must approach that limit.

There still is a US DRAM manufacturer. Micron is still alive and kicking (and has been continuously in business since 1978), selling to consumers via the Crucial brand. There was price-fixing (which Micron doesn't seem to be completely innocent of, either), but one thing to keep in mind is that RDRAM, even if it weren't patented, required approximately 5-7 extra mask steps to create, as compared to DDR DRAM. In the cut-throat world of DRAM manufacturing, where every penny counts, this is a deal-breaker. Samsung was able to make money off RDRAM only because it was so expensive. Was it illegal for these companies to team up and kick down RDRAM? Yes. Am I sad to see it go? No way.

... or by the fact there is a technology company in Idaho.

I know you were being funny, but I assume you've heard of these guys... http://www.micron.com/

...Maybe these guys... http://www.hp.com/

But don't take my word for it: http://www.entrepreneur.com/Magazines/Copy_of_MA_S egArticle/0,4453,308612,00.html

> This chip from Micron, costs less than $2K and does 500 full-frame megapixel images per second.

Now imagine a Beowulf cluster of these things!

Seriously now, this made me think of a couple of things. One is that this technique, which a lot of you say is worthless, is actually adaptable, so nobody's stopping you from using better sensors.

For example, if you use a sensor with a "snapshot" shutter, one that records the whole frame at the same instance, and not the über-cheap ones they used with "rolling" shutters, you eliminate their time/resource consuming task of "slicing."

Then imagine using your megapixel sensor, that runs at 500 fps native, and adapting it for use with this technique. You can use "just" 10 sensors to achieve 5000 fps. And I do believe your image quality will be much better than theirs.

Another idea: add a few additional sensors in a closely-spaced secondary plane to cover any "holes" so you don't have to crop down your final output quite so tight. Think of digital image stabilization in consumer camcorders.

Just some food for thought. I just don't like it when people knock things. Heck, this procedure sure is more fun than sitting on your ass all day reading /., so stop bitching (that's plural you, not you in specific, Anonymous Coward).

Reading between the lines, they seem to have custom hardware and (maybe?) an MPEG encoder behind each camera, and a huge amount of software and general hassle to get an unwieldy and inflexible system to work at all. The upper limit on frame rate is about 5K/sec due to the integration time, but they would need about 160 cameras to achieve this continuously, and a hell of a lot of processing to produce sensible output. A lot of effort for something that isn't actually very useful.
For the same or less money/effort I have no doubt they could have either bought a purpose-made high-speed cam, or built one using something like This chip from Micron, which costs less than $2K and does 500 full-frame megapixel images per second, faster for partial frames. One neat feature is that it can effectively image individual lines at arbitary places in the frame at 500,000 per second - I'm sure these academic types could do some interesting interpolaty stuff with this to synthesise full-frame-like images at pretty high rates instead of messing with a system that doesn't have any realistic practical use.

FYI: Micron
Incredible.

They lost $521 million in 2001
They lost $1025 Million in 2002
They lost $1273 million in 2003

They lost $521 million in 2001
They lost $1025 Million in 2002
They lost $1273 million in 2003

They lost $521 million in 2001
They lost $1025 Million in 2002
They lost $1273 million in 2003

Micron bought out Dominion Semiconductor, a joint Toshiba-IBM memory fab plant in Manassas, VA in early 2002. As time went on, production went down, work on a second process lab was all but halted and the plant effectively stopped production early in 2003 (I had a family member that worked there). In the same time frame, they also cut production in their main plant in Idaho. The goal at was to also buy or merge with cash strapped Hynix in Korea but that was shot down by the Korean government. I believe their goal was either to move production out of the US or to buy who they could and join forces with those they could not. In that time frame, memory prices were extremely low, companies were failing and Micron saw a chance to gobble up the competition. The gamble failed when the Hynix buy fell through. Interestingly enough, they applied for and have recieved government funds related to memory dumping.
They had a goal of getting memory prices to a certain level and could not do it with competitors.

PS.. Crucial is Micron

Twin Falls, Idaho is a technoplogy SINKHOLE! in fact, it might be a good idea to avoid Idaho completely, unless you're interested in Micron, the company behind Crucial Memory, which is in Boise, Idaho. but stay AWAY from Twin Falls! there's nothing but HICKS here!

JPL has always farmed out new technology to private industry. Its our secondary charter just under our NASA work. From what I've read of the press report linked, this just seems to be a re-organization and re-focus of the old Technology Affiliates Program. I've worked primarily for non-NASA reimbursable projects. In the 10 years I've worked at JPL, I've only charged to a NASA number ONCE. And then only for a summer. A reimbursable project is when an outside organinzation pays JPL (through NASA) to do work for for them, and they get something in return, like a research paper, technology, or a piece of hardware. JPL will do the work, and then will get reimbursed by the company at completion, IIRC.

As an example of some of the work either I, or my co-workers have done under the TAP-like programs include things like systems, hardware, and behavior software for autonomous urban robots like Urbie under DARPA. Ford has funded my group to develop hardware for Engine Control, Emission Control, and diagnostics using Neural Networks. 3-Dimensional IC stacks with Irvine Sensors Corporation for novel Neural Network architectures. Quantum Well Infrared Photodetectors (QWIP) imagers by various companies. Active Pixel Sensors (APS, buzword category: CMOS Imagers) has been licenced to private companies like Micron (formerly Photobit, before they were bought by Micron). Our Micro Devices Lab has farmed out a metric buttload of MEMS instruments and sensors to more companies than I can remember.

That said, JPL WILL NOT compete with private industry. We're not allowed to and it doesn't make sense to. We don't do manufuacturing or marketing. JPL does things that no-one else does. Once we figure out how to do something, we give it to someone else and figure out how to do something new. Since we are a Federally Funded Research and Development Center, it is unappropriate for us to steal business away from legitamate business. However it is appropriate for us to be in bleeding edge research areas that are still not financially or strategically desirable for private industry. The Government usually plays anchor tennant to most technolgies.

As a peon looking up, I can see why they've started to emphasize more on reimbursable projects. NASA and Congress is getting more and more fickle on what and when to pay for new projects. The next rover is finishing up soon (The Mars Exploration Rovers, or Mars '03) and work is rolling off. Everyone coming off MER is looking for new jobs and the project that was supposed to pick everyone up (Mars '05) was pushed back to '07. So the scare of layoffs is real amongst us. I'm actually in the same boat since my projects had the misfortune of ending at the same time MER did, so I'm competing with them. (I believe I've got my funding covered, but I'm in the gap at the moment taking vacation). I'm not the only one I know in my situation. If JPL can get more reimbursable projects, I believe JPL can better weather the whims of congress.

I am glad that JPL is re-emphasizing in comercialization. Although Space missions are fun, novel technology is much more satisfying to me. If we can get more industry to fund new technology, I believe the US will be much better off.

OK, well 2pF may not seem like alot and in most cases its not. However, what you are forgetting is the scale we are working at here. I tried to lookup the exact memory module for a GeForce card, but I couldn't so I just went to Micron's site and looked up their spec on their 256Mb DDR333 SDRAM. If you will look on page six you will see the capacitance ratings for each signal line are as low as 0.5pF for three of the signal lines and max out at 4.0pF for the I/O (data) lines on the memory module. So lets look at the 2pF number again. By adding a connector you increase your input capacitance by 400% in some cases and 50% in the best case scenario. This is very bad and will directly impact how much memory can be put on one bus and how fast the memory can be timed. The more input capacitance you have on a line the harder the output buffers of the graphics chip (or memory controller) have to work. More input capacitance directly affects how fast you can get that nice little square wave signal to look nice enough to be registered on the other side. The more input capacitance the longer it takes, and this is all very relevant at the speeds we are talking about here. Also, FYI other factors for not using a connector include trace length. By adding modules you are increasing trace length by a large amount (relatively speaking of course). This also adds input capacitance.

So now you are probably asking. How much capacitance can a typical graphics chip or processor drive? Well I tried to find the datasheet on nVidia's website for their GeForce chips, but didn't turn up a thing. So I went to Intel's site and looked up the datasheet for their 845G chipset with integrated graphics. If you look on page 525 you will see that the output drive for the Intel chip is 12pF. So now you can probably see the problem. Assuming all we drove were memory modules directly from the 845G (which we wouldn't in real life) we could put just two to three 256Mb (32MB) modules on board without connectors. If we put the Molex connector you specified in between that number changes from 1 - 2 chips. In real life we would put a nice buffer in between that has a stronger output drive in between the 845G and the memory. Like TI's 24-Bit to 48-Bit Registered Buffer. That sucker has a 30pF drive and each buffer could easily drive 6 - 7 modules for a total of 256MB of RAM without the connector. Add a connector and this number deindles to 4 - 5. Anyway, I'm sure you get the point. At this scale even a 2pF connector makes a big difference.

However, after saying all that I should mention that I do not believe that these electrical considerations are the main or only reason the cards are not expandable. I think alot of it has to do with demand. Very few people are gonna upgrade their video card with more memory. I don't know any Matrox Millenium owners, including me, that upgraded their memory on their video cards. Because the economies of scale for a specialized memory make them much more expensive to produce than consumers like myself are willing to pay. In adition, by the time I am gonna upgrade a cards memory I can probably buy a brand new one with that amount of memory for the price of the piddly module ;)

JOhn

OK, well 2pF may not seem like alot and in most cases its not. However, what you are forgetting is the scale we are working at here. I tried to lookup the exact memory module for a GeForce card, but I couldn't so I just went to Micron's site and looked up their spec on their 256Mb DDR333 SDRAM. If you will look on page six you will see the capacitance ratings for each signal line are as low as 0.5pF for three of the signal lines and max out at 4.0pF for the I/O (data) lines on the memory module. So lets look at the 2pF number again. By adding a connector you increase your input capacitance by 400% in some cases and 50% in the best case scenario. This is very bad and will directly impact how much memory can be put on one bus and how fast the memory can be timed. The more input capacitance you have on a line the harder the output buffers of the graphics chip (or memory controller) have to work. More input capacitance directly affects how fast you can get that nice little square wave signal to look nice enough to be registered on the other side. The more input capacitance the longer it takes, and this is all very relevant at the speeds we are talking about here. Also, FYI other factors for not using a connector include trace length. By adding modules you are increasing trace length by a large amount (relatively speaking of course). This also adds input capacitance.

So now you are probably asking. How much capacitance can a typical graphics chip or processor drive? Well I tried to find the datasheet on nVidia's website for their GeForce chips, but didn't turn up a thing. So I went to Intel's site and looked up the datasheet for their 845G chipset with integrated graphics. If you look on page 525 you will see that the output drive for the Intel chip is 12pF. So now you can probably see the problem. Assuming all we drove were memory modules directly from the 845G (which we wouldn't in real life) we could put just two to three 256Mb (32MB) modules on board without connectors. If we put the Molex connector you specified in between that number changes from 1 - 2 chips. In real life we would put a nice buffer in between that has a stronger output drive in between the 845G and the memory. Like TI's 24-Bit to 48-Bit Registered Buffer. That sucker has a 30pF drive and each buffer could easily drive 6 - 7 modules for a total of 256MB of RAM without the connector. Add a connector and this number deindles to 4 - 5. Anyway, I'm sure you get the point. At this scale even a 2pF connector makes a big difference.

However, after saying all that I should mention that I do not believe that these electrical considerations are the main or only reason the cards are not expandable. I think alot of it has to do with demand. Very few people are gonna upgrade their video card with more memory. I don't know any Matrox Millenium owners, including me, that upgraded their memory on their video cards. Because the economies of scale for a specialized memory make them much more expensive to produce than consumers like myself are willing to pay. In adition, by the time I am gonna upgrade a cards memory I can probably buy a brand new one with that amount of memory for the price of the piddly module ;)

JOhn

Over at Micron Technology in the imaging department we are working on the next generation of digital imaging sensors. All the processes are CMOS based instead of CCD.
Of particular interest to high frame rates might be the MI-MV13, Micron Imaging - Machine Vision 1.3Mega Pixel CMOS digital image sensor. This particular sensor can do 500fps at 1.3Mega pixel but can also be windowed to do for example 4000 fps at 1280 x 128.

Over at Micron Technology in the imaging department we are working on the next generation of digital imaging sensors. All the processes are CMOS based instead of CCD.
Of particular interest to high frame rates might be the MI-MV13, Micron Imaging - Machine Vision 1.3Mega Pixel CMOS digital image sensor. This particular sensor can do 500fps at 1.3Mega pixel but can also be windowed to do for example 4000 fps at 1280 x 128.

Over at Micron Technology in the imaging department we are working on the next generation of digital imaging sensors. All the processes are CMOS based instead of CCD.
Of particular interest to high frame rates might be the MI-MV13, Micron Imaging - Machine Vision 1.3Mega Pixel CMOS digital image sensor. This particular sensor can do 500fps at 1.3Mega pixel but can also be windowed to do for example 4000 fps at 1280 x 128.

[1] Image Quality [2] Bandwidth [3] Frames per Second (speed)

The other posters are correct pointing out the limitations inherent in high speed digital photography because today there are certainly a few that need to be over come before the transition can be made. With the speed of memory technology we are able to store a limited amount of image data on camera and allow for this to be transfered after capture has taken place. Already we see the beginings of high speed digitals that can be run indefinately with a loss in image quality. When you take out color completely and drop frame resolution than there is alot you can make a digital camera do. The reason that you have a loss in image quality as the speed increases is because the CCD / CMOS / CIF [Common Interchange Format] can't read out the image data fast enough between frames. Current implementations make one chip act as two whereby only one half of the imager captures at a time while the other half is busy transferring its data.

Readers should keep in mind that CMOS is used primarly in video because you can change the analog image data over to a digital value much quicker since there are more A/D converters and they are located closer to each pixel. If you are having trouble with the difference between the two How Stuff Works has a decent explaination. If you are looking for a vendor or want to read some data sheets to get a better idea of the differences between High Speed and High Resolution than I suggest visiting Redlake , one of the many vendors that have products on the market. If you want a better explaination of the target Image Quality that digital is trying to achieve than head over to this guy's site. I guess I will make this my paragraph of website plugs. I couldn't resist linking to an article written by a Professor of the program that I graduated from. It is about capturing a picture of a bullet hitting an object using a conventional megapixel imager.

I am glad that /. finially decided to run an article on this topic :) although it is plain to see that some of you are confused about what this technology is used for. Also I found it quite humorus that the one guy quoted image size of what he assumed the image sensor as 1024x768 which is the most commonly used screen resolution but probably has never been a image sensor size. Here is a good reminder from micron concerning the differences in resolutions. Most image sensors that are developed are of the same size in both dimensions. Not all but most.

Bandwidth isn't a problem. Another misconception that I hope to alievate. With fiber you are not limited by the amount of data that you can transfer through the cable, but by how you store the data once it is transferred. Now of course changing the data from light into electrical would cause a slow down. The reverse is also true. What someone should find out is the limitations of these converters. The only way we would see an advantage of using fiber was if we could finish developing new methods to store the data. I have read scientific columns on 3D optical storage techniques that might be applicable in the future. I think I got a bit off the track let me try and get back on.

The reason Bandwidth isn't a problem is because we don't have the capability to produce digital images at the same rate as with film technology. While it would be nice to have a 1024 x 1024 sensor running at 12K - 40K fps, it is not something that we can do currently.

So the question is what do you want to do with the high speed camera? How much important is Image Quality? How much do you want to spend on capturing the image data? See when it comes down to it, it all depends on the situation.

I am not quite sure why we are talking about high speed digital cameras in the first place. Maybe the person who wrote the article didn't research the equipment that this guy was using. I found his website and it says he is using film. Oh nevermind I reread it and he posed the question about why not use digital. I sure hope that I have answered that question!

Someone should brave the Japanese site linked off of the itworld site and find out the resolution of the 1 million fps Japanese camera. I bet it isn't very much.

Mr. Hemos, I would like to point out that Micron is a company, while micron is a length unit: 1/1,000,000 of a meter.