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G4 vs. Athlon Review
heatseeka writes "There is a great article at Ars Technica comparing the Motorola G4 and the AMD Athlon. They discuss every detail of the design of the CPU's, and give credit where credit is due. " Hannibal does a great job dissecting the different chips, as well as explaining the background behind each chip.
Comparing these two processors just isin't as exciting as the Intel AMD fight because they don't run the same software. Its like comparing apples too...ok I'll stop. underwear goes inside the pants, peanutbutter outside
This is one of the best CPU comparison articles I have ever read. He goes into good detail about the differences in design between the 2 CPU's, and makes it pretty easy to understand. The one point he makes quite clear is that although each unit has it's advantages and disadvantages, their is no clear "winner" so to speak (he does favor the G4 though). I look foward to his next article about the altivec engine.
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There was never a genius without a tincture of madness.
IBM and Motorola are working on putting multiple PowerPC cores onto a single die. IBM has already done this with it's Power CPU's (a sibling to the PowerPC). This is feasible with the PowerPC, since its power consumption is so very low. A G3 at 400 MHz (on .22 micron process) for example uses 8 W max, 5 W on average. A single PIII or Athlon uses at least 4-5 times that much on average. This is due in large part to the complex instruction set that must be decoded and executed. With IBM's and Moto's superior Copper interconnect and SOI technologies, the power comsumption and core size can be reduced further, allowing even more cores on each die. Modern Multitasking, multiprocessing OS's with well written multithreaded apps will scream on these multiple-core CPU's.
AMD doesn't have the luxury of being able to throw away (x86 ISA) whatever it wants to. They are competing with Intel for the PC market. The G4 is a lock to appear in new Macs.
I would have to partially that with a previous post about the chips being uncomparable. What is a better mode of transportantion? a 1976 Jeep CJ or a 2000 NSX. Obviously a jeep is better for one thing but an NSX is amazing for others. Same quite uncomparable. but if you compare things like how they handle in their respective targets? that is answerable. The CJ is one of the besthandling stock off road vehicles made, and the NSX is one of the best onroad handling cars. They both handle very well and use different methods to get to their equal level of quality. Now Back to the chips the article. I think the article shows more that they are both great at the same things in their target applications as opposed to who plays quake better. Good article, Good Comparision, (my new Athlon 700 smokes..)
IT HAS YOU....
just a quick reminder ppl, don't try reading /. during ungodly hours of the night. i swear to god i looked at this article and read:
"There is a great article at Art Rechnica comparing the Motorola G4 and the AMD Athlon. They discuss every detail of the design of the CPU's, and give credit where credit is due. " Hannibal does a great job dissecting the different chips, as well as explaining the background behind each chip.
i was kindof amused at the thought of an art magazine reviewing the design of a couple of chips and the backgrounds behind them. ugh.
-- the opinions stated above aren't those of my employer. in fact, they're probably not even my own. you know what, ju
This artice is very informative with respect to the architectures but a useful follow up would be to look at the performance in practice. Both of these processors can be used to run Linux and it would be rather interesting to see how a pair of workstations faired in a side-by-side test.
While such a test would be interesting I expect that the results would, in practice, be as much a test of compiler maturity rather than a test of the speed of the underlying system. Despite the best efforts of the processor designers (out-of-order execution and all) these sorts of processor tend to be very sensitive to the compiler technology. Furthermore many of the multimedia and vector processing performance enhancments (SMID vs Altivec) really need to be accessed from assembler at the moment.
Still, rather interesting stuff.
If intelligent life is too complex to evolve on its own, who designed God?
Why is every article on CPU archtecture on websites like Ars Tecnica written at a fourth grade level? I don't need a review of branch prediction and instruction decoding. Sheesh!
They should just leave it MPF which is about the only open source which does publish interesting technical information on CPU architecture.
Let me prefece all this with, I know very little about how these things work exactly so bear with me.
It would seem from the article that although the K7 & the 7400 are pretty comaparble at the moment, the 7400 would have much more room to grow as well as being a much more efficient chip.
To me the fact that the K7 has to decode all this x86 legacy stuff would suggest that the K7 is basically like a brute little monster truck that basically rampages over its flaws by packing a lot of punch, in this case by basically bumping on more and more transitors.
The 7400 seems to produce a sleeker more elegant solution to the whole thing. It's more the sleek sports car with speed, and elegant, efficient power VS the brute force of the K7. So I guess in that regard, the 7400 wins out on efficiency and future sustained growth potential...
Must be said though that a mate of mine owns an Athlon and it rocks the house down, so even if it's like a brute little monster truck instead of the sleek sports car of the G4, it still packs a pretty hefty punch. I guess they both kinda rock the house down...
The Athlon is an amazing chip, even more so given the need to maintain backwards compatibility with real-mode X86 code and the hack that is MMX. The only performance improvements I really expect to see going forward in X86 architecture are going to be due to process improvement rather than architectural development. MMX and 3DNOW are kludges on the architecture. In light of that, Athlon stands out even more.
The G4, though, has the advantage of being a lighter-weight chip (fewer transistors needed, fewer instructions, less microcode). As for speed, RISC versus CISC aside, the Motorola/IBM designs have not shown the ability to drive the high clock speeds that Intel and AMD are playing with. Until about a year ago, the two were neck-and-neck, but the X86 chips are now up around 800 MHz while the G4 is just passing 500 now. But given the efficiency of not having to deal with all the microcoded X86 instructions the G4 minimizes the difference in a well-implemented OS.
Another thing to keep in mind (mentioned in the article) is that the G4 is not strictly designed for desktop computers. PowerPC chips are very popular in the embedded market, where they go into single-board computers, automobiles, and all sorts of dedicated hardware. Sales to Apple alone wouldn't keep a chip family alive. Interestingly, Intel sells a lot of older 386 processors to the embedded market too - the too-cool Blackbery 2-way pagers use a 386 processor among other devices.
The best thing that PowerPC has going for it IMHO is that Motorola didn't build backwards compatibility with the M68K series processors. They made an architectural clean break - and the few companies that needed compatibility did it through emulation (parts of the MacOS are still in 68K code today). The ample shortcomings of the MacOS tend to cover up what is a first-rate processor family.
My suspicion as to the 'real' reason Intel has been funding Linux ventures is this: they know that Windows is hopelessly tied to X86, and they are hoping to eventually leave that baggage behind in the IA-64 architecture. Ultimately, X86 will be a drag on clock speeds.
Sorry to have rambled about here some, but I'm still a bit sleep-deprived from the weekend.
- -Josh Turiel
-- Josh Turiel
"2. Do not eat iPod Shuffle."
Oops, I screwed up in the first posting. Here is a corrected one:
I agree such a test would be interesting. Just a quick correction, though: AltiVec is also SIMD, the Flynn classification which is used as a generic term in the literature.(Flynn's seminal paper is where the terms SIMD, MIMD etc. were coined first) AltiVec and SSE, MMX, 3DNow!, MIPSV, VIS etc. are SIMD implementations.
Also, Motorola has a bunch of very nice C libraries and modified compilers which take advantage of the new instructions, and I'm sure some other SIMD extensions have similar C libraries; so it's not exclusively accessible from assembly language. What's probably needed is some very smart compilers to choose when to use the SIMD extensions.
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check it out:
http://www.motorola.com/SPS/PowerPC/AltiVec/
and click on "progamming examples"
cheers
While it is one of the first truly unbiased and highly technical articles on the K7 and G4 chips (instead of rumors and performance "benchmark" drivel), it does not say that much about the chips in the end. It should have concluded with a stronger statement about the efficiency of the G4 chip.
The US Govt is often criticized for implementing obscenely expensive solutions to problems when simple ones would have done the job better. This can be applied the the K7 vs G4 question, for it is always better to have efficiency when the performance is the same.
Rumor has it that Intel is running the new Itanium chips currently with 30 watts of power consumption, over twice that of the G4. If I upgraded my motherboard to the itanium (tm), I would have to get a new case or power supply because of the incredible inefficiency of the chip. That is not novel engineering, but sluggish engineering, something which is not prized in this day in age.
"In individuals, insanity is rare, but in groups, parties, nations, and epochs it is the rule." -Nietzsche
The REAL sam_at_caveman_dot_org is user ID 13833.
It is a no brainer that these are the best two chips you can get in a PC today. But average joe 6-pack won't buy either of them because they don't have the name Intel stamped on them. Take your athlon or g4 duct tape an intel logo on it and then maybe the average user will pay attention. What they really need is better marketing.
True, but the gap will lessen (or disappear) in the near future. The G4 has been limited (in clock speed) by it's exceptionally short 4-stage pipeline. Motorola has demonstrated a version of the G4 with a longer 7-stage pipeline that hits much higher clock speeds (~700 MHz range at the demo - higher in production). Each stage is simpler and faster, resulting in the higher clock speed. The K7 already has a very deep pipeline, which is a large factor in its high clock speed.
is here
:)
It shows power consumption of the major chips in use. Note where the PPC chips are!
Enjoy.
Pope
It doesn't mean much now, it's built for the future.
As for speed, RISC versus CISC aside, the Motorola/IBM designs have not shown the ability to drive the high clock speeds that Intel and AMD are playing with.
The PowerPC doesn't need the high clock speeds of the Intel/AMD chips. On average, it does about twice as much per clock cycle than the X86 chips do.
Comparing clock speeds without consideration of clock efficiency is like comparing the version numbers of the various Linux distributions.
#naabhaprzrag, #sverubfr-000, #agi-fcbafberq, negvpyr[pynff*=' negvpyr-ary-'] { qvfcynl: abar !vzcbegnag; }
Our organization uses the PowerPC Microprocessor in cases where we had used other processors in the past where power consumption and other small factors had become an increasingly a problem over time. Also the fact the architecture isn't tied to an OS made things much easier to work with (stable) and thus we could design our systems to do exactly what we wanted to do how we wanted it. We also have the flexibility to change that how and when we want and stick with the same processor and a familiar architecture.
Granted we don't make Personal Computers but IBM has marketed those processors toward the Linux world.
Motorola/IBM designs have not shown the ability to drive the high clock speeds
I think this is probably not an issue of the Microprocessor design as it is the fabrication capabilities.
Also, the clock speed is not a valid comparison between two different chips, especially two vastly different chips; what you get per MHz is not the same thing; otherwise you would be able to buy and 800MHz Z80. It's like the truck company that built a 2 stroke pickup: people got freaked by the fact it redlined at 4000 RPM.
Post may contain irony: discontinue use if experiencing mood swings, nausea or elevated blood pressure.
One important part of the PowerPC architecture which this article fails to mention, is the multiple condition code registers of the PPC. (These date back to the older Power architecture, BTW.)
Unlike all the other similar features mentioned in the article, these can not be retrofitted into the K7, because it is limited to the x86 instruction set, which does not have this concept.
Basically, any instruction which needs to check the result of an operation (such as a compare, or overflow from an arithmetic operation) has to use condition codes. But in a pipelined processor, the result of the operation usually has to wait until the instruction has finished going through the pipeline. Rather than wait this long to decide what to prefetch, branch prediction tries to guess whether or not the branch will be taken. The predictions are usually right, but not always. What if there is more than one such comparison close together, particularly if the result is not being used directly for a branch, but for a boolean expression?
What the PPC does is have multiple (7?) condition code registers. When an operation such as a compare is done, you select a condition code register to receive that result. In the same way that code can be optimized for RISC by interleaving multiple threads of operations such that the result of an operation isn't used until three or four instructions later, the condition code register usage can also be interleaved.
With out-of-order execution (OOO), the CPU automatically rearranges instructions to achieve this interleaved usage of registers. And thusly, the PPC will gain this advanatage with condition code register usage as well.
#naabhaprzrag, #sverubfr-000, #agi-fcbafberq, negvpyr[pynff*=' negvpyr-ary-'] { qvfcynl: abar !vzcbegnag; }
Moto didnt have a choice in whether to implement 68K opcodes in PPC, IBM owns PowerPC, Motorola is just licensing it. Trying to add an opcode to the PPC is a real nightmare because you have to get IBM's approval. Moto went to PPC beacuse Apple demanded it, not because it was better than the Moto RISC, the MC88110. Actually, clock for clock the '110 was faster than the 601, and it had a better bus design than the Power architecture, so they put the MC88110 bus on a Power core, and that became the PPC601. The '110 also had a graphics Execution unit as well as FP and Integer units. Of course, its internal design and transistor technology limited it to about 65MHz and it was a few years late, so Apple wanted an architecture with some industry backing, IBM. NeXT was well under way in designing a dual '110 machine, I wonder what ever happened to it. One CPU did the color Display Postscript, and the other ran the NextStep OS. I'm sure Jobs was having a bit of DejaVu when Moto couldnt deliver the 500MHz G4's on time/quantity.
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Also the G4+ will have the 2 Altivec units, 2 FPU units and 4 Integer units each with 32 dedicated registers. Plus it will use the 256bit data paths, integrate up to 1MB level 2 cache on to the die and support up to 4MB level 3 cache. Thats why the PPC will eventullaly pull away they have the space to do more.
They include the L2 cache on some chips, but not others and don't bother to mention size if the cache. Just look at the three different 200MHz PPros that each consume vayring amounts of power since they have 256KB, 512KB, and 1MB caches.
This would be a good graph if your main concern is raw power consumption of a normal processor purchase (I'm sure that you could get cacheless Athlons if you buy enough).
-- "Well, Hello, Mr. Fancy-pants. I've got news for you pal, you ain't in control but two things right now, Jack and s
What would *really* be a nice boost is if it were possible to access the RISC component of the Athlon (ie. bypass the x86 decoder).
Basically, that would allow one to run legacy apps by allowing the Athlon to operate as a smokin' fast x86... and run new apps by allowing the Athlon to operate as a smokin' RISC machine.
And if this could be done in a multitasked environment, so much the better -- running a legacy app *and* a new app simultaneously.
Too much to hope for, I'm sure!
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Why are people trumpeting that the G4 only uses 4 or 5 watts, or whatever? Who cares? The Alpha CPUs, widely regarded as the fastest money can buy, use something like 100 watts, but I'm sure the people that buy them really don't care about that either.
- A.P.
--
"One World, one Web, one Program" - Microsoft promotional ad
"Remember when the U.S. had a drug problem, and then we declared a War On Drugs, and now you can't buy drugs anymore?"
I'm sorry, but I can't even begin to imagine such gross ignorance. It boggles my mind. Hitler couldn't have done half of brainwashing to accomplish this level of ignorance in his wildest dreams. THIS is scary.
All you need in this life is ignorance and confidence -- and then success is sure. Mark Twain
PS: I don't like the G4's either, but you seem to have had just a little too much to drink, or not enough to think that.
I would say even Windows 9x is more stable than the MAC OS, granted I haven't used it since 8.0 but damn was the MAC OS BUGGY as hell.
7.6 and earlier was buggy as hell, and if you're running wacky programs Windows might handle it better. But I'm currently running Mac OS 9, and it only crashes about every two weeks. I think it depends a lot on system configuration. A well configured system on any platform will be more stable than a poorly configured one. But OS 9 is extremely stable if you don't abuse it much.
One advantage that increases Mac OS stability is the smaller number of machine types and more tightly integrated hardware and software. It might be that once you install all the right pieces Windows is as reliable, but getting it there is a pain. And Windows isn't very helpful. Apple has worked hard to ensure that every version of their OS support every recent machine. Their latest (OS 9) supports any machine with a PPC, which will take you back 6 years.
Anyhow, system stability has improved dramatically since system 7, and at this point system configuration is more important than OS features. And it looks like Mac OS X will be out long before Microsoft's NT consumer arrives, so that'll widen Apple's lead in this area.
I didn't mean NT. NT is indeed more stable than Mac OS, but it is not a consumer product. It's too pricey, and is still too complex for Joe Sixpack to set up and use.
Does this guy know anything about architecture?
In a word, yes. He knows an awful lot. If you don't know what "Post-RISC" is talking about, why don't you read his article on RISC vs CISC like he suggested. Here, I'll make it easy for you: RISC vs. CISC: the Post-RISC Era
Of course, it also looks like you didn't even bother to fully read this article. Hannibal is hardly anti-mac, anti G4, or any of that. He concludes that he prefers the G4 over the Athlon (and the Alpha over both of them). Give me a break...
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"Every artist is a cannibal, every poet is a thief."
In general making more stages also decreases the amount of work done per clock cycle. Will Motorola end up with a processor that is truly faster or just higher Mhz? All other things being equal, of course.
It's not the number of courses on computer architecture you've taken that counts. It's the number that you've passed. Come back when that is non-zero.
From the article, I gathered that the Athlon has a better core but is limited by the x86 frontend. My question is - to what end is this frontend changeable? Could AMD theoretically place a different frontend on the Athlon to make it a PPC chip?
And, is this the type of idea that the Crusoe processor is going to have - i.e. modulating the frontend on a chip so it can run many architectures?
The mind ponders.
Linux - Because Mommy taught me to Share.
I haven't seen any comments on the fact that the G4 can easily be modified to work in mobile devices while the Athlon runs rather......warm.
Personally its not God I dislike, its his fan club I cant stand (bash.org)
I think your analogy is a little flawed, since we should only be comparing the chips themselves (like the engine of the car).
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Ahh, there's the rub. Or should we say ``the fly in the ointment''? If a screw-driver shop can't build it, then my interest in the G4 remains but academic. I really don't have a use for ``boutique'' computers.
I just bought a Athlon 700mhz, but the stable series of debian wont install or even boot with an athlon. The unstable series works, but that involves ALOT of work to get shit working. Unless anyone has any resources (how-tos) or information on how they got debian to instlal on there athlons. I would appreciate it. thanks. PS. Sorry for the improper grammer, I cant see what I am typing. I am in windows right now cause I cant get debian installed, and netscape poped up a illegal operation error, but it still allows you to surf the web and write this, it just sorta sticks a error box in your face, s.
Jeff Knox
I can't do better. Given the range of talent represented here, I wouldn't be surprised to find someone who could, but that's irrelevant.
The point is that there is someone out there who can do better. Not necessarily the person posting.
Mod down posts with a "Free Mac Mini/iPod" sig, they're spam!
The Power Mac 5500/225, 5500/250, and it's 6500 counterparts use 486 type fans screwed to the heatsink. They make a lovely racket when their bushings wear out too. Incidentally, Apple laptops aren't fan free either. While it is true they don't employ CPU fans, the G3 Series Powerbooks do have a small recirculating case fan turned sideways in the rear of the units. Some of the other Mac techs could probably come up with more examples.
People seem to have forgotten the point of RISC'ing in the first place. RISC's main point was to give the final control of the system's pipeline speed from the hardware to the compiler.
In true RISC processors (MIPS and SPARC as good examples) the compiler can and does produce an efficient pipeline w/o stalls of any sort. Which means that OOO is wasted on such a chip.
The problem comes in with inefficient compilers and poor resource management. To solve this, hardware dvelopers introduced things like OOO and thread forecasting to allow bad compiling alg's to retain their top speed. But this leads to a bad trend which is quite apparent in the x86 compiling community, allowing the hardware to schedule processes in the end does not encourage compiler developers to make better and better compilers, instead allowing them to "scoot by" without ever learning the art of mastering the pipeline.
There is a new architecture arriving shortly, called VLIW, which is at it's heart nothing but taking the RISC concept one step furthur, forcing the compiler to take it's motley crew of commands and set them up to pipeline efficiently. There are more differences than this, I know, but at it's heart this is pretty much what it is. A good compiler will produce better code than any OOO engine out there can ever manage. Why? Because the programmer knows what he wants, the processor does not. No matter how smart, how many transistors you throw at a problem, a smart programmer with a smart compiler will always turn it on it's head.
Karma Whoring for Fun and Profit.
Regarding some other comments:
The vector unit is state-of-the-art silicon that does way more way faster than your typical SIMD logic. It crunches biiig numbers in vector math, and can be repurposed to do simpler things, like FP math. (There seems to be some confusion whether or not it can do DP or only SP...either way, it -hauls-.)
More to the point, the PowerPC post-RISC strategy is a lot smarter than Intel/AMD's. Mix'n'match logic to create the perfect balance of processor units, and slap four cores on a single slab of silicon. This is where PowerPC is going to be -at- next year.
The problem has been Motorola lagging behind the group. IBM has signed on to crank out the next rev of the G4, and clock speeds are due for a major boost: they demoed 1GHZ tech on the PowerPC platform 2 years ago, and are cooking up 9ghz technology in deep R&D as we speak. Even with the MHZ gap, the design of the G4 is smart enough to keep up with the "big brutes" crunching x86, and the POWER4 (IBM's 64 bit PowerPC implementation for it's RS/6000 Unix and AS/400 "baby mainframe" systems.) will leave IA-64 in the dust before it even gets out of the gate.
Smart money is on the original RISC R&D houses for the edge in the post-RISC sweepstakes: wait'll you get a load of what the Alpha has in store...
SoupIsGood Food
It is true that the PPC has condition code registers, and that having more than one is better than just having a single CC register. But...
The thing that one should note is that, from a CPU design point, condition code registers are often a Bad Thing(tm) - as are instruction "side effects" in general (condition codes being one example). Particularly with superscalar, out-of-order CPUs. They add complexity to the processor's attempts to re-order instructions on the fly. This is in part because the CC regs tend to create additional dependencies between instructions, and often the CC register(s) become a bottleneck. Also, when the CPU tries to reorder instructions, it has to worry not only about whether the reordering will clobber a needed result, but also whether a moved instruction's side effects will do something unintended (ie the moved instruction changes the condition code, and so may not be able to be moved without upsetting the code semantics). These factors tend to constrain the CPU's out-of-order execution unnecessarily, leading to less optimal performance.
Most processors try to avoid CC regs, since they are a centralized resource that can easily become a bottleneck when multiple compares come close together. For example, MIPS (as most RISC CPUs) doesn't use CC regs; if you want to check a condition, there is a compare instruction which will set the value of an integer register. Since said integer register can be any of the many integer regs, rather than a small set of particular registers, there generally aren't the bottlenecking problems like with condition codes. Condition codes are really a CISC-ish thing anyway, and in general RISC processors avoid them.
Adding additional CC registers helps somewhat with loosening that bottleneck, but is really a bit of a kludge around a nasty instruction set artifact in PPC. Not exactly something you'd want to "retrofit" onto an x86 CPU (which has more than its share of nasty instruction set issues already).
I thought its a shame that its stuck pretending to be something its not, and suffering performance as a consequence. Does AMD (or anyone else) have any plans of having native software for this processor?
...well alot of you might not want to anyway but many people have the need to run a windows program once in a while...and that sells alot more processors.
I'm not saying x86 architecture is all that bad, but I bet a version of something like Linux optimized to run natively on the Athelon would outperform an x86 version.
Its x86 compatibility, when needed, is definately a Good Thing(tm) at present - for emulating/running those lesser-operating systems. Can your G4 run windows like a 700 Mhz Pentium?
You'd think that AMD could get a better hold of the 32 bit market by allowing their own technology become a new standard. After a while, they could have chips (maybe marketed for servers at first) with no x86 emulation at all. It wouldn't be needed once their architecture established itself.
Maybe I'm dreaming but I'm just looking for something better on a small budget...and backwards compatibility is nice every once in a while. Is this even possible with the current Athelon?
~J
The gap will never disappear. Intel and AMD are in a price/speed war that will never have a victor.
Eventually each company will own half the earth and they will fight wars with huge robots ala Mechwarrior. When that happens, sign me up for the cause.
--Have a Johsonville brat.
If we're discussing the Win9x vs MacOS "reliability' issue, in my experience Windows has actually been pretty stable (uptimes easily a few weeks, which is as long as I've gone without booting to whatever other OS I may have installed at the moment...typically NT or Linux). Well, I should say Win95 OSR2 or Win98 are pretty stable...the original Win95 was so damn buggy it was ridiculous. Whenever I've used MacOS (most recently, running 8.6) I've had lots of stability problems, to the point that I swear Macs just hate me :-p
:-) OS X does seem like it might actually be pretty good, though I haven't had the chance to use it a whole lot.
But then, there is the configuration factor you mentioned at work here too. My Win98 machine is pretty solid, with not too many modifications from standard setup. The Macs I use (for some of my music classes at school) may or may not be set up all that well, as I have no idea of the competence, or lack thereof, of the Mac admins.
I personally wonder how much of the grief that gets blamed on Windows is due to Windows, and how much due to poor quality hardware. On machines with quality components, I've rarely had any sort of troubles with Windows. Things start getting shaky once you start with some of the really cheap hardware, though, in my experience. I do have to give M$ credit (*gasp*) in the sheer volume of supported hardware they have, and yet maintain a reasonable level of stability.
Apple does have the advantage of a relatively small set of hardware to support. So I would hope they would be able to get a decent OS on it
once it's vendor decided to put the boot in on it OS/2 was doomed, which is a shame because its the best X86 OS
My point was that that there's a very small market for a low-end PC that can't run 'legacy' or old OSes. If you wanted such a thing, you might as well just buy an Alpha.
--
Business. Numbers. Money. People. Computer World.
Something about as technical as the K6/7400 would be perfect. Thanks!
Never refuse a breath mint.
You're off by four orders of magnitude. An extra 50W of power consumption will cost you $20/year if you run 24/7. More if you live in an expensive electric market like I do. When you have multiple boxes (like I do), it adds up. You pay $20 MORE just for the privilege of having a single wasteful CPU.
(I gave up on trying to figure out if anyone said this in the thread below, which descended into non-informative).
The main difference I see between the mac market at the time of the switch and the PC market at just about any time is: nobody ever controlled the pc market at any time. (excepting IBM at the start, which is almost irrelevant as this is the reason for using x86 in the first place)
Apple at the time, and even pretty much now, controlled both sides of the equation. The sold you the hardware and the software. If they decided not to sell you any more 68k mac's. That's it. No other sources for new 68k macs. If gateway did this right now, you could still buy a dell. If AMD did this right now, you could still buy intel.
Also, Apple was the platform. They could make an emulator that worked for everyone because there was only one platform. Who is going to make an emulator that works for all of the x86 plaforms (windows, linux, bsd, beos, etc).