Slashdot Mirror
Sun Working to Eliminate Circuit Boards
lokedhs writes "Sun Microsystems is coming out with new chips without connectors. According to the article, this will have a lot of advantages: 'Performance, for instance, could greatly escalate because the speed of transferring data among chips and the number of channels for the transfers would increase. Energy consumption could also decline. Just as important, overall costs could fall, because defective chips could be removed like Scrabble tiles.' This technology will also lead to new CPU's without cache: 'The technique could also allow designers to remove the cache--the large pool of memory currently found on the processor--and put it on a separate chip. Caches were integrated onto processors to amplify bandwidth. Adding cache, however, bumps up manufacturing costs, as it greatly increases the number of transistors. With the bandwidth constraint gone, caches could once again be made independent without it having an impact on performance.'"
With so many chips so close together, they are certainly going to have heat problems.
Interesting technology, thought.
so basically they want to stack the chips? umm, heat?
They should get together with Pringles or Lays -- they've both been doing this for a while...
This idea has merit, but the explanation is oversimplified. Moving the cache 2 centimeters from on top of the processor to a separate chip may be feasible, but it will increase latency (increasing the number of clockcycles a cache fetch takes and re-affirming a need for an on-chip cache to cache the "cache"). Other applications of this technology (like the fact that any part with issues can be easily replaced) seem more relevant.
What they need, instead is VioletTooth (wireless chip-to-chip communcations). That way, they won't have to worry about alignment problems and such!
Did you even read the article before posting it here. The article talked about eliminating the pin that is used to house the chip. Due to the size of the pins, it limits the number of I/O paths a chip can expose to the motherboard. Instead they can implement transmitter/receivers using capacitive inductence to increase the I/O paths a chip can expose. Thereby increasing the bandwith a chip can utilize.
I figured Sun would have laid off their entire R&D department by now :)
Love,
Zaq
This wireless chips integrated for a purpose thing reminds me of Replicators
Either way, I'm thrilled and spooked.
Um...who repairs motherboards anymore? At around $100 a pop, most people just get a new one.
If there's a high-end application for this technology, great, but getting rid of high-end hardware is one of the biggest reasons people are also getting rid of Sun...
One thing is for sure. If they can get this to work and if heat production can be cut down, this would make computing equipment and electronics much smaller. The printed circuit board is one of the big things holding us back from much better electronics miniaturization.
Just as important, overall costs could fall, because defective chips could be removed like Scrabble tiles.
With my luck I'll get a dead Pentium Z or Q that I just can't get rid of.
The angel in the oatmeal.
Wow, this announcement reminds me of an awesome book I just read: http://www.kuro5hin.org/prime-intellect/mopiidx.ht ml
Think of it as lots of itty bitty low power radio transmitters and receivers.
Sounds clever to me. Electrical engineers have been constantly fighting unwanted interference in their circuits. Now they will be listening for it.
Most likely, the capacitive coupling of signals is only targeting chip to chip data signals, not the supply of power to the chips.
PJRC: Electronic Projects, 8051 Microcontroller Tools
And in other news, scientists are developing a computer with no electronic parts at all!
"Who are in control, they are not in control of anything - they don't even control themselves!" - Glen Beck
Eliminating connectors also removes a problem that pops up in microchips - without connecting wires, you don't have most of the parasitic capacitances that crop up on chips. A capacitor is anything with two metal contacts, so wires (especially parallel wires) cause very small capacitances, usually in the order of several picofarads. The problem is that on microchips, the capacitor values that are being used are generally in that range too, so parasitics can be very problematic.
Heat transfer is also a problem, but I'm not convinced that it would be so different from current heat considerations. The heat should still spread through the chip, regardless of connectors, and dissapate on the chip's surface. Whether they get overly ambitious with stacking these chips is another question.
Dust & dirt. I would imagine that at such low voltage levels, induced current would require a damn near perfect level of alignment between the chip and the "socket". This is admitted in the article. What they don't admit is that it's going to be nearly impossible to get the damn thing in the socket without letting dust or dirt inbetween the chip and the socket.
And a more interesting topic is their consistent mentioning of taking the cache of the chip. That's a nice dream and all, but where the hell are you going to put it then? Hardwired onto the motherboard? That's going to dramatically increase the cost of mobo's (so they are simply shifting who gets to eat the high sticker price on their products). And what if I buy a quad capable mobo, but only put 2 processors on it, I'm effectively wasting 2 sets of cache, rather than simply wasting 2 cpu sockets, and the sockets are a hell of a lot cheaper than the cache. I suppose you could fix this by going back to COAST (cache on a stick, yeah i know you remember that nasty stuff). But that brings in a whole new problem: These days, cache is only fast because it's so close to the cpu. If they move it off the die, it's just going to be put back on in 2 years because we can't access the cache fast enough ever since we moved it off the die.
I'm no super computer engineer, but these guys better have an entire family of rabbits they plan on pulling out of their asses or this fucker's gonna flop.
It appears some people have managed to implement chip stacking for faster RAM among other things (check out the prototype pix).
--- You shall know the truth, and the truth shall make you mad- Neal (not Cowboy) Boortz
This was posted back in September of last year :
m l?tid=102&tid=137&tid=187
http://slashdot.org/articles/03/09/22/1055244.sht
jdb2
With this connectivity, there would seem to be a need to standardize CPU chip speeds. Otherwise, a multi-CPU system w/disparate chip speeds would need a sophisticated register design to allow the faster chips to 'idle' while the slow one occupies a needed memory address.
If designed, however, this could allow admins to assign quickie chips to the OLTP (or DSS batch loads @ night) systems, and the slower CPUs to the less intensive tasks (like sys admin).
so basically they want to stack the chips? umm, heat?
It has to be said, I think that if Sun are seriously thinking of producing such chips then it must be a moderately good idea (they're not monkeys after all), so I wouldn't write it off on the basis of heat concerns.
You've probably noticed that people's noses get bigger as they get older. That's because old people are huge liars.
Wow. It will be even easier to bug a computer, just drop a survailiance device in it, or near it (preferably with a small flashing led on it, to the Mission Impossible soundtrack).
When asked why, the answer is almost always: "It's 2014".
Well, this is offtopic, but there's no place to discuss the problems Slashdot has been experiencing, so why not here? If the admins won't provide an appropriate forum, we have no other choice.
Does anyone have any idea what's going on here? I can't be the only one who wishes for a front-page story explaining why Slashdot is so amazingly unreliable and broken lately--especially for subscribers who are paying $ for this service.
The article mentions "capacitive coupling". Here is the relevant WikiPedia entry, and here's a paper on the specifics at Sun.
If you stack chips, then each chip can only communicate with chips right next to it (am I wrong?) So you'd be able to communicate directly with 2-6 chips, otherwise the chips would have to relay through each other, like a daisy chain. Hopefully none of them would break that communication, otherwise you could have a motherboard "chip" relay messages between them all.
Let's see, in 2 weeks the've anounced that they were looking a buying Novell and getting rid of circuit boards. I guess a positronic brain will be next.
"Eve of Destruction", it's not just for old hippies anymore...
This side up.
...as will your friendly neighborhood competitor, spy organization, etc. And you thought the Tempest effect was bad.
As an aside, I guess I'll have to stop Gaff Taping my CPU into the socket.
[% slash_sig_val.text %]
Multiple communications channels between chips can be used. Each channel uses an individual pad slightly embedded in each chip, and the pads in each chip have to be physically aligned to some extent. This has two advantages... because the pads are done on-die and not outside the chip, the pads can be two orders of magnitude smaller than external pins. Also, the pins are protected from electrostatic discharge. The summary at the end of the article says:
- Our 350nm CMOS test chip demonstrates 16 channels operating simultaneously, each communicating pseudo random patterns at a rate of 1.35 Gbps, for an aggregate bandwidth of 21.6 Gbps.
In other words, it looks pretty viable...Well.... You can do that. And you can have a lot more than four interconnects per chips. However the "simple optical connections" are anything but simple. Look into (forgive the pun) photonic switching fabrics for more info. Cray Inc. is looking into optically coupled chips for their Cascade project (DARPA supercompute-off). Sun just thinks capacitive coupling is the way to go. As far as the heat goes... it doesn't generate as much heat as real connections, as little or no current is flowing.
I work in a Faraday Cage, you insensitive cl... err... you insightful... uh...
Maybe the next step is for all the components to come in lego bricks. The self-organizing bus won't care what order you put them together in, so whenever you add a component (50 GB flash drive, GPU, firewire ports, ect.) you just click it on somewhere, and it adds it into the system.
Can anyone tell me how to set my sig on Slashdot?
Sun is the company I hate to hate. They have some of the brightest people in-house and create some amazing tech and ALWAYS seem to crap the bed on the business side. What good is a beautiful baby boy when it ends up being still-born? Man, I wish IBM just officially turn them into an R&D department.
-_-
As for the technique of capacitive coupling, that is how signals used to pass through low voltage amps virtually since the triode tube. The technique has been used for isolation amplifiers for many years. The signal on one side of the voltage barrier is digitised in some way (perhaps just PCM) and transmitted across a voltage barrier using very small capacitors, to where it is decoded. In some cases, power for the input side is also transmitted by capacitive coupling across the barrier.
Because the transmitting and receiving side of the capacitors is so tiny and the electric field therefore so constrained, it is not going to be possible to read the signals with an external aerial.
I believe Philips, among others, earlier suggested using LEDs and photodiodes along the edges of packages, but appart from requiring power they could only be unidirectional. Capacitive coupling itself absorbs begligible power and can be fully bidirectional.
Panurge has posted for the last time. Thanks for the positive moderations.
The problem with capacitive connections is that you are, for all intents and purposes, using small radio links. This causes several issues to come to the fore:
- Your immunity to cross-talk goes down. Misalignment will exacerbate these problems.
- Capacitive receivers will also be able to pick up local RF fields. The computer will be much more vulnerable to external interference than it was before.
- The computer will also radiate much more than it did before, creating more RFI and leaking information that might be crucial (like crypto keys).
Making the chips the meat in a sandwich with metal sheets for the bread would help this a lot, because tightly coupled ground planes attenuate both radiation and reception. As long as you're putting a ground plane on top of the assembly it might as well do double duty as a cooling device, though I wonder what effect the heat-transfer compounds would have on transmission and crosstalk.Sustainability and energy independence essay
Just to clearify to the un-initiated. It is the exact same technique that allows CMOS transistors to work (the basis of most CPU transistors).
CMOS-FET = Complementary Metal Oxide Semiconductor - Field Effect Transistor
That's semiconductors separated by oxide (oxidized silicone or glass) to allow fields derived from differing voltages on either side of the glass to affect conductivity and thereby provide actuatable signals. All this new system does is replace the Oxide with something else; namely the walls of the outside of the chip and the unavoidable air-gap.
Obviously this alternate medium is not as efficient as normal hyper-thin glass, BUT it's more efficient than transferring physical electrons from silicon to copper and amplifying it such that you can induce a measurable current down the coppy wire several centimeters away. More-over, it's more practical to etch micro-wire paths on the edge of a chip than to manually pin-punch chips like we do today. We can make such signal points smaller and more articulate.
The ONLY problem (as outlined in the article) is keeping these micro-signals aligned.. If you're off by even half a capacitive cell, then you're fields aren't going to be strong enough, and depending on cell-spacing, you're likely to generate noise to adjacent cells.
-Michael
so basically they want to stack the chips? umm, heat?
Re-read article. It's not a stack. They make reference to scrabble tiles as a comparison.
Even if it were a stack liquid cooling built directly into the stack, ala the internal combustion engine, could handle the heat effectively. Probably more effectively then our current heat sink technology.
TW
It is so lucky for Sun that Slashdot exists to bring together ignorant people from all over the world to tell them what their professional engineers have been unable to figure out. I'll bet no one down there had considered the fact that wireless transmission is different than wire-based transition. Hopefully some of their people are reading this, and the R&D department can get right on with dismantling the project.
Seriously, I keep clicking the 'read comments' button hoping to read something interesting. Instead, I see a dozen posts by people who read the headline, think 'well that won't work!', and post about it. If you came up with it in half a second, do you think you're the first person to have that very original thought? Come on.
"They think airplanes will be faster? Ha. They've completely forgotten to take headwinds into account. "
http://research.sun.com/async/Publications/KPDisc
jdb2
As long as they don't bring olestra into the mix.
This is a very cool idea and it's the kind of thing I expect from Sun. Once it's stated, the solution almost looks obvious. While there's lots of work needed to make the idea practical, I admire the way they took a big noise problem and used it to propagate signal. It's too bad they are run by someone who thinks that they are going to make their money by licensing software instead of selling chips and licenses to very cool and real inventions.
Friends don't help friends install M$ junk.
I wonder if this could lead to new treatments of spinal injuries? Say you could place a chip intervening between a severed spinal cord. Instead of having to physically attach all those millions of nerve endings, you could have the chip do it by proximity, and carry the signals on past the gap.
BTM
That was the turning point of my life--I went from negative zero to positive zero.
Sun is not "coming out with new chips without connectors". Sun has demonstrated a new kind of interconnect in a lab. They might use it in a DoD funded supercomputer project. Maybe.
You're not going to "stack chips like Scrabble tiles". The unpackaged chips have to be aligned within a few microns and held in position. That's going to be done in an IC packaging facility. The result will be a multi-chip module, a single package containing several chips.
Multi-chip modules have been around for a long time. The Pentium Pro, for example, was a multi-chip module. There's a multi-chip module Linux computer in a single package from ETRAX. Multi-chip modules are expensive and hard to manufacture, and they're generally used only when you need to combine chips that couldn't be manufactured on the same substrate, like a fast CPU and flash memory. They usually cost more than the chips packaged individually. That's why this isn't a mainstream technology.
This new approach might revive the multi-chip module market. Might. This has to become a cheap process before it will be used outside the supercomputer world. A whole generation of automated assembly machinery has to be developed to assemble and align chips in multi-chip modules before this is more than a demo technology. But this looks more promising than the way multi-chip modules are currently made. If it becomes cheaper to put two chips in one package than to put two chips in two packages, this is a significant development. Otherwise, not.
its negative effect on the market, read this one again and be happy.
:)
OSS is bringing down the overall value of computing, which is a good thing for all of us. The increased competition means the big players must begin to really innovate of die slow. The stuff we use everyday should be cheap. Intel did its job on the hardware side of things, OSS is working hard on the Software side.
This is the Sun I am used to seeing. I have said before, their value is in their people --nice to see them putting it to use.
Blogging because I can...
Dean G.
"I have a great mind to believe in Christianity for the mere pleasure of fancying I may be damned."-- some guy named George
It's only a special service given to subscribers. All of us freeloaders have to put up with the normal, always-on service.
Pretty much the same way one aligns a glass fibre in it's termination point...
--dave
davecb@spamcop.net
However, it's probably not a place to discuss it unless you have something to contribute to resolving it.
The next 503 error will be ready soon, but subscribers can beat the rush and see it early!
There is a research paper here that gives a lot more information than the article linked (ironically enough, I happened to be reading it yesterday). They address many of the issues people have brought up (alignment, dust, etc.), and the paper really isn't a hard read.
They actually have a bunch of interesting papers in the parent directory here, mostly covering stuff about asynchronous/clockless computing.
My server
I've managed to 'Eliminate Circuit Boards' without even trying in the past. I need a better soldering iron... and to control my temper
Sun service engineer: I'm trying to fix this CPU, but all I have is sky pieces, anyone have a piece with a little bit of a boat?
It would be good for hobbyists in that the shift to tighter pins and ball grid arrays is making it extremely expensive to fabricate single circuit boards. Imagine buying a bunch of ASICs from digikey, stacking them together with duct tape, and instantly having a custom circuit board. The sides of the chips would only need transmit, recieve, and clock plates.
In manufacturing, the trend is still to integrate more and more on a single die. The cache will still be on the CPU but in addition, so will the system memory, graphics chip, and power supply. One day the 120V AC power cord will plug directly into the CPU.
I must say I'm skeptical about going to serial links for things like memory access. If you go from a 256 bit parallel bus running at 800 MHz to a serial link, your motherboard traces are going to have to carry a signal at something like 200 GHz to get the same bandwidth. Your circuit board is going to need to be a millimeter-wave waveguide, and what are you going to make the transducers shoveling that data over the motherboard out of? You can generate 100 GHz-THz carriers using Gunn diodes, but that's not a signal.
You'd need optical links, and not very long ones. It probably wouldn't reduce the cost of the motherboard, anyway.
They have 5-6 years to work on this whole idea. Every once in a while, people have to go into completely different directions. The engineers at sun are not idiots. Do the people on here actually believe that they're not going to deal with these types of problems that are mentioned here?
Open Source Java DAO Generator
This technology pertains more to chip manufacture than motherboard manufacture. The alignment difficulties alone will prevent this from being seen in the field. According to the research paper, the scientists first aligned the chips using a 10x stereo microscope, then used a Vernier measurement system to align them to within a few microns. There's no way that process will be seen outside of a lab or manufacturing plant.
What this will let chip makers do is to manufacture the cpu and cache on separate silicon wafers, then stack them together and package them as a unit. The researchers claim a speed of 21.6 Gigabits/second using a 4x4 matrix of transmitters. Perhaps we'll see processors being sold with X Gig of memory on-board, with X being the amount of memory that can be manufactured in the same space as the CPU. Perhaps additional processors could be stacked together as well. Imagine putting 4 CPU's and 4 Gig of memory into a spot on a motherboard that takes 1 CPU today. You will still need a printed circuit board to connect to the circuitry that handles the external devices, ports, slots, etc.
Alignment is not a problem. You can use automatic cell matching using a reconfigurable IOB. What you need is an array of cells that has more cells than signals, eg, extra cells on both ends. Then set the chips together, and initialize the entire cell array with an alignment pattern (eg. a pattern that has no repeated sequences. The two chips can then read the other chip's pattern and use that information to determine which cells correspond to which signal. You will of course need to have extra cells both horizontally and vertically.