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AMD Announces Quad Core Tape-Out
Gr8Apes writes "The DailyTech has a snippet wherein AMD announced that quad core Opterons are taped out and will be socket compatible with the current DDR2 Opterons. In fact, all AM3 chips will be socket compatible with AM2 motherboards. For a little historical perspective, AMD's dual-core Opteron was taped out in June 2004, and then officially introduced in late April, 2005.' AMD also claims that the new quad processors will be demo'd this year. Perhaps Core 2 will have a very short reign at the top?" From the article: "The company's press release claims 'AMD plans to deliver to customers in mid-2007 native Quad-Core AMD Opteron processors that incorporate four processor cores on a single die of silicon.'"
Someone care to explain what that means?
Does it have something to do with the design being finalized, or the manufacturing facility being prepared to start making them (like a game "going gold")?
This space intentionally left blank.
Per TFA, "completion of the design". I was also confused by this phrase in the summary.
Ben Hocking
Need a professional organizer?
All AMD needs to make these new chips a success is to have Steve Jobs use bogus marketing compiler generated SPEC scores...
And flood the x86 review sites with mountains of cash...
Worked for Intel...
K8L has double the FP units per core and twice the internal memory bandwidth as the current K8. Plus with 2 extra cores. 2007 is going to be very interesting
I'm interested to see if software companies who license their software by CPU will continue to define a "CPU" as a physical socket, or a core. Right now Microsoft and VMWare (and lots of others) define a CPU as a physical socket, not a core. So a dual core processor only counts as one CPU for licensing purposes.
It will suck if they start realizing how much more money they could be making by defining a core as a CPU for licensing...
I am glad to see AMD making progress on its quad core chip. No longer can megahertz bring mega bucks. Moore's law doesn't mean Moore money. (Ok, I'll stop now.) We have seen more chip innovation over that past 4 years than I thought was possible.
In case you are wondering what the differences are between AMD and Intel in quad core designs, this comes from TFA:"Intel has recently accelerated its quad-core plans; the company recently announced that quad-core desktop and server chips will be available this year. Intel's initial quad-core designs are significantly different than AMD's approach. The quad-core Intel Kentsfield processor is essentially two Conroe dice attached to the same package. AMD's native quad-core, on the other hand, incorporates all four cores onto the same die."
I cannot wait for comparative benchmarks. I wonder how much ground Intel will gain by being first to market.
Information wants a fueled airplane waiting at the hangar and no one gets hurt.
Isn't AMD depending on additional cores to beat Intel's performance similar to how Intel's Prescott depended on additional MHz to beat AMD's performance?
Sounds like the shoe's on the other foot. I hope AMD brings back the kind of engineering innovations that brought it support among those in the know back in 1999 and 2000.. (Like focusing on a superscalar architecture with the K7.)
Four cores is a fine concept, but they mustn't forget to increase the capabilities of the individual cores.
tasks(723) drafts(105) languages(484) examples(29106)
JESUS.
That means I can get a 32-way system in that Tyan 5U case.
That's just friggin' ludicrous.
IIRC, 32-cores is the limit for the current generation of Hypertransport. I think it has a 6-bit address and half of them are reserved for memory controllers. And that doesn't include I/O MCPs. So the practical limit is 28 (7x4).
THIS THING CAN TURN ON A DIME, MACROSSZERO STYLE ALSO FUCK BETA, ~NYORON
Back in the old days when you finished a chip design, you sent a tape of it to the chip foundry, thus "taped out". These days you just ftp the files, but "ftped out" doesn't sound as good.
Tapeout is when the designers are finished with deciding where all the transistors and such are on the chip (layout), and the layout data files are sent over to the mask-maker to be changed to the masks (basically things you shine light, xrays, whatever through in order to put those designs on the chips during fabrication). Long long ago, actual tape was used for masks.
And now I know. Gracias.
You are so boring that when I see you my feet go to sleep.
Way back in the 1960's the way you designed a printed circuit board, or an integrated circuit, was to get a big piece of clear plastic and lay out the lines with red tape. They used red tape so you could see through it, in order to align the tape exactly over the layer below ( most PC boards use at least two layers, IC's at least 5 layers.) As you can imagine, a rather tedious, error-prone process.
When you were done with the tape and exacto knifes, you'd hand the plastic over to the foundry guys, who would photographically reduce each layer to the appropriate microscopic masks.
Sometime in the mid 70's, computers and optical printers got cheap and good enough so you could actually design the lines and layers on a COMPUTER SCREEN. Sales of red tape went way down. Nobody missed the red-tape days.
Nowdays just about everything is computerized in this process. THere's never a plastic sheet or tape or paper stage-- the bit images go directly form the design mprogram to the foundry.
But they still say "The design got "taped out"."
It took AMD a very long time to create a low-wattage version of the dual core 280. With four cores burning away on the new chip, I wonder how efficient putting a quad-core chip on a server board will be. Right now, most servers are running more than 80W per chip, making for a massive thermal dissipation problem. There's a lot of heat to shunt away from the chip, after all.
.. 25W .. over having a quad core monster at over 140W!
I'd rather have an ultra-efficient dual core chip, sayyyy
"Don't worry about the problems you have in mathematics, I assure you mine are much greater." - Einstein c.1919
Depleted, Bankrupt, Barren, Destitute, Drained, Exhausted, Impoverished, Spent. Oops, my new glasses added an extra "p".
I have been an AMD fan and user ever since I built my first AMD 486 DX4/100 system back in the day.
Currently I still use an Athlon 700MHz system, and just built a socket 939 X2 +3800 system for my wife.
I have never had trouble with AMD based system. Love'em.
Kudos to you, AMD.
Uh, Linux geek since 1999.
Soon there will be news of your server room melting into the Earth's core from the heat.
This will happen 4 times before they plan to do a recall, thus the name "quad core".
- Adam L. Beberg - The Cosm Project - http://www.mithral.com/
The next step after using mylar and rubylith was using CAD, and sending a nine-track magnetic tape of the data to the foundry. So "tapeout" came to mean writing the final magnetic tape.
Nowdays, of course, the data is usually transferred over the internet, so no tape of any kind is involved (not even duct tape). But it is still called tapeout for historical reasons.
Citing similarities between blade counts in razors and processor counts in servers, Gillette began acquiring shares of AMD in a hostile takeover bid.
A signature always reveals a man's character - and sometimes even his name. -- Evan Esar
...and knowing is half the battle.
G.I. Joooooooooooe!
I'm never buying a processor again. I'm tired of chasing the ultimate hardware ghost around. Console gaming keeps looking better and better to me.
the mods may say you posted flamebait, but to me it's a flame that warms my heart. rock on, brother! --chebucto
Wonder how long it will take for compilers and languages to catch up with the concurrency challenges. Till then, applications will run slower than ever.
[On the desktop, multimedia players, browsers, compilers, IDEs, how many of them will use those cores? Servers seem to be ready though.]
Life is a conviction.
After spending a week of my life trying to work out why Windows Media Encoder 9.0 produced stuttery video on a brand new 4200 x2 based system only to finally pinpoint the ***** processor I have to say Im not impressed with this. No doubt AMD will be showing WMEs huge performance increases with x4 when transcoding but when it doesnt ****** work on broadcasts thats ****** useless.
Unimpressed.
Time to start calling it "Tube Out"
Fascism trolls keeping me up every night. When I starts a preachin', he HITS ME WITH HIS REICH!
And when will Gillette-Intel come out with its five-core Fusion system with the patented "Serving Surface" for a close and comfortable network solution?
Rob
In fact, all AM3 chips will be socket compatible with AM2 motherboards
This is precisely why I recently purchased an Athlon 64 X2 instead of a Core Duo despite glowing reviews of the latter. The Duo is on Intel's ancient 478/775 sockets whereas X2 is on AMD's new AM2 socket. How many more processors can Intel jimmy into those tight little PGAs? AM2 will have legs for years to come while early adopters of Duo will be buying new motherboards with their next CPU upgrades.
AMD is announcing TAPE-OUTS now! How pathetic!
It's at least a year from shipping.
https://www.accountkiller.com/removal-requested
It's no unusual at all for for 'heritage' terminology to survive past the technology or system that inspired it - because the understanding of the term is still widely held.
For example - the 'Christmas Tree', the section of a submarines ballast control panel that displays the status of the hatches and various important valves. It was originally called that because it used red (to indicate open) and green (to indicate shut) lights. That evolved into a system that used red circles (open) and red bars (shut) - but it's still called a Christmas tree. (And probably still will be when the BCP communicates its status to the control party via AI brain implants.)
i clicked on the read more... just to see this comment, because i knew it'd be there. never fails that i hear someone asking what taped-out means whenever it's used.... i learned about it at a hardware talk while an intern at apple years ago
to email me: take my
It's still vaporware, as far as we're concerned.
Having worked for motorola's semiconductor group I am familiar with the term. The wikipedia describes it as:
"The term refers to the writing of the magnetic tape with the final data file describing the circuit layout and other details. The term is still used even though magnetic tapes are now rarely used for this process."
The tape(s) is then sent to the fab.
That is incorrect in the ic mask layout terminology. Tape out specifically refers to converting and sending "tape reels" with the polygon data for chip manufacture. Now a days we use the net or CDS, etc, but the term still applies.
Write your code in Java. Concurrency utilities are built right into 1.5 on up. With these processors, it should no longer be an issue...
;)
Now I know I just lost any karma this story might have gained me....
The cesspool just got a check and balance.
Wake me up when AMD has 65 nm scale cores. The vast majority of Dou Core 2 Duo Conroe Core whatever performance and efficiency gains are due to the differences between 90 and 65 nm features. Smaller scale means more execution units and more sophisticated cache logic on the same die. Until AMD does 65 nm their products will be either too hot or too slow.
We've been at 90 nm for so long people almost forgot what a massive improvement a smaller node size can make. Various AMD 65 nm engineering samples are floating around Asia and AMD has made announcements about various 65 nm models appearing Q4 06, early 2007. This is the real battle. However, no mention of what these quad-core parts are supposed to be using...
Lurking at the bottom of the gravity well, getting old
Are they stuffing two die on a package, or is it to 4 cores on a die?
Article didn't specify.
I'd be surprised if their process yields could handle 4 cores and be profitable.
The Quad Core Tap Out sounds like it would be a good name for a wrestling submission.
Before long these guys are going to be moving in on the CPU cooler business.
Pining for the fjords
Honestly, can you use 4 cores in any of your current applications? I think the time is coming when the 30 year trend in faster CPUs will end. If you can't increase the mega-herts, and extra cores don't actually improve application performance, what will Intel and AMD do to keep improving their products? I wrote an essay with some possible ideas: Computers in 2020
augment your senses: http://sensebridge.net/
Taping out is the equivalent of an alpha release of software, I think. I've worked with new processor designs before. On the project on which I worked, the first processors were designated "Engineering Samples" and were marked ES1, ES2, ES3, etc. Then after most of the major bugs were worked out, they were designated "Working Samples" and they were marked WS1, WS2, WS3, etc. After all the known bugs were fixed, it went into production and was designated "Final Cut" and marked FC1, and subsequent bugfixes in the production version were FC2, FC3, etc. So with this naming convention, basically "taping out" means they have a ES1. Toshi
Why? Intel says they will likely be releasing their quad-core chips this year. (Both Xeon and 'Core Extreme'. I wonder if they'll call it the Core 2 Extreme still, or if they'll go for Core 2 Quad?)
Another non-functioning site was "uncertainty.microsoft.com."
The purpose of that site was not known.
How do you think that integrated circuit design was handled before it was done on computers?
"Prefiero morir de pie que vivir siempre arrodillado!"
If you can put four cores on a chunk of silicon, you can put the whole darn computer on a chip. I can't prove it but I bet two cores plus a bunch of memory on the chip is faster than four cores plus the memory off the chip. It's very difficult to design a complex board with a fast front side bus and that puts a limit on how fast off-chip memory can be accessed. There's also no reason we can't put many other functions on the cpu. That's a standard technique for DSPs for instance.
It isn't unknown to put many different functions on an ASIC. One product I am familiar with puts an amazing range of functions on an ASIC. Having many functions on the CPU makes the printed circuit board much cheaper. It probably also saves power. A one chip desktop computer will happen eventually, why not now?
I've just assembled my first SMP box, an AM2 Athlon 64 X2 3800+. Running Windows XP (gaming, video, audio) it is the most unstable thing ever.
Playing a simple MIDI file thru Audigy 2 shuts down the whole computer in a minute or so. Changing game's affinity to just one CPU mid-game shuts down the computer. File copying with the onboard NIC (nForce 570) shuts down the computer - Intel PCI NIC somewhat fixed this.
I somehow blame Microsoft for all this. I doubt that drivers are being written for good SMP support and then such systems suffer with weird system kabooms.
Hopefully Vista 64 bit will fix this stuff. Of course, somewhere in 2009, when we get stable 64 bit drivers and rebuild the whole hardware 3 times till then...
Is it just me? Unstable SMP on Windows XP with games/audio production stuff?
I get your point; however, Moore's Law has nothing AT ALL to do with Megahertz. Instead, it has to do with the number of components (transistors and circuits and such) that can be crammed onto a piece of silicon. From what I remember, Moore's Law states that the number of components that we are able to fit on a piece of silicon will double roughly every 1 1/2 to 2 years. As far as I know, this still holds true with these new dual- and quad- core processors, even though they may run at the same MHz clockspeed.
Gravity is a contributing factor in nearly 73 percent of all accidents involving falling objects. -Dave Barry
I'm not sure if you're pointing out my grammar error or whether it genuinely confused you. By "this phrase" I was refering to "taped out".
Ben Hocking
Need a professional organizer?
So, since it's over the internet, I guess these days you could say it was "tubed out"?
Like 'Dialing' a phone, or better yet 'booting' a computer (from the old tall tales about a man lifting himself into the air by his bootstraps)
also consider the adage: Never underestimate the bandwidth of a station wagon loaded up with backup tapes.
I do see your point, but the PPC derivative in the Playstation 3 is a different beast than the PPC in Xbox360 or in Wii, you know....
It's half-assed of /. summary to say the above without even a mention of Kentsfield, which will probably beat AM3 to market with 4 cores in a single package. Next time give us the whole ass.
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
With Windows Vista soon to arrive, why bother? When XP Pro 1-2 CPU License came out, Dual-CPU (as in dual sockets) was the thing for non-corporate users that built uber-machines. They had the money to pay for it, why not charge them for that capability? Basically, M$ planned for what was "the shit" back then, as opposed to today, where Vista comes in. Microsoft isn't all *THAT* stupid, though I will admit their OS design with integrated everything is pure stupidity. The coders may not know jack, but the marketing droids and the management staff + stockholders have a nice manipulative idea of what' happening, and what will happen.
Still waiting on Serviscope_minor to wake up to fucking reality and realize that Jessica Price isn't going to fuck him.
Can I make a Beowulf cluster of these ?
Intel just got to the 2 cores per die stage. Their 4 core design is 2 dual cores slapped together.
Most people don't care if it's four cores on the die, or two dies inside the package. They both have four cores and plug into a single socket.
It could do untold damage to Intel's ability to sell those quads if AMD's quad solution blows it away,
So far Intel's Core 2 Duo dual cores are beating AMD64-X2 at the top of the market. It's rash of you, to say the least, that when two Intel cores are beating two AMD cores, that somehow four AMD cores will beat four Intel cores.
"It's the height of ridiculousness to say for those 9 lines you get hundreds of millions."
How can you take a slashdot post seriously when you can't even proofread your own copy-paste to make it reads properly? Dice instead of dies?
Anyways, as long as most programmers/games are stuck in serial mode, parallelization isn't going to be mainstream anytime soon except for the science and stock markets, which would require that kind of power. Remember - games can generally task more of a computer than any other program. Games have to deal with everything, because the designer (experienced or not,) has to think of every possible thing in the real world for "immersion."
Still waiting on Serviscope_minor to wake up to fucking reality and realize that Jessica Price isn't going to fuck him.
I guess you missed a few stories. The new cores will most likely be on a 65nm process and will also have 4MB of L3 cache.
That's more than a slight variation from today's CPU.
I agree though, I'm looking forward to more affordable near super-computing power on my desktop. If you compare today's PCs with the super computer I used to run on years ago, it's almost frightening what that little desktop box is capable of. The direct effect of these new CPU releases is to benefit those of us who desire more power in our PCs.
The cesspool just got a check and balance.
I'm looking forward to when "surfing the web" becomes cliche'.
Tubing, anyone?
Do a google search for an image of "widlar" to see the guy that designed many an early Ic, and he's got his cigar resting on a "tapeout".
Back before the dawn of time, when we didn't have dirt yet, we "cut rubies" (used Exacto knives and straightedges to cut Rubylith). People still use Rubylith to do fabric silkscreening and such. No colored tape on paper, not dimensionally stable and not enough contrast for camera-reduction.
-Jay-
It doesn't matter if the server application is programmed to address four cores or more, can the OS itself handle that kind of process priority? Remember DEC Alpha and NT 4.0?
Still waiting on Serviscope_minor to wake up to fucking reality and realize that Jessica Price isn't going to fuck him.
They won't care until one performes significantly better than the other.
Conversely, it's rash of you to make TBBA's. (That's Truth by Blatant Assertion). Let me show you how that works, prior to Core 2 - It's rash of you to say the new CPU with 2 Intel cores will beat 2 AMD cores, since even a single AMD core already trounces the Pentium Dual Core CPU.
It completely ignores all relevant facts. The new AMD cores will most likely be 65nm, putting them on the same footing as Intel's new chips. The AMD quad to Intel quad can be closely compared to the previous Intel Pentium "Dual Core" - 2 slapped together cores - vs AMD's dual core on a single die. Many of the same dynamics exist, with one major difference - AMD is doing with the quad what Intel did with the Core 2 - the AMD quad is sharing 4MB of L3 cache. That's one more level than Intel's offering, btw. Intel's quad will be 2 Core 2's slapped together, sharing a single FSB. AMD doesn't have a FSB bottleneck. Anandtech's review of the Core 2 comes up just short of stating that the FSB is going to bottleneck Intel's 2P system (Woodcrest) probably, and wisely, waiting until 2P benchmarks come in. We're all waiting on those, as they will reveal much.
In any case, I am speculating and stated as much as I backed my speculation with what information has been released to date. You are free to draw your conclusions however you'd like, but do so with some basis on known facts.
The cesspool just got a check and balance.
Mylar.
My title is Sr. IC Mask Layout Designer / CAD Engineer, I'm sorry what was yours again?? ... ]
http://www.answers.com/topic/tape-out
tape-out
[
The term refers to the writing of the magnetic tape with the final data file describing the circuit layout and other details. The term is still used even though magnetic tapes are now rarely used for this process.
Thanks.
... the amount of wire needed to bridge the two dies together.
AMD's hypertransport so far blows everything Intel has out of the water. I run an AMD 64 3000+ Socket 754 with HyperTransport 2.0, and I can easily tell the difference (In perceptible loading times for games and 3-d engines like Blender3D) just by using my metronome at 120 BPM and counting the ticks.
Just as an FYI - I prepared this little test on both systems, using only my metronome at 120 BPM.
System 1
2.0 GHZ P4 w 512K L2 cache and 64 K L1 cache.
1024 Megs Corsair DDR-DRAM
SuperMicro P4SDA+ motherboard
20 Gig WD 5400 RPM HDD ATA 100
256 GeForceX 6200 PNY
SBLive! 5.1 Digital
Intel Proset 10/100 Ethernet
System 2
2.0 GHZ AMD Athlon 3000 + x64 w/ 640 K Cache (assumed 512 KB L2 Cache + 128 L1 Cache since I don't have a clue and am too lazy to look up AMD specs)
1024 Megs Corsair DDR-DRAM (Same sticks from the other system*)
Gigabyte K8u Motherboard (Yes a diff mobo with diff capabilites but I'm only comparing the GHZ race, here, with 32 vs 64 bit performance on a 32-bit OS)
20 Gig WD 5400 RPM HDD ATA 100*
256 GeForceX 6200 PNY*
SBLive! 5.1 Digital*
Intel Proset 10/100 Ethernet*
AMD Kills Intel just by the few measurements of the main games I run using a metronome as a timer - those measurements are perceived speed of loading, actual load time, and average FPS. To a simple normal consumer standpoint, AMD beats Intel hands-down, were they to actually make a detailed comparison to the two chipmakers. I'm not trying to be a troll - this is pure RL testing, since I have both machines that I've mentioned side-by-side with each other. These are my RL results - YMMV.
Still waiting on Serviscope_minor to wake up to fucking reality and realize that Jessica Price isn't going to fuck him.
in a real sense, the rush to multicore is pure laziness on the part of chip designers. yes, there are some interesting issues that come up when you replicate the cpu 4 times on one chip or package. but fundamentally, the real win is in the microarchitecture of a single core. and I really, really hope AMD hasn't botched it there, since Intel has the ability to pull some pretty nice stuff out of their hats.
right now, even dual-core opterons are not a clear win because of factors inherent to multi-core, such as how all external resources, already limited, become more highly contended, and how multicore products lag in clock. and don't forget that Amdahl's law is still in force - you may be happy about the throughput in parallel sections of your code/workflow, but your actual happiness is often dominated by serial sections and therefore single-core performance. with many parallel processors, you _only_ care about the serial sections!
it may be that AMD has done enough tweaks to the K8L core to stay competitive. we don't know yet, unfortunately. the worrisome thing is they're trying to transition to 65nm, 300mm, quad and a new core all in one step. I'd personally be a lot happier if they had test versions of a single-core K8L out now, for instance.
If you don't fundamentally understand parallelism, Java isn't going to help you. I mean, so it's got a "synchronized" keyword. So what? You've still got to know at what granularity you want to synchronize stuff, you've still got to avoid deadlocks and race conditions, etc.
The only thing hyping Java as a magic silver bullet will do is encourage the creation of a lot of buggy threaded code.
"[Regarding the 'cloud,'] ownership was what made America different than Russia." -- Woz
What I'd really like is asymetric cores... something like a really power efficient simple 1Mhz core, but when needed, a more powerful 2Mhz core steps in... then a 4Mhz core, then 8Mhz core... The box can have like 32 cores, each one 2x as fast as the last... (oh, I wish!) while 99.9% of the time, you're only using the simple 1Mhz one (ie: how much cpu power does it really take to update the clock?).
(it doesn't have to start at 1Mhz... it could start at 100Mhz, jump to 500Mhz 2nd core... 1Ghz 3rd core... and 2Ghz 4th core---so an idle CPU would use very little power).
Besides, most of the time, you won't use the cores equally anyway. You'll likely run 1 "heavy" app (some game), and a few very light ones.
"If anything can go wrong, it will." - Murphy
I don't want one now, too little too late.
All this multi-core stuff is great, but is software keeping pace? It's nice to multitask more quickly, but unless I am mistaken that extra core doesn't help when you are playing a 3d game.
(I read that Unreal's upcoming "Gemini" rendering engine will be multi-threaded on the PS3. Hopefully that'll mean it supports multiple procs on the PC too.)
http://www.sun.com/processors/UltraSPARC-T1/index. xml - 32 hardware threads in one package.
n dex.jsp
Which powers the record-breaking T1000/T2000 servers: http://www.sun.com/servers/coolthreads/overview/i
you had me at #!
Claiming you have a relevant and authoritative title and citing (indirectly) wikipedia is hardly a convincing technique for arguing on slashdot.
"Prefiero morir de pie que vivir siempre arrodillado!"
I bet you're wrong. Nearly every geek on the planet knows what "taped out" means when it comes to chip fabrication. It's not exactly a secret.
Tape still playes a small but pivotal role in the test chips we design here. There's a bug in one of the power pins for our pad ring, so we use tape to mask off that pin so it doesn't cause a short circuit (and we continue to use the same pad ring, since no one wants to bother fixing it for internal test chips). We also had a case where we sent two different chips out to get manufactured on the same run, and got half a lot of each chip back. However, they weren't labeled, and there wasn't any way to tell which chip they were from the outside. We ended up prying the covers off, looking at an identifying mark on the silicon, and then taping the cover back on (since it didn't want to seal properly after the first removal).
Note: "here" left unspecific to protect the guilty.
Would you care to elaborate on that? I remember Dad doing PCB layouts with both mylar rubylith and mylar tape on clear mylar sheets. These days of course, he uses CADint PCB.
"Prefiero morir de pie que vivir siempre arrodillado!"
I am building a new PC this month, and this doesn't interest me at all.
Having all these cores seems to me to only relate to a few people who run a lot of apps really hard. I'm mean really, how often do you need to play WoW, scan your PC for viruses, and compile an OS at the same time? It just doesn't make sense to me to put a ton of money into a bazillion core processor, when I've used my PII MMX for so long without thinking, "Hey, I sure wish I could run a bazillion apps at once."
Nope, I think I'll stick go with an AMD Duron. Most bang for the buck as I see it.
"In a world that exists without walls and fences, who needs Windows and Gates?"
Nice troll. I'll bet a lot of people actually believe that bullshit. You, sir, are a true crap artist!
You might also refer to the original version of the wikipedia entry on "tape-out"t &diff=62979385&oldid=3700361
http://en.wikipedia.org/w/index.php?title=Tape-ou
"Prefiero morir de pie que vivir siempre arrodillado!"
Yeah, the old entry specifies what tapeout means. I know they used tape to do PCB/etc layout. But we're talking about tapeout not tape.
Intel's first Quad chip will be two dual cores, but they have one coming next year that won't be.
Anandtech's review of the Core 2 comes up just short of stating that the FSB is going to bottleneck Intel's 2P system (Woodcrest) probably, and wisely, waiting until 2P benchmarks come in. We're all waiting on those, as they will reveal much.
The Woodcrest system doesn't share an FSB between the processor sockets, each being a little faster on the FSB than Conroe, so FSB should not be a problem for Woodcrest systems. It might be a problem for Clovertown.
I am curious what sort of single user app will show a difference between the dual-die approach and the single die approach on the first quad core chips. I remember some mention that the new game engines support dual core capable, but can they take advantage of a quad? I don't think media encoding will be hurt as that's mostly processor power.
The question, however, is this: Is it WORTH it to put the entire computer on a chip?
The memory controller is already on the chip. Looking at the rest of the motherboard stuff, like the PCI/PCI-X/PCI-E busses, audio, serial, ethernet, etc., it's not cost-effective. They can be manufactured to fully sufficient speeds on much less expensive processes.
The only other chip that would make any sense would be a GPU - but GPUs aren't usually so much cycle-limitted as bandwidth-limitted. Besides that, quad-core chips are clearly server-oriented chips, and most servers don't need that sort of video power.
steve
Oh, you're not stuck, you're just unable to let go of the onion rings.
> we still also "dial" the phone
Interestingly, in China, they have been "hitting" the phone since there were phones. "Da dianhua" is much more appropriate with touchpads than it was with rotary dials.
-I like my women like I like my tea: green-
Back in the mid-60's people were using black crepe-paper tape (like masking tape but black and stretchy) for laying out PC boards. Being 'stretchy' allowed it to bend around corners. Large sheets of clear film were used and aligned front to back by punching a hole in the sheet corners with a 1/4 inch diameter pins to keep them lined up. Then the board pattern was taped onto the sheets of film; topside on one layer and bottomside on another. A few designs used more layers. Mostly these were 4X actual size. These taped sheets were then reduced in a photo darkroom and used to make a glass photo-mask of actual size.
However alignment remained a problem, so some company came up with the process of using red and blue plastic tape for the front and back sides of the board and these were both put on the same large piece of 4X plastic sheet. That way the front and back were always in alignment. A red or blue filter was used in the photo lab to expose only one of the colors for each layer.
The same processes were used for large IC's well into the '70s and pictures appeared on covers of various publications when the 6800, 6500, and 8085 processors hit the market. I was not in the semi-conductor industry, but I have never read any article that said a board was "taped-out" when it was put on magnetic tape for manufacturing. It was nearly always used to tell management that the physical board layout was nearly complete and ready. Sometimes the taping took weeks.
When large high-resolution computer moniters became available, the red-blue became obsolete and the board design went straight to magnet tape for the Gerber-Plotter. However, I never heard any person refer to this as being "taped-out".
AMD will really miss an opportunity if they call the new chip anything other than Tetrathlon.
-- Ed Avis ed@membled.com
I think the phrase referred to in times past, when the design for a chip was literally made into masks for the photo-etching process by taping patterns onto plates.
Now you'd probably have to go to a museum to actually see this being done (or to somebody who was doing it as a hobby or project, which is where I've seen it), but the language has stuck.
When a design has been "taped out," it's basically ready for production; it's ready to be actually etched into the silicon and for the manufacturing process to begin.
"Ladies and gentlemen, my killbot features Lotus Notes and a machine gun. It is the finest available."
Personally, I could care less how many cores a computer has, never the less, I'm glad to see AMD inspire some hardware competition at a time where consumer computing (video games, editing videos, downloading porn, etc.) is dominating the market.
It's good to see someone is thinking with their big head.
/Uh, huh, sure you're working there, Spanky. Get back to some REAL work.
The Rapture is NOT an exit strategy.
I think the phrase referred to in times past, when the design for a chip was literally made into masks for the photo-etching process by taping patterns onto plates.
Ah, like when we did photo-etching for printed circuit boards (PCB's!)
A feeling of having made the same mistake before: Deja Foobar
That's 40 cores in 5U. Which is a good density but can't match the throughput of processors with quadruple SPEC scores. Plus there's only one FPU and vector unit for the whole die which totally kills it for any kind of media or scientific processing (which is pretty much the only reason why you want a massive N-way system anymore).
:-( ]
:-D
T1 is good for running IO bound java apps, a server for thin clients running interactive COTS Solaris applications, and virtual web hosting. That's about it.
It's not even very good for databases because it lacks the memory bandwidth having to share one crossbar among all 8 cores [ and a single bank of DDR...
If someone were to come out with an x86-compatible T1-like device it would kick ass for virtualizing windows servers though (for the same reason one hooks up a bunch of Sun Rays to a T1)
Put all those propietary apps in one place with one node license... need a dev box? Sure... let me clone one for you.
THIS THING CAN TURN ON A DIME, MACROSSZERO STYLE ALSO FUCK BETA, ~NYORON
Single user apps that would benefit:
That's enough
The cesspool just got a check and balance.
The last sentence of the poster's comment is unsupported by all available evidence. Intel is scheduled to go quad-core this year, while AMD has a chip "taped out", which means probably sometime in the middle of next year. Thus, Core appears, in fact, to be at least maintaining its lead over AMD, if not expanding it.
E pluribus unum
It has been done for many years already - Cyrix MediaGX / NS/AMD Geode. Typically used in embedded and appliance computers.
With AMD merging with ATI, it wouldn't be a huge surprise if we see an upgraded all-in-one chip in the future. Perhaps targeted at low-end notebooks and media appliances.
If J.K.R wrote Windows: Puteulanus fenestra mortalis!
I guess I'll skip this one to get in line for the next generation 64 or 128 cores processor.
Tyan had a 4-sockets K8 motherboard for 1U servers. You would have 16 cores/1U, which means 80 cores per 5U. Definitely better !
willy
The blurb at the top suggests that this will replace Intel's Core 2's. I think not, because this will be used in the server market and Intel's Core 2's are for the desktop/notebook market. So I'm pretty sure they will both go about their sweet business without needing to worry about each other.
AMD has to change their socket all the time because they bring the memory bus to the socket. Want to go from DDR to DDR2? AMD has to change their socket. Want to go to FB-DIMMs? New socket.
Since the memory controller isn't on the CPU on Intel, that means they can keep the same socket longer. They do have to up the FSB speed from time to time (775 started at 800FSB, and is at 1333FSB now), but the socket didn't have to change.
To be honest, as the power spec to the CPU often gets tightened or increased with new chips anyway, you can't really use old mobos with new chips anyway. There were plenty of socket 939 mobos made that never could take an X2.
Kinda funny too that when X2 came out in the 939 socket, people were like "yeah, same socket, that's a good thing!", but when Core 2 Duo comes out in the same socket, some people instead say "same socket, that's a bad thing!"
Anyway, I'm sure you already know 775 isn't a PGA socket. It's an LGA, just like AMD just went to.
Intel's Kentsfield 4-core CPUs (two dice, two cores per die) fit in 775 just fine. Also their next 4-core CPU which uses 4 cores on one die will fit also. That's a lot of expansion capability.
Anyway, I don't mind buying new mobos, I usually buy the $400 version of a CPU, and so sporting $150 for a mobo too isn't something that bothers me. Old mobos don't necessarily provide max performance for the new chips anyway, even if they are compatible. I know others that don't have as much to spend would feel differently.
http://lkml.org/lkml/2005/8/20/95
My Title is "Friend of Bob Pease", the guy that designed several LMXXX chips in the early 70's, many still in production after 30 years. He's checking with his buddies to figure out the origin of the term.
I have no problem believing that after the days of rubylith tape and Mylar, the term "taped out" migrated to writing out the data onto mag tape.
We'll know better once Bob gets back with some of the straight poop.
> AMD has to change their socket all the time because they bring the memory bus to the socket. Want to go from DDR to DDR2? AMD has to change their socket. Want to go to FB-DIMMs? New socket.
Not like it really matters. When was the last time you upgraded your motherboard without upgrading your CPU? The other way around is much more common. Personally, I just assume that by the time I want to upgrade my CPU, technology will have advanced such that I need a new motherboard and RAM anyway. Since I've never built a computer less than a year apart (and usually not less than 2 years, except in the case of failures), this has always been true.
-- OpenVerse Visual Chat: http://openverse.com
I didn't realize that 775 was LGA instead of PGA so thanks for the tip.
As for the internal memory controller, I've always liked that decision. I'm a little surprised that the memory controller isn't significantly cheaper than the reams of L2 cache required by Intel chips to stay speedy, but hopefully that logic will become streamlined in future chips. It's interesting to see Intel "brute forcing" on that front with 4MB caches vs. 512KB caches on the AMD side (they made 1MB caches on their early X2s but will stay at 512KB from now on).
Since the vast majority of users don't upgrade their CPUs there might not be many who care about the luxury of keeping an old, albeit possibly outdated motherboard as you said. Hopefully AMD can still be taken seriously in the retail universe in lieu of the suddenly fierce and impressive competition coming from Intel once again.
It baffles me that its become legendary, and that it appears to be common knowledge that it is key in AMD reducing latency.
But I can't figure out how it would do so. And the Core 2 Duos show Intel matching and besting AMD on latency. No cache can truly reduce latency (only mask it on hits), so it's pretty clear to me Intel has matched AMD's latency without an on-chip memory controller.
Also, Intel isn't brute-forcing the FSB with huge caches. The issue here is cache synchronization. AMD has HT to do this, and HT is fast and compact. It's so fast that it allows AMD's entire (excellent) NUMA system. AMD can use piecemeal portions of the L2 cache from one CPU as cache for the other CPU with little overhead (latency). And they can make their caches exclusive, so that the L2 doesn't uselessly overlap the L1.
Intel cannot do this. In the past, each cache was completely independent and the system kept them coherent with MERSI protocol and transactions over the FSB. Since the FSB is so slow, that slowed down each access to a non-exclusive (the E in MERSI) cache line while the core waits to see if anyone has a newer version of the active cache line in their cache. This undercuts the value of a cache, although most lines in the cache will be exclusive at any given time.
With the Core processors, since two cores are on one die, the cores communicate directly across the die to maintain cache coherency. This is similar to AMD's "crossbar switch" (a term almost never used properly) in the X2s. Additionally, Intel can adjust the split in their cache so that either core gets the entire cache (most useful when the other core is halted) or they both share it 50-50. This approximates the L2 sharing AMD gets from NUMA. It's more granular, but it's actually faster per transaction. One notable difference is Intel's system doesn't work across dice, which means that Intel's two die Kentsfield system will again suffer on non-exclusive pages. AMD's 4x4 will suffer vastly less (it can no longer use just the crossbar switch, but HT is still very efficient).
So Intel's caching is in my opinion not Intel brute forcing anything. They may not have a system as elegant as NUMA, but they have applied multiple valid techniques to produce a system that in the general case outperforms AMD's memory system.
Back to the on-chip memory controller, I've designed several very successful systems in the last few years. So successful that there's a 50% chance you own one of them! I'm not going to pretend the consumer products I did are in the same league as Core or Athlon in terms of memory bandwidth. But this experience has highlighted the issues of FSBs, cache coherency, DMA, and memory controllers.
In a system with cache coherency (PCs are cache coherent, as any high performance system must be), the cache controller(s) must see every memory access in the system (even DMAs). In an Intel, that means every memory access must appear on the FSB. Now, that may seem like an obvious statement, but since much of the DMA and the memory controllers both appear on the Northbridge (NB) in a PC, the NB could just route data directly from the DMA controller to the memory and back without putting anything on the FSB, except then the CPU's cache controller would become incoherent, which is bad. AMD puts the cache controller and the memory controller next to each other on one chip, so they can easily communicate (over HT, at least for coherency).
However, putting the memory controller on the CPU means every memory access not only has to be seen by the CPU, but processed by the CPU. DMA memory accesses instead of being send to the CPU for cache snooping instead have to go through the CPU for translation to memory signalling. That means you have to put a LOT of pins on the CPU. Especially in a system with dual-channel DDR2 SDRAM. And those transistors are working hard. This puts more heat into your CPU.
Also, according to common knowledge it increases the memory latency on DMAs. Except I dunno about that common knowledge
http://lkml.org/lkml/2005/8/20/95
Any response from Bob yet?
"Prefiero morir de pie que vivir siempre arrodillado!"
The stuff about AMD's cpu bearing the weight of the DMA requests is really an issue as to whether the DMA requests are slowed down more than an issue of if the CPU would be slowed down by the DMA requests. The CPU would be slowed down by the DMA requests if it didn't have dedicated circuitry to handle it. But if course it does have the circuitry, it couldn't really afford not to. It does add additional complexity and power consumption to the chip though.
http://lkml.org/lkml/2005/8/20/95