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The International Technology Roadmap for Semiconductors is published regularly and has information on the maturity of emerging technologies like carbon. There are many possibilities for "more than Moore" improvement. http://www.itrs.net/Links/2012ITRS/Home2012.htm

What is indeed news is that intel is fielding them first.

Well, while it is nice a slashdot article has finally been written about FinFET's - there may already have been one, I just can't remember - these devices have been widely guessed to be a part of the 22 nm technology node for quite some time. (see: http://www.itrs.net/ and http://en.wikipedia.org/wiki/22_nanometer ).

They offer more effectivity for your gates as the field is not coming from one, but from 3 sides to the channel. That means a bit more scalability, but not much more. There is only a bit of improvement possible for the future in putting the gate below the channel as well (as hard as that may be, i, personally, don't think it would be worthwhile), so this won't save moore's law in the end.

It may not surprise you that they actually haven't been invented by intel, and are not new.

The term has been coined more than 10 years ago ( http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=823848 ) (find one of the free pdf's of this classic paper for yourself)

What is more interesting is how far down these transistors will scale in the extreme ultraviolet processes that are emerging right now.

FTA:

The photonics technology [will] help IBM to achieve its goal of building an exascale computer by 2020

So I guess IBM is in line with the International Technology Roadmap for Semiconductors.
  There has been a lot of research done by the major players in the industry, individual components have been developped (light sources, couplers, phodetectors, optical waveguides, etc...) and IBM just showed they can produce them on-die with standard semiconductor production methods.
That's not the kind of breakthrough the article claims, it is usual incremental progress. And I am quite happy with that.

The structures made by block copolymers can be either functional (or a template to make something functional) or used as a mask (like a photoresist) for chemical etching (so it is, in a way, a replacement for a photoresist). In one of the examples from this paper, the block copolymers are used to template the formation platinum nanowires; these could be used either as a functional structure or as a mask allowing one to etch a very fine striped pattern into the surface. The unique feature of using microwaves is that it speeds up the self-organization of the block copolymer, allowing it to realize a minimum energy configuration (i.e. the desired pattern); other methods have generally required a substantial period of time to fully organize. This method manages to complete the organization in under 4 minutes, which is something that the ITRS (published by the Semiconductor Industry Association, see: http://www.itrs.net/ ) has stated is a necessary step for the commercial implementation of block copolymer lithography. The paper, published in ACS Nano, really goes into details. If you /you institution is not a subscriber, you can still access the Supporting Information free of charge which includes dozens of pictures & SEM images and a video.

(rohtua ht4 eht m'i)
(oops... didn't mean to do that last one anon.)

The structures made by block copolymers can be either functional (or a template to make something functional) or used as a mask (like a photoresist) for chemical etching (so it is, in a way, a replacement for a photoresist). In one of the examples from this paper, the block copolymers are used to template the formation platinum nanowires; these could be used either as a functional structure or as a mask allowing one to etch a very fine striped pattern into the surface. The unique feature of using microwaves is that it speeds up the self-organization of the block copolymer, allowing it to realize a minimum energy configuration (i.e. the desired pattern); other methods have generally required a substantial period of time to fully organize. This method manages to complete the organization in under 4 minutes, which is something that the ITRS (published by the Semiconductor Industry Association, see: http://www.itrs.net/ ) has stated is a necessary step for the commercial implementation of block copolymer lithography. The paper, published in ACS Nano, really goes into details. If you /you institution is not a subscriber, you can still access the Supporting Information free of charge which includes dozens of pictures & SEM images and a video.

(rohtua ht4 eht m'i)

But the only "law" is that the number of transistors doubles in a certain time (something of a self fulfilling prophecy these days since this is the yardstick the chip companies work to).

Yes. That's very real. There is an actual industry-wide roadmap which provides guidance for the entire semiconductor industry. Different parts of the industry have to advance together. Mask-making and wafer exposing technologies, for example, have to advance together, even though the equipment comes from different companies. Device physics, clock rate, and cooling design all go together.

The groups that come up with that roadmap take Moore's Law as a goal. Read the executive summary, especially the chart on page 72. The big change from classical Moore's Law thinking, though, is that it's not just about reducing geometry size any more. Still, the industry projects continuing reductions in geometry size through at least 2017. Still on CMOS, incidentally.

But the only "law" is that the number of transistors doubles in a certain time (something of a self fulfilling prophecy these days since this is the yardstick the chip companies work to).

Yes. That's very real. There is an actual industry-wide roadmap which provides guidance for the entire semiconductor industry. Different parts of the industry have to advance together. Mask-making and wafer exposing technologies, for example, have to advance together, even though the equipment comes from different companies. Device physics, clock rate, and cooling design all go together.

The groups that come up with that roadmap take Moore's Law as a goal. Read the executive summary, especially the chart on page 72. The big change from classical Moore's Law thinking, though, is that it's not just about reducing geometry size any more. Still, the industry projects continuing reductions in geometry size through at least 2017. Still on CMOS, incidentally.

For those unfamiliar with the field of semiconductor design, heres what the sizes mean. The Toshiba press release is about flash. In flash, the actual physical silicon consists of rectangular areas of silicon that have impurities added (aka. doped regions or wells). On top of these doped regions, are thinner parallel "wires" (narrower rectangles) made of poly silicon. The distance between the leading edge of wire and the next is called the pitch. Thus, the half pitch is half that distance. The reason this is important is that half pitch is usually the width of the polysilicon wire and effectively becomes the primary physical characteristic from the point of view of power consumption (leakage), speed and density.

The official roadmap for processes and feature sizes (called process nodes) are published yearly by the International Technology Roadmap for Semiconductors, a consortium of all the fabs. According to the 2009 lithography report. 25nm Flash is supposed to hit full production in 2012, thus inital deployments happen a couple of years before. Effectively Toshiba seems to be hitting the roadmap.

The takeaway being, theres nothing to see here, its progress as usual. The big problem is what happens under 16nm. Thats the point at which current optical lithography is impossible, even using half or quarter wavelength, and EUV with immersion litho.

There have been formal semiconductor roadmaps to the future since 1992. There's an consensus roadmap updated annually by an industry group.

This isn't a blue-sky thing. It tells all the players what they need to do to keep up their part of the technology. The fab-equipment people, the device physics people, the etching people, the mask people, the substrate people, the design tools people, etc. all have to push their parts forward. The roadmap tells them how far each piece has to be pushed.

These roadmaps are available for past years, and you can see how the industry has tracked the roadmap. It's reasonably close for any five year period. The big change in the last decade is that heat dissipation is starting to dominate the problem. The roadmap now focuses on memory devices, which have low activity per cell compared to compute elements and aren't yet power-limited.

The current consensus is that the improvements to known technology can get down to 22nm, and then it gets hard. The roadmap assumes CMOS transistors; other devices are discussed, but aren't factored into the mainline predictions.

Just to back this up more (sorry), you can actually read about how the semiconductor industry works.

They share a certain amount of information with reports, generated by input from a large number of companies, which supply resources through assignees to this organization.

What is this organization?

ITRS - International Technology Roadmap for Semiconductors

http://www.itrs.net/

You can read the latest report (no NDA required!): http://www.itrs.net/Links/2008ITRS/Home2008.htm

More specifically, the 2008 Update Overview: http://www.itrs.net/Links/2008ITRS/Update/2008_Update.pdf

The reports are reworked from the ground up, every other year (odd years), then just a relatively minor refresh on the even years.

So, with just a little time, you can actually read the roadmap used (more or less) by all silicon semiconductor companies (IDMs, Fabs, you name it).

L. Scrub

Just to back this up more (sorry), you can actually read about how the semiconductor industry works.

They share a certain amount of information with reports, generated by input from a large number of companies, which supply resources through assignees to this organization.

What is this organization?

ITRS - International Technology Roadmap for Semiconductors

http://www.itrs.net/

You can read the latest report (no NDA required!): http://www.itrs.net/Links/2008ITRS/Home2008.htm

More specifically, the 2008 Update Overview: http://www.itrs.net/Links/2008ITRS/Update/2008_Update.pdf

The reports are reworked from the ground up, every other year (odd years), then just a relatively minor refresh on the even years.

So, with just a little time, you can actually read the roadmap used (more or less) by all silicon semiconductor companies (IDMs, Fabs, you name it).

L. Scrub

Just to back this up more (sorry), you can actually read about how the semiconductor industry works.

They share a certain amount of information with reports, generated by input from a large number of companies, which supply resources through assignees to this organization.

What is this organization?

ITRS - International Technology Roadmap for Semiconductors

http://www.itrs.net/

You can read the latest report (no NDA required!): http://www.itrs.net/Links/2008ITRS/Home2008.htm

More specifically, the 2008 Update Overview: http://www.itrs.net/Links/2008ITRS/Update/2008_Update.pdf

The reports are reworked from the ground up, every other year (odd years), then just a relatively minor refresh on the even years.

So, with just a little time, you can actually read the roadmap used (more or less) by all silicon semiconductor companies (IDMs, Fabs, you name it).

L. Scrub

I disagree - Intel, for one, has made it into the thing that drives everything they do. It's not a natural law, by any means, but they act as though they HAVE to keep on the track that it predicts. It becomes kind of a self-fulfilling prophecy. I think they hate the idea of showing one of their founders, Gordon Moore, to be wrong, even if the prediction has already far outlived any expected lifetime. And because Intel is such a key player in the semiconductor industry, the ITRS follows.

International Technology Roadmap for Semiconductors

You can read more about it at the ITRS website.

A quick scan of the website reveals this interesting image. The observant will note that with current news progress is already ahead of their curve.

International Technology Roadmap for Semiconductors

You can read more about it at the ITRS website.

A quick scan of the website reveals this interesting image. The observant will note that with current news progress is already ahead of their curve.

International Technology Roadmap for Semiconductors

You can read more about it at the ITRS website.

A quick scan of the website reveals this interesting image. The observant will note that with current news progress is already ahead of their curve.

Look here for the answer:
http://www.itrs.net/Common/2005ITRS/Litho2005.pdf
http://public.itrs.net/Files/2002Update/2002Update -ORTC.pdf

Look here for the answer:
http://www.itrs.net/Common/2005ITRS/Litho2005.pdf
http://public.itrs.net/Files/2002Update/2002Update -ORTC.pdf

They're not exactly arbitrary, but they're not physically imposed (like quantum rules or something) either. They're basically just more-or-less a constant ratio from one down to the next.
The semiconductor companies get together and publish a roadmap called ITRS that says we should all try to get to X nm by 20xx, and here are the challenges, etc.

Now someday we're going to get to one of these technology nodes, as they're called, and find out there really is a fundamental phyiscal limitation that keeps us from going any smaller but we haven't got there yet. (Finally, my sig is directly relevant to what I'm posting!)

Lithography "generations" are determined by an international consortium of semiconductor companies. Long ago Intel, IBM, et al. realized they would not be able to afford the research necessary to advance the the industry (this was all before we were able to go sub-micron). As a result, the ITRS (http://public.itrs.net/) was developed to lay out the necessary groundwork for research and lithography landmarks for the industry. Current generation 90nm, next is 65nm, and 45nm after that. Eventually there's supposed to be a 32nm node, then 11nm with a potential stop over in the 25nm range.

Past that it's anyone's guess. 0.3nm is about the size of a silicon atom, so considering we need to be able to pattern polysilicon and copper at these sizes it doesnt make me too convinced that we'll make it to 11nm reliably...

Then again, they said we'd never make it below 1000nm ...

I thought the same thing. The language is at least fluffy, if not bizarre. The document is peppered with odd sentences like this:

"The older members of the data communications research community spent some of their formative years in the time when data communications was being revolutionized by the creation of a new paradigm: packet switching."

I am a research professional in the areas of data communication and semiconductors, and I find this document very confusing and, well, wierd and perhaps even silly.

Compare this document against the ITRS Semiconductor Technology Roadmap:

http://www.itrs.net/Common/2004Update/2004Update.h tm

When juxtaposed against a thorough document such as the ITRS report, the e2e-vision does look a little bit randomized.

have not been solved. One type of logic found in computers is called CMOS, the other called TTL. TTL has another special implementation that allows it to achieve high clock rates.
What are you talking about ? TTL is a bipolar logic family and has a handful (10-20) gates (NAND/NOR/INVERT) per chip. Each and every microprocessor or ASIC today uses the CMOS logic. And even though some folks are running around talking about the end of CMOS, these folks don't seem think so. They say we can go on till 2018 drawing gate lengths as small as 22nm (or 18nm effective) (Page 15 in the executive summary PDF) since just about everybody in the semiconductor industry is involved in coming up with this roadmap, I think it just be have some validity ...

The new ITRS Roadmap (the successor to the SIA Roadmap) comes out today. This is the semiconductor industry's consensus position on what happens next. Multiple technologies have to advance for each new generation of semiconductors. The roadmap is an attempt to predict the problems ahead.

Someone will probably post an ITRS Roadmap story soon, and this issue can be continued then.

Yes, perhaps they promise less resistance than copper interconnect of the same size, but isn't a diameter of 100nm actually a bit large? Can nanotubes shrink, or is their diameter a chemical requirement? According to the International Technology Roadmap for Semiconductors, copper wiring pitch should now in 2003 already be 245nm. So with 50% spacing between those nanotubes, you're not even talking a 2x improvement in size over current interconnect. What if the things are too big to be used as interconnect for those 35nm gates we're supposed to see in 2007?

The author messes up by paying too much attention to the constant: that is, whether the doubling time is 18 months, 2 years, or some other number. He also worries too much about whether it's an exact exponential or not. It's not. So what? The most amazing thing is that a doubling time exists, meaning that we have exponential growth.

Moore's Law should be read as saying that various measures of transistor density on chips grows as O(exp(t)); this has held for 40 years. Of course, no exponential growth can continue forever.

Much of the recent history of the electronics industry has consisted of treating Moore's Law like a human law, that is, it is the marching order for the entire industry. Everyone from the fabs to the electronic design software houses to the microprocessor manufacturers to the systems houses plans in terms of generations of exponentially increasing density. Even the computer science notion "all problems can be solved by adding an extra level of indirection" implicitly assume that since the processors are getting faster all the time, we can make the code slower if we get more function out of it.

Keeping this exponential scaling process going is a massive undertaking; those interested in the problems at the cutting edge might want to look at the International Technology Roadmap for Semiconductors.

In any case, Moore's law is doomed in the long term. I think it's got another decade or so of life, though, as the researchers have a pretty good handle on the next couple of generations of scaling.

The executive summary of the 2001 edition predicts that in 2016 the drawn gate length for microprocessors will be 13 nanometers (0.013 microns).

Now that we're on the verge of 0.1 micron transistors it is time to dump the microns unit and start using nanometers. The tables in the "International Technology Roadmap for Semiconductors" all use nanometers.

You can get surprisingly close. Laying down monomolecular layers by chemical means is common, for example. Lines with edges smooth to a few atoms are possible.

The limits are in sight, though. Read the SIA Roadmap.

The most authoritative look at the subject is the yearly International Technology Roadmap for Semiconductors available here. It predicts progress through 2016, at least. And in any case the end of scaling (which is what the EE Times article is mostly about) is not necessarily the end of Moore's Law. Increased die size, 3D structures, etc., can keep things moving. More money has been spent studying silicon than any other substance in history.

Anyway, the roadmap goes out for about 15 years, and has some startling predictions (chips will run at .6-.8 volts, but will need about 200W of power) and it covers everything from processors to memory to everything else. Like, ALL the parameters. It's very comprehensive.

So, why should you look at it to see what's going to happen in the next 15 years? Because the ITRS is extremely important for the industry. All the chip manufacturers, all the test equipment manufacturers, all the materials manufacturers... they all look at the ITRS to see what they need to work on. The Silicon industry is made up of hundreds of companies, and in order to get them all to meet up at the same place to continue making faster stuff, they need to all be working towards the same goal... and so they all follow the ITRS, for the most part.

That's not to say that you won't see some new technologies pop in, but the ITRS is typically dead-on for most stuff.

Take a look at the National Technology Roadmap for semiconductors:
http://www.i trs.net/NTRS/RdmpMem.nsf/Lookup/RdmpPDF/$file/grdc hal4.pdf

The diagram on page 11.

The total delay *increases* after a certain point because the delays in the wires dominate.