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Intel Shrinks Transistor Size By 30%
pinkUZI writes "Intel will announce that it has crammed 500 million transistors on to a single memory chip, shrinking them in size by 30%. " The tech details are sadly lacking in the article - but I'm sure those will follow. Indeed, the Yahoo piece gives the details that "...has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers."
In related news, Intel stated that this new manufacturing process will help their processors more effectively compete with charcoal on a heat density versus cost basis.
Life is the leading cause of death in America.
I'm waiting for Intel to reduce heat output by 30%. 130 watts for a top end P4 is pretty insane, when a top end Opteron is only 100 watts. I don't care how small it is.
He who laughs last is stuck in a time dilation bubble.
it is not the size of the chip she cares about....it is the number of transistors you have.
Will this be incorporated into the new Unobtainium chip?
~S
Yes, Moore is less - or smaller you could say.
...they've found a way to get rid of the base, collector, or emitter. Unfortunately, these new transistors can only store zeros.
...selling methods for reducing the size of our transistors?
Sheesh, evil *and* a jerk. -- Jade
I work for Intel, and I gotta say--we do this every couple of years, and this wasn't a particularly stunning or unexpected part of our roadmap. If you wanted a more sensationalist headline for a pretty expected bit of news you might try the old "Intel Proves Moore's Law Not Dead Yet"
"The tech details are sadly lacking in the article - but I'm those will follow." :P
At least that is one way to reduce typos by slashdot editors, just start leaving out entire words.
This sounds like a great way to tackle heat and power problems with laptops (and PCs, it's not like modern PCs don't have heating trouble too). I'd lay a bet though, that it'll still run hotter than the P4s, it seems there should be an addenium to Moores law.
Moore predicted his Law would run out in 2012 when 1 billion transistors are fit on a chip. Looks like we're ahead of schedule.
Support the First Amendment. Read at -1
That's some progress!
If you never make mistakes, it's probably because you're not doing anything.
Actually, from the article, the new techniques make for smaller transistors, that use less juice, leak less energy, and work faster. The heat output per-transistor would be much smaller.
Of course, that's not Intels market. Any heat/space saved will be reallocated for new features (extra CPU cores blah blah).
If you want a cool, slow chip, look to VIA or transmeta. If you really want/need a real Intel, look to the Pentium 4 M's.
I don't need no instructions to know how to rock!!!!
This can't be any official sort of press release...nowhere do they measure the size of the transistors by how many it takes to equal the width of a human hair!
You're thinking DRAM, with one transister per bit, but slow (plus it needs refreshing every 60msec or so). Static RAM is mucho faster, with 4 to 8 transistors per bit.
Also, your math is in error. 500M transistors for 70 Mbits works out to 7 transistors per bit. I'm guessing the visible portion of the chip will be 64Mbits and 6 transistors/bit, with most the rest of the transistors allocated as spares. When you make a chip that big, you can boost yield by making spare blocks of memory that during manufacturing can be substituted for bad areas on the chip.
--- Often in error; never in doubt!
They could just say "Clock gating".
What makes a non-technical journalist think "Clockgate" isn't just another White House scandal like Watergate, Flowergate, Whitewatergate, Cattlegate, Travelgate, Filegate, and Zippergate?
With the switches this small, is it safe to say that they are using nanotechnology? I know it's not the cool molecule-sized-killer-robot style nanotech but this seems to fit the description of devices on the scale of a nanometer.
Blaze a trail to the New World
Yeah, but you don't have that nice heat sink that also doubles as a grill grate for those professional chef-type grill marks. Mmmm....
If you never make mistakes, it's probably because you're not doing anything.
"Reduced transistor size by 30%" is an odd way to announce moving from a 90nm to a 65nm process.
Just to help avoid any confusion here, this is not some new clever transistor design or something. It's just another incremental step in process size reduction. It happens every few years. And it's not just Intel -- I know IBM and NEC are doing 65nm right now as well. I suspect TSMC and UMC are also, though I'm not sure (I know UMC had problems in 90nm that they're still fighting with . . )
everything in moderation
I submitted this earlier, but was rejected.
Anyway, here is the offical press release from Intel's website.
In C++, friends can touch each others private parts.
Did they announce it? Or is Miss Cleo now employed by /.?
Like I said, I'm not looking for Intel to supply me a cooler desktop CPU. Just like I don't expect nVidia to come out with a cooler high-end graphics card.
AMD/Intel sell to the high performance crowd. They sell supercharged V8s that require a helluva radiator to keep them cool. They even handle overclocking fairly well, which would be like bolting a couple NOS bottles into the trunk.
VIA/Transmeta make little hybrid 4 cylinder engines that are good enough to push around a compact sedan, and you could probably run them for months with a dead radiator, cooling them with just the heater core. (Ie; the cars interior heater on full blast).
They're different things. I'm not shocked when I find out that VIAs stuff isn't in the same performance league as the P4, and I'm not shocked when I find out that Intels stuff is much hotter than VIAs. Just like I'm not surprised to find out that a supercharged V8 in an old muscle car runs hotter and sucks more gas than the 4-banger in my mitsubishi go-kart.
I don't need no instructions to know how to rock!!!!
The actual Intel press release claims that:
"Intel's leading strained silicon technology, first implemented in its 90nm process technology, is further enhanced in the 65nm technology. The second generation of Intel strained silicon increases transistor performance by 10 to 15 percent without increasing leakage. Conversely, these transistors can cut leakage by four times at constant performance compared to 90nm transistors. As a result, the transistors on Intel's 65nm process have improved performance without significant increase in leakage (greater electrical current leakage results in greater heat generation)."
Tomorrow intel will announce it's achieved tempuratures greater than Sun (fire ball in middle of solar system, not server company).
Intel's product line will include an alternative to the popular "George Foreman Grill". Intel's grill, powered by the PIV processor will grill a "Big George" style hamburger in under 30ns.
Microsoft is expected to make an announcement in coming weeks to annouce it plans to dominate the college cookware industry by selling inferior products at lower costs with Hamburger DRM.
May I ask why, every time they shrink the size of components, they feel a need to put more on the chip? I realize more can be done, but with all the heat/power problems with increased density, why not use the space with chip power you already have? The result would be a cooler, lower power device.
Ad Astra Per Asper
Electrons move at about 3cm/s
The speed of the electron is not the speed of the signal. Think of a cardboard tube full of ping pong balls. Stick a ball in one end, it pushes a ball out the opposite end.
10 amps of current in a 1mm copper wire has a drift velocity of about 0.024cm/s. Thats how fast the electrons in the wire are moving. The thermal velocity, however, would be somewhere around 100,000 meters/sec. Thats how fast the signal is moving. And it's really close to c/3 (a third the speed of light).
The bound electron whipping around a hydrogen atom is moving pretty damned close to the speed of light.
Sometimes, electrons can move Even faster than light!
Optical computing may or may not be the future. In theory, quantum teleportation and that kind of crap could propogate even faster than a bunch of photons.
I don't need no instructions to know how to rock!!!!
Quoted from your original post:
That's 10MB per (square?) 35 nanometers.
From the post I am replying to:
Why "wrong"? From the Yahoo article:
"The Santa Clara, Calif.-based company said Monday it has created a fully functional 70 megabit memory chip with transistor switches measuring just 35 nanometers -- about 30 percent smaller than those found on today's state-of-the-art chips."
Now according to Google, there's 10,000,000 nanometers to a cm. Our chip is 35 nm in size. 10,000,000 divided by 35 is 285,714. So we now know that we can put 285,714, 35nm chips in a 1cm strip.
OK, here are your errors:
Original post: No, it is not 10 MB per square 35 nm, the transistors have 35 nm gate lengths, simply meaning the lenth of poly cut to form the gate is 35 nm, probably at least 3x as wide (can't really say without detailed knowledge of their layout). The overall transistor foot print is going to be MUCH bigger than a 35 nm square, as you haven't even included the source and drain, let alone contacts!
Now on to your second post. You say "Our chip is 35 nm in size." It is obvious you do not work for Intel if you are saying your chip is 35 nm in size. The chip is going to be MASSIVE compared to 35 nm (see above point) once you put 500,000,000 of them on the chip.
My only mistake appears to be in accepting the parent's figure of ~10 MB.
No, you have many mistakes, primarily seeming to be without a clue of semiconductor processing or circuitry.
Any questions?
Yeah, do you feel like uttering any other ignorance while you are here today? I apologize for being rude, but it seems to me like you are trying to put on an air that you know what you are talking about when it is blatantly obvious you are without a clue.
First a story on /. about better lubricated, faster hard drives. Then another story about shinking chips. Is Cmdr Taco trying to give me a complex?
Well, there's spam egg sausage and spam, that's not got much spam in it.
I don't know where the 500M transistors mentioned in the submission come from. I don't find it in both linked articles. I doubt the 64MBit chip (~67E6 bit, marketing makes that 70) uses that much transistors. I think the 64MBit chip is just a demonstration/benchmark for the new process since it's pretty easy to scale a memory chip design to a smaller gate size due to its simplicity.
The problem is production, not cooling. By making the CPU die bigger, you a) decrease the number of dies you can make on a single wafer, which costs a fixed amount to produce, thus making each CPU more expensive; and b) defects that would have only scrapped 1 die out of 300 will now scrap 1 die out of 50, thus making the yields lower, raising the cost per die, making the CPU more expensive to the consumers. Decreasing the die size and increasing the wafer size leads to cheaper chips which is a Good Thing (tm). A nice side affect is that it also allows for higher clocking, which is both good (more ops per second) and bad (current leakage and heat issues). Smaller dies also consume less voltage, which is again a Good Thing (tm). Just have to get current leakage, a Bad Thing (tm), down and the chips would run cooler and consume less power. This new process is better at current leakage, so thats a Good Thing (tm). All in all, making the CPUs smaller is good for Intel and good for the consumer.
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You zee, ferst we take ze reduced size transeestors, and then we use thm in ze new dual core processorz so that even though you zink the procezzor will be smaller - pop - ze prozezzor weeel be bigger and e'more cumbersome and eexpanzive zan before, ja..
Being a computer engineer, I'm quite familiar with Moore's law, it's the reason I continue to find open jobs. Since when did Moore say "doubles every two years"?!? It is "doubles every 18 months" you incompetent journalist!!
</flame>
The Widget
Reuters has more detail on the whole process, and how this will help not only in memory, quoting:
"In a bit of semiconductor showmanship, Bohr said Intel had manufactured a memory chip with more than a half-billion transistors using its new 65-nanometer manufacturing process, which was developed at its site in Hillsboro, Oregon. "
First of all, they were talking about memory modules there. The more transistors you can fit on them, the bigger memory modules will be. With 64bit computing on the horizon it's about time they increased module sizes and made 2G and 4G modules as common as 512M and 1G are today.
Second of all, you don't have to put more stuff on the chip. They just say they now can do it. They also can make smaller chips doing the same thing which means better yield and less cost.
is one thing. Producing it on the Production Line is another.
This is why there are Chemical Engineers, as opposed to Chemists. Or Mechanical Engineers, as opposed to Physicists. You can produce a single one at a cost of $10,000 in the lab, and that is an achievement.
But there's another step, and it very quickly leaves the realm of a controlled environment...
Holy cow!!! I bet someday we'll be able to carry a radio in our shirt pocket.
Carver Mead would say Moore's Law is at an end.
Intel shrinks the number of commands of the x86 architecture by 30% thus resulting in less heat and a global saving of energy of multiple gigawatts per month.
I'm not fully understanding why 70Mbit is being treated like it is so dense. I mean we have 16 chip 512MB DDR nowadays don't we? That's 256Mbit and 256 > 70. Am I just missing some nuance or what?
Thanks.
Ceffecive is a measure of all the capacitance that will be charged/discharged by the switching. It appears in the equation for dynamic (switching) power. Call it what you will, but this is how we determine dynamic power.
I do enjoy being corrected when wrong, but I'm going to have to ask you for some more reliable source than yourself on this one before I can have the joy. Here are some points for you to ponder while you google for something to back up your claim:
Capacitance varies with gate area and inversely with distance between "plates" of the gate (C = k*A / d). Reducing the gate width (space between the plates) actually increases capacitance, and this itself would increase power. But, you're also able to reduce the gate area (though not as much, but in 2-dimensions, so shrinking gates is usually a slight reduction in C). But, if the (dominant) interconnect capacitance (see next point) requires a larger transistor to drive it (which will be the case if voltage is not reduced) then the Area of the gate will increase, and so the capacitance will be right back up to where it was before you shrank the process.
According to Intel, "transitor loads are comprised of >50% interconnect capactiance." Wiring capacitance does not necessarily decrease with process shrinks (and may even increase significantly from cross-capacitance, depending on wire pitch and spacing.)
Most importantly, but probably too complex for this discussion, is the fast that gate capacitance depends strongly on voltage. This relationship is not well understood or investigated other than empirically.
Of course, the simplest way to show you that you're mistaken would be to send you some excerpts from process manuals showing that the capacitances do not drop with simple process shrinks in most cases, but that would probably get me fired.
everything in moderation