Slashdot Mirror

← Back to Stories (view on slashdot.org)

Four Core Processor to Bring Tera Ops

Posted by CowboyNeal on from the whole-lotta-ops dept.

panhandler writes "As reported at CNet and the Austin American Statesman, researchers at UT are working with IBM on a new CPU architecture called TRIPS (Tera-op Reliable Intelligently adaptive Processing System). According to IBM, 'at the heart of the TRIPS architecture is a new concept called 'block-oriented execution"' which will result in a processor capable of executing more than 1 trillion operations per second."

220 comments

  1. Researchers ... by makapuf · · Score: 4, Funny

    at Unreal Tournament ? Why, some have cool jobs.

  2. one trillion ops/second by Adolf+Hitroll · · Score: 3, Funny

    this way you, yankees, can count every dollar of your actual external debt in a little more than a second !

    --
    Smile, don't click...
    1. Re:one trillion ops/second by Anonymous Coward · · Score: 0, Funny

      or in a little less than a trillionth of a second, count every one of Iraq's weapons of mass destruction.

    2. Re:one trillion ops/second by Anonymous Coward · · Score: 0

      http://www.wallstreetview.com/GDPRankings.html

  3. Great.... by innosent · · Score: 4, Insightful

    Great... Just what we need, processors that can perform an instruction, then wait 40000 cycles for the next instruction to be read from memory. I wish we could see some memory improvements to go along with these.

    Seriously, though, this will help break all the clustering records, provided we can come up with faster interconnects by then.

    --
    --That's the point of being root, you can do anything you want, even if it's stupid.
    1. Re:Great.... by Anonymous Coward · · Score: 0

      HPC already has trouble with this on modern machines. That's why most high performance code computes data in blocks so the data can remain on the CPU cache.

    2. Re:Great.... by n3rd · · Score: 3, Informative

      Great... Just what we need, processors that can perform an instruction, then wait 40000 cycles for the next instruction to be read from memory. I wish we could see some memory improvements to go along with these.

      Sun is working on something along those lines, check it out

    3. Re:Great.... by innosent · · Score: 4, Interesting

      That's throughput they're working on, which is great, but not the problem. Latency is the problem, not throughput. Try having large programs with lots of branches and/or syscalls: If the code is large enough, you'll spend more time bringing pages in from memory than actually executing your code, especially since you can forget about pipelining benefits...

      Personally, I wish a company would throw out every idea from current memory, put a GB of cache on a chip, and get memory access times down to about 3 picoseconds. But memory doesn't have the marketing appeal that processors do, so we're screwed.

      --
      --That's the point of being root, you can do anything you want, even if it's stupid.
    4. Re:Great.... by asavage · · Score: 2, Interesting
      Personally, I wish a company would throw out every idea from current memory, put a GB of cache on a chip, and get memory access times down to about 3 picoseconds. But memory doesn't have the marketing appeal that processors do, so we're screwed.

      The problem is the larger the cache size, the slower the access time. It is a trade off.

    5. Re:Great.... by AlecC · · Score: 2, Insightful

      True, for general purpose computing, which is probably what most /.ers probably do. But this sort of massive processing power is really only needed for the simulation people, who do large amounts of contoguous number cruncong, such as matrix multiplies. That sort of thing will be speeded up enormously by this sort of architecture.

      As a concept, this is hardly new. There have been all sorts of different parallel processing architectures over the years - SIMD, MIMD, strings, arrays, etc. Each has performed well on one particular class of problem, but generally crashed out as soon as you move away from its sweet spot. For example, changing gear from array mode (lots of big matrix ops) to linear mode (making decisions on the results) tends to lose most of the time gained by the array processor. OTOH, clusters of general purpose processors tend to wast time on memory or object contention unless they are working on highly decomposable problems.

      Maybe this architecture is a better compromise that its many predecessors. (It ought to be - IBM built enough of them). But don't expect to use them youself, unless you work for an advanced engineering company, a weather forecaster or the DoD.

      --
      Consciousness is an illusion caused by an excess of self consciousness.
    6. Re:Great.... by kamakot · · Score: 1

      I'd think it'd still be faster than the current RAM setups.

    7. Re:Great.... by scovetta · · Score: 1

      Or some hard drive speed increases. I think normal every-day IDE drives have gone from 10-11 ms down to maybe 8-9 in the past 10 years. Wow, way to make Murphy proud, fellas.
      <plug>Western Digital hard drives are the best.</plug>

      --
      Wer mit Ungeheuern kämpft, mag zusehn, dass er nicht dabei zum Ungeheuer wird. --Nietzsche
    8. Re:Great.... by DickBreath · · Score: 1

      Wouldn't wide enough memory words fix this? Instead of puny 128 bit memory, go to bigger words, like 2048 bit words. Now in each memory access, you're reading in enough 64-bit instructions to keep the processor busy.

      The width of the new 2500-pin DIMM's could have an adverse effect on case design however.

      --

      I'll see your senator, and I'll raise you two judges.
    9. Re:Great.... by Anonymous Coward · · Score: 0

      From the Project website:

      "As transistor densities increase and clock times shrink, processors and systems are rapidly becoming bound by wire and memory latencies. On-chip communication latencies will prevent conventional, monolithic processing cores from executing at full speed and efficiency. It is no longer possible to increase performance simply by building deeper processor pipelines. Furthermore, existing microprocessor architectures have become increasingly specialized, achieving near "peak" performance on only a small class of applications. The TRIPS design provides substantial performance improvements by both providing large pools of execution resources and exposing communication latencies throughout the components of the system and delivering system level configurability to applications and runtime systems. In this way, the system can adjust the hardware to meet the varying demands of each application."

    10. Re:Great.... by Wesley+Felter · · Score: 1

      The problem is the larger the cache size, the slower the access time. It is a trade off.

      The TRIPS team has solved that with NUCA.

    11. Re:Great.... by drinkypoo · · Score: 2, Interesting
      Maybe someone should just get SRAM working at higher speeds and densities without making it bloody expensive as it has been, thus eliminating the need to do refreshes, and enabling asynchronous reads from memory at synchronous speeds but without the need to be synchronous.

      Or maybe IBM's MRAM will do this for us.

      --
      "You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
    12. Re:Great.... by Slack3r78 · · Score: 1
      Western Digital hard drives are the best.
      Assuming they aren't DOA when you get them ;) Note: I'm not just trolling. DOA drives are a serious problem with WD HDs.
    13. Re:Great.... by jrockway · · Score: 1

      > The width of the new 2500-pin DIMM's could have an adverse effect on case design however.

      That's not necessarily true. There's no reason that I know of that requires RAM to be a long stick. Make it look like a CPU and you can have a square-shaped socket that has more pins/square inch.

      --
      My other car is first.
    14. Re:Great.... by pmz · · Score: 1

      Latency is the problem, not throughput.

      And, this is also exactly what Sun's program is aiming for. Highly-threaded processors can use latency to their advantage, by scheduling additional threads during the waiting period.

      --
      Healthcare article at Kuro5hin
    15. Re:Great.... by akuma(x86) · · Score: 1

      That's what prefetchers are for. If the memory pattern is predictable (many are), then you don't have to wait, the hardware will prefetch the data for you and have it ready to go when the core needs it.

    16. Re:Great.... by Anonymous Coward · · Score: 0

      blue gene
      "The Blue Gene/L design will run these applications much faster because the machine will be populated with data-chip cells optimized for data access. Each chip includes two processors: one for computing and one for communicating, and its own on-board memory"

    17. Re:Great.... by stevesliva · · Score: 1

      First of all, unless the memory is embedded on chip, you've already lost-- slow bus speeds, limited pins. Second of all, once you have your on-chip cache, a single wordline might be very fast... if it's a kilobyte wide, then you can read 1024 bits every cycle no problem... but no cache has only a single wordline (unless it's a register), and no bitline has a single bit. So now you have a word address to decode, and a bitline with lots of bits on it and a sense amp at the end... and a bit address/mux if you want it. How does this affect latency? Well, that depends on the size of the memory not the speed of the memory cell. The bigger you make it, the longer the access. A single storage element is plenty fast... if the access isn't random, interleave intelligently and there's no problem. It's a size problem: you can't have every book in the library of congress at arm's length (physically). You've got your phone book, dictionary, and the last few books you read. The rest take a bit longer to obtain.

      --
      Who do you get to be an expert to tell you something's not obvious? The least insightful person you can find? -J Roberts
    18. Re:Great.... by Anonymous Coward · · Score: 0

      I disagree on the waiting for memory. While this is true for simpler applications actual floating point mathematics with multiple matrices doesn't require that much memory but would significantly benefit from parallelizing.

      Maybe with a tera-op chip we may finally get multiplayer Grand Theft Auto.. ;D

    19. Re:Great.... by drinkypoo · · Score: 1

      While there is something to what you say, the G5 has a 1GHz bus and there is no reason to believe that this is the upper limit of bus technology, so clearly it is possible to do much better than we have been with our memory bus. Ostensibly, the best plan would be to have a lot of cache, a lot of main memory on-chip, and then a lot more memory off chip. Put more explicitly, perhaps it is time for computer architecture to more closely mimic the way it is used. While computer technology has been moving away from that ever since it has first been used, to give us software-reconfigurable devices which can do anything, this results in most tasks being much slower than they would be with purpose-designed hardware. This is not a surprise by any means, but perhaps it's time for more work put into reconfigurable hardware. The most recent commecial advances in this area are still software-based; transmeta's processors for example.

      --
      "You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
    20. Re:Great.... by SiJockey · · Score: 1

      We have three approaches to memory in TRIPS. One is by using a large (>1000 instruction) issue window, we tolerate lots of memory latency behind other work. Second, we have a low-latency cache design called NUCA (non-uniform cache array). Third, we are incorporating efficient recovery from data value speculation (take a cache miss? Guess the value!) Thanks for pointing out this important issue!

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
    21. Re:Great.... by SiJockey · · Score: 1

      Actually, we are working a fair amount on latency of single threads. We deal with branches by predicating (removing) large numbers of them, so that ideally there are a hundred instructions or so between each branch (since when you predicate, both paths are fetched, you improve branch prediction at the expense of fetching more useless instructions). Our results show that this is a *big* win. And yes, I'd love a 3ps memory too!

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
    22. Re:Great.... by innosent · · Score: 1

      Well, first of all, thanks for your work, it is sorely needed. Having said that, though, I don't think TRIPS quite covers what I had in mind. I am more concerned with areas where you have to jump to an unpredictable location every 5 instructions or so, such as processor simulation. My most recent work in this area was on a VAX simulator, where benchmark differences between my workstation (~2700 VAX MIPS [scaled to VAX 11/780]), and the simulated VAX on my workstation (average 5 instructions per simulated instruction, 10.5 VAX MIPS!) are huge due to the difference between code that fits in cache and doesn't break the pipeline, and code that breaks the pipeline before it can be filled, and needs to jump to a new memory location after every 2.5 (average) instructions. Due to latency, something that should simulate at about 10-15% (worst case) of processor speed, only can simulate at about 0.4%. I can't even simulate the performance of a machine built 15 years ago, and that's sad. Marketing departments keep telling us that machines are faster, I'd just like to see them be right someday. Our systems aren't much faster, even though our processors are 2 or 3 orders of magnitude faster.

      Of course, no one is going to fix this until they think they should, which will probably never happen, since I'm sure most of the chipmakers are happy with their profit margins now. In other words, if you're going to do something that needs to be done as fast as possible, it better have a predictable path and fit in cache, or you might as well use a cluster of 486s.

      --
      --That's the point of being root, you can do anything you want, even if it's stupid.
    23. Re:Great.... by SiJockey · · Score: 1

      Do you mean processor emulation, where you basically have a bit switch statement based on which instruction you are emulating, jumping through an indirect branch to the execution semantics for each instruction? If so, that's an interesting problem. I think there's parallelism there, but I'll wait until I'm sure that's what were discussing before spending the cycles thinking!

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
    24. Re:Great.... by innosent · · Score: 1

      Yes, processor emulation, or in my case, architecture emulation, since it must also simulate VAX storage and networking hardware for compatibility reasons. Switch statements are ok, but for VAX, I've found that you have to get a little dirty and do table lookups for the opcode functions (one table indexed by opcode with the transfer addresses for the jump into op simulation), since there are about 273 instructions to simulate. It's quite simple, really, but I noticed the bottleneck when I changed from the switch statement to the O(1) table lookup implementation. I had expected to lose an average of 100 instructions per loop, which would be a huge speedup. I did lose the 100 average instructions, but only got about a 5% speedup, since the processor was just waiting to pull everything from memory.

      Of course, this wouldn't be a problem if it fit into cache, but it takes quite a bit of code to simulate 273 opcodes, the interrupts, and hardware.

      --
      --That's the point of being root, you can do anything you want, even if it's stupid.
    25. Re:Great.... by innosent · · Score: 1

      Sorry, I forgot... There is parallelism at the process level, of course, since you could spread out the load (similar to Mosix), but then again, why would you use $2000+ new hardware to simulate something slower than what you can find on ebay for $50. We have several VAXes, all about 10-15 years old, and I can't even beat the slowest ones (about 15 VAX MIPS [VUPs]) with the best machines available.

      Of course, I/O is quite a bit faster, but the simulated CPU is so much slower that it doesn't make a difference.

      --
      --That's the point of being root, you can do anything you want, even if it's stupid.
    26. Re:Great.... by DickBreath · · Score: 1

      Well, I was trying to be somewhat of a smart ass, and somewhat serious. (Hence my nick.)

      While wide memory words are a real possibility to fix memory bandwidth in keeping processors appetites satisfied, nobody would seriously consider a 2500 pin DIMM.

      Other possibilities suggest themselves. Your square 2500 pin arrangement might be one. A very high speed serial interface might be another.

      Yet another possibility is that socketed memory might just go away completely. No really. As computers push the sub-$200 barrier, I forsee a whole new type of non-expandable computer emerging. No expanability. No slots. Just a solid plastic brick, with another brick for the power supply. The computer brick has all the connectors. It's $89. When it ain't fast enough anymore, or doesn't have enough memory anymore, then just chuck it and buy a new one. Sort of like calculators.

      I see no fundamental reason why today's $200 computers have to be priced so outrageously high! It's not like they are made of gold. Within a few years, every processor architecture, no matter how expensive, has it's chips selling for $10 in the back of electronics magazines.

      We are already at a point where processor power -- finally! -- has got high enough to satisfy most common types of software, even using inefficient (i.e. productive) development methods. So two trends will emerge. A fork if you will. One line of computers will maintain the same prices but get ever more powerful. Another line of computers will maintain the same power and get ever cheaper.

      Back in the 70's, when pocket calculators were $400 for a four-function, 8-digit unit with no square root, nobody would have believed the day in the 80's when 4-banger calculators would be disposable. I see no fundamental reason that the same won't be true for PDA's and even personal computers. After all, it's not like they are made of rare earth, like Gold or Platinum -- i.e. made of something intrinsically expensive. And it is not like they are labor intensive to assemble. Especiall PDA's, or the "plastic brick" type computers I described.

      --

      I'll see your senator, and I'll raise you two judges.
    27. Re:Great.... by Tower · · Score: 1

      The other very signifact tradeoff is, of course, that putting that much cache on a chip causes yields to drop quite dramatically, can create large timing and power quality issues... all of which lead to a design that ships late and costs more than anyone wants to pay.

      --
      "It's tough to be bilingual when you get hit in the head."
  4. And Windows 2005... by Anonymous Coward · · Score: 4, Funny

    Will still take five minutes to boot into a login prompt. Some things never change.

    1. Re:And Windows 2005... by Anonymous Coward · · Score: 0

      Like Windows booting to a login prompt?

    2. Re:And Windows 2005... by Anonymous Coward · · Score: 0

      And Debian Tyron (Version 3.2, after sarge version 3.1) will still be using Kernel 2.2.28, some things never change.

    3. Re:And Windows 2005... by The+Ancients · · Score: 1

      And you would need a login prompt why? By 2005 Microsoft will have everyone's user/pass and will log in for you, to reduce security risk...

      --
      The Mothership
    4. Re:And Windows 2005... by slittle · · Score: 2, Informative

      ??

      Things change plenty. Windows' boot times have been improving in recent years, esp. compared to the Win9x days.

      I think you meant to make a crack about Doom III or something...

      --
      Opportunity knocks. Karma hunts you down.
    5. Re:And Windows 2005... by julesh · · Score: 3, Informative

      Come on, funny as the line might be, timing from power-on to having a working desktop, my systems come in like this:

      Windows 2000 - 45 seconds
      Windows 98 - 1 minute
      Linux + KDE 2 - 1 minute 10 seconds

      (Admittedly linux + console is about 20 seconds, but that's not really a fair comparison - Windows 98 'text mode only', i.e. DOS, is only about 2 seconds).

      Also, boot up time is largely IO bound. Improving your processor speed will make comparatively little difference (I think doubling speed might shave 10% off these figures, possibly more for the Linux one because the KDE issue is dynamic linking related which is a CPU problem).

    6. Re:And Windows 2005... by Anonymous Coward · · Score: 0

      Yeah right. Win 3.11 booted in 5 seconds on my 60MHz Pentium....

    7. Re:And Windows 2005... by Anonymous Coward · · Score: 0

      A windows out of the box maybe takes 45 seconds. The more you install programs the slower it gets. It took me about 4 minutes (!) before the mouse pointer was actually allowed to click on something (yes, the desktop appeared sooner).

      All this on a 600MHz pentium.

      After blaster I had to format everything and reinstall w98.

    8. Re:And Windows 2005... by cbiltcliffe · · Score: 0

      Linux + KDE 2 - 1 minute 10 seconds

      (Admittedly linux + console is about 20 seconds,

      If it takes 50 seconds to bring up KDE on your Linux machine, something is seriously wrong with your setup. I've got a Celeron 366 256MB machine that boots into KDE faster than that. What are you running this on, a 486?

      --
      "City hall" in German is "Rathaus" Kinda explains a few things......
    9. Re:And Windows 2005... by falzer · · Score: 1

      Windows 2.0 started in about 2 seconds on my XT.

    10. Re:And Windows 2005... by Anonymous Coward · · Score: 0

      Not only that, but who really cares? Like you have to reboot a Linux machine half as much as a Win2K machine...

      Riiiight.

    11. Re:And Windows 2005... by pmz · · Score: 1

      Windows 2000 - 45 seconds

      So what? Solaris 9 booting on a six year old workstation goes this fast after optimizing the rc directories. Also, most people wait for the hourglass cursor to go away in Win2K after logging in, anyway (I don't trust Windows enough to attempt work while it is still busy--that's just asking for trouble).

      --
      Healthcare article at Kuro5hin
    12. Re:And Windows 2005... by julesh · · Score: 1

      Windows 2000 - 45 seconds

      So what? Solaris 9 booting on a six year old workstation goes this fast after optimizing the rc directories.

      The original AC I was replying to suggested that 5 minutes was common. I was pointing out the error of magnitude. Also, the fact is that Linux with a modern desktop environment isn't much better.

      I wasn't saying 'wow, isn't windows fast'. I was saying 'look, there isn't a lot of difference between windows and a system of the kind that I guess you prefer'.

      Also, the timings here are on a Pentium 2 233Mhz processor with a fairly poor 5,400 RPM IDE disk. The 6 year old Sun workstation you talk about probably has a comparable processor (if not actually a faster one) with a reasonably high quality SCSI disk. _That_ isn't a fair comparison.

      Also, most people wait for the hourglass cursor to go away in Win2K after logging in, anyway (I don't trust Windows enough to attempt work while it is still busy--that's just asking for trouble).

      Well, I don't. And you know what - I've never had an issue with it. Besides, the hourglass only stays for another 5 seconds.

    13. Re:And Windows 2005... by jo42 · · Score: 1

      > Windows' boot times have been improving in recent years

      B*llsh*t!!

  5. Re:Wow... by Fooker · · Score: 0

    wow. heh, that would be totally Boss. think of all that could be done, why someone with that could totally be the king of all the distrobuted computing programs. lol

  6. Better link by Textbook+Error · · Score: 5, Informative

    A somewhat more informative link for more info. Would it really kill submitters to put a link to the actual project in their submission...

    --

    Nae bother
    1. Re:Better link by tarawa · · Score: 1

      Of coarse it would ... this is Slashdot after all. ;)

  7. Thank God by (outer-limits) · · Score: 3, Insightful

    EPIC is clearly dead in the water. Intel didn't learn from the 432.

    --

    Microsoft - Where would you like to go today, Maybe Jail?

    1. Re:Thank God by pmz · · Score: 1

      EPIC is clearly dead in the water.

      Only in the context of general-purpose processors. VLIW CPUs are common in signal processing and video cards. Perhaps the Itanic can become a $5,000 behemoth DSP chip for the next generation of 260-watt graphics cards. Perhaps they can put those rediculous SPEC scores to some use?

      --
      Healthcare article at Kuro5hin
  8. See The Project Yourself by robbyjo · · Score: 3, Informative

    Here

    --

    --
    Error 500: Internal sig error
    1. Re:See The Project Yourself by Anonymous Coward · · Score: 0

      please mod parent up.

  9. SCO's response: by 10Ghz · · Score: 5, Funny

    "This is yet another breach of our IP! Our fine researcher came up with this technology over 10 years ago, we have just ket it hidden for all this time. Unfortunately we wrote the patent-applications with invisible ninja-ink and they are being kept in a vault in our Fortress of Doom (tm), so we can't show them to anyone.

    We expect IBM to pay us 5 billion dollars plus 4 x $699 for each CPU sold"

    --
    Lesbian Nazi Hookers Abducted by UFOs and Forced Into Weight Loss Programs - -all next week on Town Talk.
  10. Fabrication by Anonymous Coward · · Score: 4, Insightful

    Does anyone remember the Pentium Pro? It was an extremely expensive processor. This was because of its strange system of connecting the CPU core with a massive amount of cache ram; production yields were very low, so fabrication costs were very high.

    Imagine how high the failure rate would be with fabricating a CPU with four cores... I don't see how it would be practical unless it was with an extremely-high yield design such as the StrongARM.

    1. Re:Fabrication by Nazmun · · Score: 2, Interesting

      what if they could fabricate each core separately and then somehow connect the cpu's. Shouldn't be too hard to do in the factory. It wouldn't be as fast as a single core cpu's internal bus but it would be a heck of a lot better then mult cpu's in standard mobos now (like xeon's etc.).

      --
      Hmmm... Pie...
    2. Re:Fabrication by Anonymous Coward · · Score: 0

      That's much the same as what happened with the Pentum Pro. The problem was they couldn't test what was working until after the separate bits had already been joined together.

      How are they going to plug in and test an incomplete CPU core designed to work exclusively in tandom? They've got alot of work to do.

    3. Re:Fabrication by ottawanker · · Score: 2, Interesting

      Imagine how high the failure rate would be with fabricating a CPU with four cores... I don't see how it would be practical unless it was with an extremely-high yield design such as the StrongARM.

      Naw, that doesn't seem like too big a problem. All they have to do is check to see how many cores are working, and then sell the chips like that. Something like this (assuming you pay a premium for more cores, relative to the lower yields):

      $500 for 1 core
      $1200 for 2 cores
      $1800 for 3 cores
      $2500 for 4 cores

    4. Re:Fabrication by Zork+the+Almighty · · Score: 0

      This is actually a great idea.

      --

      In Soviet America the banks rob you!
    5. Re:Fabrication by Phishpin · · Score: 1, Insightful

      Marketing a chip that has a product defect doesn't sound so great to me, even if the chip performs flawlessly with a broken core or two.

      IBM: "Well, all our chips are made with 4 cores, but some of them get made broken, so we sell those for less as if they were only made with the number of cores that work"

      Customer: "I wonder what Sun and Intel are up to these days."

      --
      -phish
    6. Re:Fabrication by Urkki · · Score: 1

      But it wouldn't be marketed like that of course. Just like early 486SX wasn't marketed as 486DX with a broken/disabled FPU.

    7. Re:Fabrication by Anonymous Coward · · Score: 0

      Pentium 4s can be busted Xeons,
      Celerons can be busted Pentium 4s,
      it doesn't stop people from buying them

    8. Re:Fabrication by Jeff+DeMaagd · · Score: 1

      The multi die module wasn't a "strange system" it was simply an expensive way to do it. Both the CPU and cache were fabbed separately and individually bonded into the package and into each other. As I remember, others have done similar things before, but I think it was the largest scale use of its kind. Now a more complex CPU with a big of a cache is more routinely put on the same die, and I expect that this project will as well.

    9. Re:Fabrication by G-funk · · Score: 1

      Erm, what do you think the difference is between a different clock speeds of the same cpu? They print them up, the ones with less errors get a higher clock speed.

      --
      Send lawyers, guns, and money!
    10. Re:Fabrication by Wesley+Felter · · Score: 1

      Check out the Power4 HPC sometime. Or the Celeron.

    11. Re:Fabrication by geekee · · Score: 1

      The Pentium-pro was a 2 chip solution in an expensive package. That combined with state-of-he-art technology at the time made it very expensive. The article doesn't mention the device count or die size for this chip, so your yield analysis is pure speculation without any real data.

      --
      Vote for Pedro
  11. Only 32 Billion Now by Nazmun · · Score: 4, Informative

    The four cores add up to only 32 billion operations right now according to the CNet article. They project that they won't reach 1 trillion until 2010.

    --
    Hmmm... Pie...
    1. Re:Only 32 Billion Now by davstok · · Score: 1

      So I can only replace ten Pentium 3000s with this one chip, such a pity...

  12. Oooh, can't wait for the G6! by Capt'n+Hector · · Score: 4, Insightful
    But of course, these processors will require entire software rewrites.

    But this reminds me of a growing trend, and that is that as soon as large infrastructures are finally completed (be it the transition to OS X or 802.11b) the technology becomes obsolete. However, the entire infrastructure must be replaced. I don't care how many gazillion flops this or any other processor can pull. They need to easily scale so that the entire infrastructure does not need replacing.

    --
    Quid festinatio swallonis est aetherfuga inonusti?
    Africus aut Europaeus?
    1. Re:Oooh, can't wait for the G6! by delirium+of+disorder · · Score: 1

      If we wrote portable code, we could just recompile (to an extent).

      --
      ------ Take away the right to say fuck and you take away the right to say fuck the government.
    2. Re:Oooh, can't wait for the G6! by watzinaneihm · · Score: 1

      With IBM behind it it shouldnt matter. IBM has the grandplan of making Linux the OS which will run across all its server lines. Look at this article for example.
      Anyway competition is always a good thing, and you really don't have to move the infrastructure unless you have to. If Intel chips remain good enough, stick on to that, you probably will still be able to find support for that.

      --
      .ACMD setaloiv siht gnidaeR
    3. Re:Oooh, can't wait for the G6! by traskjd · · Score: 1

      You don't think that some IT people are realising that building a system that doesn't require a new infrastructure is a dumb idea? I mean look how many are currently unemployeed.

      It would make a lot of sense for those developing such systems.

      - traskjd

      --
      My blog [.net, rants, general IT]
    4. Re:Oooh, can't wait for the G6! by ElGanzoLoco · · Score: 1

      But this reminds me of a growing trend, and that is that as soon as large infrastructures are finally completed (be it the transition to OS X or 802.11b) the technology becomes obsolete.

      Obviously, you are new to the computer industry, aren't you?

      --
      Hello! I'm a disaster waiting to happen!
    5. Re:Oooh, can't wait for the G6! by Anonymous Coward · · Score: 0

      How interesting. Did they mention that these CPUs break PowerPC compatibility ?

      Besides, sincerely, do you really believe this will become mainstream in less than a couple of years ? Look how long did the previous PowerPC CPUs last since the switch to it in Apple computer line. How long was the 64bit world touted/promised by Apple/Motorola before IBM stepped in with the PPC970 ?

      OTOH, when you're selling these beasts in the mainframe market, clients are not afraid to rebuild the whole system if it can enable the real machine power. Someone pointed in the last IBM compiler topic a tool to optimise binaries after the compilation stage, depending on the architecture the binaries are targeted to. If IBM make such tools, they necessary believe you have rebuild the program you intend to use even if you change the platform revision it'll run on (not only major architecture change).

      Hell, even gcc provides optimisations depending on the architecture level.

    6. Re:Oooh, can't wait for the G6! by Capt'n+Hector · · Score: 1
      No actually. It has only been in recent times that we have finally built large infrastructures based on rapidly progressing technology. I'm not only talking about computers, I'm talking about everything from roadways (which need to be repaved all the time anyway) to electricity.

      Backwards compatability is nice, but let's not forget forwards compatability as well.

      --
      Quid festinatio swallonis est aetherfuga inonusti?
      Africus aut Europaeus?
  13. We'll need a lot better compilers by kramer2718 · · Score: 3, Insightful

    If each chip is basically four processors each of which can execute 16 operations simultaneously, it will be difficult for compilers to find 64 independent instructions to execute each cycle.

    I guess one possibilty could be to execute instructions from four different processes simultaneously, thus reducing the probability that the instuctions will interfere.

    --
    http://yetanotherpoliticalrant.blogspot.com
    1. Re:We'll need a lot better compilers by boopus · · Score: 4, Interesting

      Exactly. The IA64/itanic/itanium instruction set provides for executing multiple instructions "simultaneously" (aka: pipelined with no interference) but the intel guy I heard from said it so far doesn't provide anything close to the improvements they hoped the feature might. Scaling it up to 64 instructions per clock is only going to help tasks which IBM supercomputers have already lost to beowolf clusters.

    2. Re:We'll need a lot better compilers by Alain+Williams · · Score: 2, Insightful
      • it will be difficult for compilers to find 64
      • independent instructions to execute each cycle


      The problem is that the word independent is the wrong one.


      It depends on what sort of work you choose to do on this sort of beast, finite element work (simulations, etc) involves the same operation on lots of values over and over. This is how Cray made his money years ago.


      This is not a desktop machine for you to do office automation on, quake maybe, but not word smithing.

    3. Re:We'll need a lot better compilers by Mostly+a+lurker · · Score: 1

      For many applications, it seems unlikely to me that compilers can do the job without help from programmers. Often, the programmer can identify sections of code that do not interfere with each other when no reasonable compiler could know this. I suspect we need new methods of software design that highlight these situations combined with compiler features that make it easy for the programmer to identify them. Specifics? Hey, on this one I am in marketing: the implementation is the job of the engineers!

    4. Re:We'll need a lot better compilers by NovaX · · Score: 1

      Developers write in high-level languages and the compiler converts it into assembly. The dependent instructions (such as loads required to do an add), is where the problems with parallelism are. This is a significant aspect that compilers do deal with: trying to reorder instructions to reduce branches and bubbles.

      Above instruction-level parallelism there's thread-level. Processors utilizing SMT or CMP can execute multiple threads. Here developers must seperate their code correctly so that their application can do multiple things simultaniously. A compiler can't do it, because as you suspected it won't know what's dependent both in data and in order of execution.

      So, while you have a good idea, there are a lot of books out there covering the topic.

      --

      "Open Source?" - Press any key to continue
    5. Re:We'll need a lot better compilers by leek · · Score: 1
      A compiler can't do it, because as you suspected it won't know what's dependent both in data and in order of execution.

      Actually, some compilers can do it. They can break apart a user's program into multiple threads which execute in parallel, without the user giving any source code directives or hints.

      Automatic parallelization, array disambiguation, loop dependence analysis, etc. are not new. Despite apparent dependencies in code between instructions, high-level optimizers can often do dependence analysis which can detect higher-level patterns which are independent and thus can be executed in parallel, even though the code generator's individual instructions seem purely sequential.

      If the compiler cannot be sure about data dependencies or control dependencies, then there are still sometimes devices to help it optimize in spite of these possible dependencies, e.g. speculative and advanced loads on Itanium.

    6. Re:We'll need a lot better compilers by SiJockey · · Score: 1

      What we're really after is building large single cores (16 ops in parallel, eventually 64 or 128). The compiler doesn't have to find them, just schedule the code and let the out-of-order window take care of it. You can use the multiple processors if you have an application that parallelizes nicely. I'd rather have 10 100-op cores than 1000 1-op cores!

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
  14. Expensive by White+Rabbitt · · Score: 1, Insightful
    It seems cheaper to me to simply make larger clusters of computers with more processors than to redesign processors. For example, why don't IBM and UT team up to design an 8-processor Itanium motherboard or something?

    First, they don't spend money reinventing the wheel. Second, hardware production failure rates are reduced because if an eighth of all cores fail, you don't average zero production. Third, most of the code is already written for multithreading with multiple processors. It would probably be cheaper to build larger facilities than to design mulitprocessor processors.

    1. Re:Expensive by mkramer · · Score: 1

      What's maybe not clear from the information in these links is that this chip is not designed for general purpose computing. It's part of DARPA's Polymorphus Computing Architecture plan, which is to make a processor than can be blazingly fast on threaded code AND streaming code, and can handle switching between both with speed.

      These processors will be used in harsh conditions (space, high-G sensor systems, etc.), and require low power and small packaging. The primary selector model for the competition is SWEPT (Size, Weight, Efficiency, Power, and Time).

      The UT TRIPS chip is one of 8 architectures competing in the PCA bid. I'm on a cometing team (Raytheon, supporting USC's MONARCH), so I'm highly biased, but when you get down to it, TRIPS is really the least revolutionary of the designs.

    2. Re:Expensive by SiJockey · · Score: 1

      Two clarifications ... one of the chip's modes IS designed for fast single-threaded, general purpose computing. Second, I'm biased too, but I think the ISA and the execution model are pretty revolutionary. :-)

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
    3. Re:Expensive by mkramer · · Score: 1

      I guess this is the point where I get to put my foot in my mouth. I think I'll be hiding my nametag at the forum next week.

      Out of curiosity, what's the resource utilization like in single-threaded mode? Is it possible to keep all/most the ALUs busy?

      I'm going to go hide in embarassment now...

    4. Re:Expensive by SiJockey · · Score: 1

      The resource utilization (on a 16-wide ALU core) is low in single-threaded mode ... ranging from about 1 to 10 ops per cycle (averaging around 4). That's the same average as the Alpha 21264, which has 4 units and averages about 1 on the same benchmarks. When we run data-parallel threads (FFTs, FITs, DCTs, etc.) we show higher utilization, of course. My hope is to raise the utilization with more tuning for the low-ILP benchmarks, but in the end, I care about performance since the transistors are cheap, so long as those transistors can also be used to exploit parallelism in other workloads when it exists. Thanks for an excellent question.

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
  15. Just a warning by Kizzle · · Score: 5, Funny

    If anyone in any way shape or form mentions the word beowulf, expect a swift kick in the nuts by your's truly.

    That is all

    --
    Hacker Media
    1. Re:Just a warning by iapetus · · Score: 3, Funny

      But just imagine a BeowAAAAAAAAARRRRGGHH!

      Ooh, now I can sing soprano again...

      --
      ++ Say to Elrond "Hello.".
      Elrond says "No.". Elrond gives you some lunch.
    2. Re:Just a warning by mors · · Score: 0

      Have you started kicking yourself yet, after all you did say the forbidden word.

    3. Re:Just a warning by cgibbard · · Score: 1

      Can you imagine a mosix cluster of these?

  16. It doesn't matter... by Anonymous Coward · · Score: 0

    It'll still take forever for Open Office to load.

    1. Re:It doesn't matter... by julesh · · Score: 1

      Huh? Open Office loads in about 5 seconds on my (relatively feeble) Win98 machine.

      What are you on?

    2. Re:It doesn't matter... by cbiltcliffe · · Score: 0

      It'll still take forever for Open Office to load.

      Try the new version, dude. 1.1 loads in less than half the time of 1.0.3. And it exports to PDF directly, too.

      --
      "City hall" in German is "Rathaus" Kinda explains a few things......
  17. Let me guess. by JanusFury · · Score: 4, Funny
    capable of executing more than 1 trillion operations per second."
    Let me guess...
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    ...
    --
    using namespace slashdot;
    troll::post();
    1. Re:Let me guess. by Anonymous Coward · · Score: 0

      No, that would require main memory bandwidth of nearly 1TB/s if the NOP is 1 byte. A simple jump to itself would be much faster.

    2. Re:Let me guess. by pe1rxq · · Score: 1

      Unfortunatly a typicall processor would do only have the amount of jmp instructions compared to a nop.... Some prediction and pipeline magic might compensate however.

      Jeroen

      --
      Secure messaging: http://quickmsg.vreeken.net/
  18. It won't work... by heironymouscoward · · Score: 1, Offtopic

    Sure, the machine will work.

    But it's going to take more than a faster CPU to kick-start the IT industry in the West.

    Right now, IT is a sunset industry, serving a market that is itself rapidly becoming extinct as entire business chains get automated in foreign countries. Within five years the famous Western IT industry will become a thin service layer reselling products (hard and soft) developed and produced elsewhere.

    Building yet faster CPUs does not alter this. There is no way new generations of faster hardware can pull the industry out of its situation.

    What can?

    Possibly two things. First, to realise that the market for IT is rapidly globalising, and that western technology will have to sell to China and India if it is to sell at all.

    Secondly, to realise that this means extraordinary cost efficiency, based on a true understanding of the nature of today's technology, rather than an attempt to shoehorn today's reality into yesterday's way of working. Technology - such as operating systems that was a luxury item only ten years ago is now not only a commodity, it is basically free. The same applies to so many technologies that a business which does not take advantage of this simply will not be able to compete.

    Guess what I'm saying is: switch to Linux and OSS before you croak, folks. It just seems to make so much sense.

    --
    Ceci n'est pas une signature
    1. Re:It won't work... by Anonymous Coward · · Score: 0

      How, exactly, did you reach that conclusion?

      Switching to open source will only shrink the market even more, there is NO value at all, it certainly will not help.

      Some people say that IP rights is something unique to this industry, that utterly untrue. More or less all major businesses have substancial IP rights. Patents, copyright, trademarks. What would McDonalds or Coca-cola be without their IP rights? Nothing!

      Car-manufacturers don't give out blueprints to their cars, medicine-manufacturers don't give out the ingridients.

      It's time for this industry to grow up and protect their rights just like everyone else.

      It doesn't have to be the huge disaster it is now in this industry, it's self-inflicted by the people working in it.

    2. Re:It won't work... by Anonymous Coward · · Score: 0

      "Guess what I'm saying is: switch to Linux and OSS before you croak, folks. It just seems to make so much sense."

      Why would that make sense? Linux and OSS destroys even more of the value still left in the country.

    3. Re:It won't work... by SammyTheSnake · · Score: 1

      How, exactly, did you reach that conclusion?

      well...

      Switching to open source will only shrink the market even more, there is NO value at all, it certainly will not help.

      You obviously haven't actually thought about this. RedHat, SuSE, IBM, Mandrake, and many others are actually making a reasonable living from OSS, particularly in the service area, providing & supporting the system, not selling the software

      Some people say that IP rights is something unique to this industry, that utterly untrue. More or less all major businesses have substancial IP rights. Patents, copyright, trademarks.

      I agree on this point but...

      What would McDonalds or Coca-cola be without their IP rights? Nothing!

      Gibberish. Coca-Cola may be one example of a "secret recipe", but all McDonalds have is trademarks, they hardly have any patents on the recipe for a burger! Besides, even Cola isn't excactly a closed market, there are dozens of colas on the market, and many of them are only significantly different from Coke because they're working to a cheaper market and they cut corners on quality of ingredients to meet that demand.

      Car-manufacturers don't give out blueprints to their cars, medicine-manufacturers don't give out the ingridients.

      Again, not true. I have two manuals for my motorbike, (I considered buying a third from the manufacturers themselves, but it was three times the price of the other two) which contain as much information about the bike as one would need to be able to completely dismantle it and re-assemble it. There may be techniques involved in the manufacture of parts, but you can ask any forger or material scientist for those. Pharamaseuticals are required by law to tell you exactly what they contain (*grabs a couple of boxes of pills*) "Citalopram Hydrobromide, 20mg", "ibuprofen 200mg" hmm, sounds pretty specific to me. If you're wondering what other ingredients there are, it's chalk, sugar, shellac & sometimes colouring, same as any pill you take.

      It's time for this industry to grow up and protect their rights just like everyone else.

      I think the problem with this suggestion is that the "industry" isn't a single entity, the protection you mentioned above is protection of one party in the industry from another party in the same industry, which is counterproductive in that it reduces the positive benefit available from competition. It means that competition is nothing to do with the quality of the product, rather how easily the customer is duped into *thinking* it's better (or more convenient, or whatever)

      It doesn't have to be the huge disaster it is now in this industry, it's self-inflicted by the people working in it.

      Maybe, but at the end of the day, I think the main reason technology jobs are moving out of the "developed" world and into the "developing" world is money. It's cheaper to employ people in india or wherever, so that's where the business goes. It's nothing to do with IP.

      Cheers & God bless
      Sam "SammyTheSnake" Penny

    4. Re:It won't work... by heironymouscoward · · Score: 1

      Linux and OSS destroys even more of the value still left in the country

      How on earth can you claim this? I've been writing OSS for eleven years, what value have I destroyed? It is as meaningful as claiming that free energy or lower taxes or free transport would destroy value...

      The fact is that cheaper technology is an inevitable consequence of any process of development, which is why you can today afford to throw away items like plastic drink bottles which were incredibly valuable only 50 years ago.

      OSS is symptomatic of the technology curve, and the point of my post is this: if you are too stupid or tradition-bound to make use of the technology curve, you will, inevitably, die.

      I assume when you go to work that you drive a car, and you don't ride a horse?

      I assume that you use a computer to post to /., and you don't send your comments in by paper.

      I assume that your entire home is filled with the cheap near-disposable products of modern industrial society.

      Why, please, should software be exempt from this general rule?

      --
      Ceci n'est pas une signature
    5. Re: Re:It won't work... by Anonymous Coward · · Score: 0

      You obviously haven't actually thought about this. RedHat, SuSE, IBM, Mandrake, and many others are actually making a reasonable living at this.

      Mandrake is near Bankruptcy and IBM to the best of my knowledge has still not shown profits in the OSS market how is this a decent living?

      The reality is OSS shrinks the market. Simply because people can make money in the service sector doesn't mean that OSS is good. People can make money in the service sector of commercial software. In fact, there are more jobs servicing commercial software than OSS. IMHO OSS may have it's advantages but it can do nothing but heart the IT industry.

  19. RTFA by Anonymous Coward · · Score: 0

    a) These chips are designed for supercomputers. When you're running a massive simulation with billions of cells, it's not hard to come up with 64 independent instructions.

    b) Again, these chips are designed for supercomputers. They have compilers that deal with related problems for todays supercomputers. It's not like they'll be using gcc to compile programs for it.

    1. Re:RTFA by Wesley+Felter · · Score: 1

      Actually, I believe DARPA envisions using TRIPS as a general-purpose high-end embedded CPU; think radar signal processing, surveillance imaging, general control tasks, etc. I think they looked at all the different kinds of CPUs in tanks and fighters and said "wouldn't it be nice if one kind of CPU could so everything?"

  20. Cell by Jagunco · · Score: 4, Interesting

    Wasn't the PS3 "Cell" chip made by IBM and Sony supposed to deliver 1 teraflop too?

    1. Re:Cell by Mostly+a+lurker · · Score: 1

      According to a story at the embedded Linux portal, this project is still on track. It is amazing how little hard data there is available. On the face of it, this should be a pretty major product, at least in the entertainment market. Imagine what the film editing and production companies could do with this.

    2. Re:Cell by cybergrue · · Score: 1

      This does sound a lot like the Cell, but less advanced. I wonder if this an old project that just came to light recently or something. Looking at the project it looks like a grid computer on a chip, so in that way it is a bit more advanced then the Cell. They probably just came to the same realizations as Sony did when trying to design a next gen chip, that single core chips were a bottleneck and came to a similar conclusion that multiple cores were a better solution.

  21. Called WHoOPS by Bitmanhome · · Score: 1

    It's actually called TORIAPS, but whatever.

    --
    Not that this wasn't entirely predictable.
  22. Memory by Detritus · · Score: 2, Informative

    It's easy to throw 8 processors on a motherboard. The hard part is designing a memory subsystem that can supply the bandwidth for 8 processors and any other bus masters. Plus, you have to provide cache coherency for all of those processors.

    --
    Mea navis aericumbens anguillis abundat
    1. Re:Memory by White+Rabbitt · · Score: 2, Informative
      Wasn't one of the main premises of the TRIPS system that each processor is more or less independent of its neighbors? They used the term "network" to describe the processors' interrelationship. With operating systems that commonly are processing 20 threads when no apps are running (*cough* XP), what would be the advantage of increased "networking" of the processors?

      It appears that the only issue that would be solved is there would be less lag between processors--but at the speeds they're talking about, the memory supply and caching will present new issues anyhow, ne?

      Sorry about my complete disregard for proper terminology...

    2. Re:Memory by mkramer · · Score: 1

      This processor isn't intended for running general purpose code. Its primary design is for highly streamed code, such as front-end processing for a radar or infrared sensor. It'll host an on-chip OS whose main purpose is to bus data on and off the chip, and handle resource allocation. But 90%+ of those resources are to be dedicated to number crunching in a deterministic fashion, allowing for high parallelism.

      The "network" is merely a dynamic switching layer between onchip components.

  23. Lemme Guess... by SharpFang · · Score: 2, Funny

    TRIPS. Lemme guess. The name says all about reliability of the system.

    --
    45 5F E1 04 22 CA 29 C4 93 3F 95 05 2B 79 2A B2
    1. Re:Lemme Guess... by d60b9y · · Score: 1

      I think it says more about their PR department. Remember the golden rule, acronym first, meaning later...

    2. Re:Lemme Guess... by Anonymous Coward · · Score: 0

      TRIPS? Sounds like a backronym (sp?) to me.. you know, like the Commodore PET ('Personal Electronic Transactor) !!
      God, I'm showing my age!

    3. Re:Lemme Guess... by Valar · · Score: 1

      Eh. Reliability can't really fully be determined until a chip comes off of the line. And this is really theory/sim work. They hope to get someone to buddy up with them and help with an actual proto. And remember, if the same reliability standards were in place for trains as were for computers, they would derail every two hours :) As far as the acronym, I'm gonna have to ask someone about that... (some people blamed it on PR or marketing people, but the EE dept. doesn't really have any)

      --

      ====
      Crudely Drawn Games
    4. Re:Lemme Guess... by drinkypoo · · Score: 1

      I was thinking more along the lines of a certain novel by stephen king (amongst his more inspired works but with a typically poor ending.) That sort of implies that the system will crash out due to a massive virus and only one in a thousand processes remain.

      --
      "You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
  24. TRIPS?!? by Anonymous Coward · · Score: 1, Funny

    SCO smokes crack, IBM goes for trips... what will be next, sysadmins sniffing exploded capacitors instead of ethernet packets?

    1. Re:TRIPS?!? by delirium+of+disorder · · Score: 1

      Awww man, I bit into a polorized capacitor once. OUCH!

      --
      ------ Take away the right to say fuck and you take away the right to say fuck the government.
  25. But... by Anonymous Coward · · Score: 2, Funny

    A) Will it run linux
    B) Run Quake 3 at an acceptable FPS
    C) Take a slashdoting
    D) Make my Coffee
    E) Run Linux
    F) Where is my flying car!?

    1. Re:But... by Anonymous Coward · · Score: 0

      A) Will it run linux
      Yes.

      B) Run Quake 3 at an acceptable FPS
      Yes, but without graphics.

      C) Take a slashdoting
      It's a kinky type, likes spanking, should like slashdotting too.

      D) Make my Coffee
      Sorry, the coolant liquid is poisonous.

      E) Run Linux
      No.

      F) Where is my flying car!?
      You left it in the bathtub together with your boats.

    2. Re:But... by Anonymous Coward · · Score: 0
      [will it] B) Run Quake 3 at an acceptable FPS

      Well, it's being designed by a team researching UT, so Quake obviously isn't one of their priorities.

  26. I just wanted to say... by boola-boola · · Score: 4, Informative

    ....that I've had Doug Burger and Steve Keckler as professors here at UT, and not only do they know their stuff, but they're great professors as well, and they really seem to intimately care about the technology. They have a great sense of humor too (such as Dr. Burger complaining that he doesn't even have root access to his own machines :-P)

    1. Re:I just wanted to say... by Anonymous Coward · · Score: 0

      Man, could you possibly slide your tongue any further up that ass?

      Hope you get that A.

    2. Re:I just wanted to say... by SiJockey · · Score: 1

      Thanks for the nice comment ... and no, I still don't have root access to my own machines!

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
  27. Hyper Threading Type existance by rf0 · · Score: 1

    Now this is cool and if they can make it show itself as 4 CPU's instead of one it might neven mean that porting existing software is easier. Of course I'm not sure what the performance overhead would be

    Rus

    --
    Cheap UK and US VPS
    1. Re:Hyper Threading Type existance by Anonymous Coward · · Score: 0

      It will show itself as 8 CPUs.

      2-core SMT POWER5 chips currently appear as 4 CPUs (2 cores and 2 hyperthread-like 'fake CPUs' per core)

  28. Block Oriented execution by old_unicorn · · Score: 1

    So this processor will get on and do "inquire 'delete *.* are you sure (y/n)'", delete *.* ...pause for user entry to catch up ...oops.

    --
    ***You learn something Every day. And then you die.***
  29. hmmmmm by schappim · · Score: 1

    "block-oriented execution" - I don't know that position, sounds kinky... "which will result in a processor capable of executing more than 1 trillion operations per second." - when she said 'size doesn't count', she lied. ~Marcus

  30. Being done today.... by Anonymous Coward · · Score: 0

    This is nothing new. In fact, you are probably buying "broken" chips today. When the chip makers build CPUs, they mostly all strive for the highest clock-rate that they can get. However, during chip testing, a large percentage of the CPUs fail at the highest rates. So they keep testing them until the find a clock rate that the chip passes at (will work). Then, they mark the chip with that number and sell it.

    So, according to your logic, anyone who is buying a chip that is less than the top rate is buying a bronken chip.

    1. Re:Being done today.... by cbiltcliffe · · Score: 0

      is less than the top rate is buying a bronken chip.

      "Bronken"? Is that a cross between "broken", and "wonky"? :)

      --
      "City hall" in German is "Rathaus" Kinda explains a few things......
  31. Only on /. by kinema · · Score: 1

    Only on Slashdot would someone be complaining about a processor (or processors) that only get 32 billions OPS.

    1. Re:Only on /. by davstok · · Score: 0

      Exactly, I guess you have to spell things out in cleartext here to get modded up...

    2. Re:Only on /. by pla · · Score: 1

      Only on Slashdot would someone be complaining about a processor (or processors) that only get 32 billions OPS.

      Except, they only get that on a fairly narrow range of problems (easily divided into four independant chunks, and heavily CPU bound rather than memory-intensive).

      For some perspective, the newest P4s get 6.4 billion instruction per second, more if you consider the total possible SSE2 throughput. With standard number-inflation, it wouldn't surprise me to find out that this thing does nothing really impressive besides stick four general purpose CPUs on one die, with SMP slightly enhanced as a result of the physical proximity of the cores.

      Of course, perhaps in keeping with your point, I certainly wouldn't turn up my nose if offered one at an affordable price, but as far as how "cutting edge" this seems, I wouldn't cut the budget for "real" supercomputers just yet.

  32. Acronym Attack by Gaxx · · Score: 1

    I wonder how long it took them to work out TRIPS as a abreviation? I suspect a high acronym:hardware design ratio... that said, it took small team a fairly long time to work out LEMUR at our place ;-)

    --
    -- Gaxx
  33. It's actually good to replace the infrastructure by Fefe · · Score: 1

    Why? Because it means people will spend money on infrastructure, which increases cash flow in the IT industry, which will help keep the bubble afloat a while longer.

    A lot of the growth of the computing industry comes from making smarter and backwards compatible products. But look what it got Microsoft to make an Office version that is backwards compatible -- they had to use various other means to ram it down people's throats, because they didn't feel they needed to new version.

    A large part of the turnover and the jobs in the computing industry come from people buying stuff anew they already have, because the new version won't play with the old version.

    This will probably not be so important an argument for the US economy any more, since those jobs are now in India and China, but this cycle of renewal is what secured the survival and even growth of the industry until now.

  34. Re:Note to mods: by Anonymous Coward · · Score: 0

    500 years ago a jewish slave trader tossed my ancester off a cliff 2000 feet to her death so I am severly offended as an African descendant and a human being!

    Anyone named cliffy2000 must be modded down because I am offended!

  35. Re:Note to mods: by Anonymous Coward · · Score: 0

    Maybe his name is Adolf and he's on a hit roll?

    What no one can have the name Adolf now you stupid bagel gobbling yid?

  36. Damn by DarlFromSCO · · Score: 0

    I should have opted for a per-GigaOPS licensing instead of my 699$ per CPU licensing.

    --
    IP law confuses me. I am persuaded slashdot readers who read this sig now legally owe me 699$
  37. But... by The+Revolutionary · · Score: 1

    has Netcraft confirmed it?

    --

    .sig Realistic fines for copyright in

  38. At what cost? by Bruha · · Score: 1

    I wonder if those professors working on these are the same ones who let their TA's come to the first day of class and in some cases first week of class instead of them themselves.

    My fiance was pretty disgusted this year since she's a grad student and for the money's she's paying she does not expect a student to be teaching the class on day one.

    1. Re:At what cost? by ptr2void · · Score: 1

      What's your problem? Does she expect to learn much from the professor on day one? It's more important that the professor is available to the end of a class, when the really difficult questions arise (that some assistants may be unable to answer).

    2. Re:At what cost? by citizen6350 · · Score: 1

      Generally, professors who work on this sort of thing are not course-teachers. They get several years off from the wet-backs to do cool stuff like this when they can get the grants. Time off for good behaviour, so to speak.

      --
      "Sorry Im not more user-friendly."
  39. In related news.. by Viol8 · · Score: 1

    Today IBM announcemed the release of 2 new landmark acronyms: TRIPS and PERC. According to a spokesman: "Well felt that RISC had run its course
    . Its far to familiar to people outside the industry now and besides , it has somewhat negative connotations. With these new acronyms we can
    once more confuse millions of people over the acronymns expected 10 year lifecycle and also it gives us plenty of bad in-joke
    opportunities for our technical authors"

  40. Unfair comparison by axxackall · · Score: 3, Informative
    W2k keeps loading its services even AFTER I login. I can change the boot sequence order to Linux time for X11 Login prompt at least half.

    Well, I don;t need postfix, Apache, Zope, MySQL, PostgreSQL and many other services at the moment of login. So, Win2k designers has recognized the it and optimized the boot sequence being oriented for a desktop user. In Linux we still keep a server-oriented mentality, that's why XDM/GDM/KDM/EDM is always the last thing to start.

    Besides, Win2 boots some services in parallel, while in Linux we still boot all of them sequentially, waiting for [OK] string before starting the next one. The only way to paralelize the sequence is to track dependencies between services. In Gentoo there are some efforts to do the parallel boot.

    But as for now, Linux is (by dfault) is oriented for servers, and GUI login is the last (ltterally last) thing you need on your server.

    --

    Less is more !
    1. Re:Unfair comparison by julesh · · Score: 2, Interesting

      Actually, I have substantially optimised my Linux startup times to get it down to that. I've removed a load of non-essential services (I'm not running a mail server or web server at all now, I only really have stuff that runs from inetd and mysql running other than the absolute essentials) and moved the X startup so that it happens before a lot of other stuff has loaded.

      OK, I'll admit that I haven't parallelised it beyond this, but I wouldn't expect to see a huge amount of improvement from that. Besides, most unix daemons fork and terminate the parent process before doing very much, in much the same way that most WinNT services just call StartServiceControlHandler (or whatever its called) first thing as they get into their WinMain()... there's not a lot to gain by parellelising that.

    2. Re:Unfair comparison by Anonymous Coward · · Score: 0

      " W2k keep loading it's services AFTER I login. "

      I believe the only reason for Linux doing this,
      is on most distro's X11 is started in the last
      run level. run level 5 on Red Hat, and system
      services are started in runlevel 2 and 3.
      Is there a reason why you could not start X11 in 3 and other services like Apache, PostgreSQL, Zope in runlevel 5 ?.

  41. Austin American? by Anonymous Coward · · Score: 0

    Are you an Austin American?

  42. IBM can work with the Japanese by Mostly+a+lurker · · Score: 2, Insightful

    Have you noticed that big Japanese companies seem comfortable working with IBM? I find it difficult to think of any other large US corporation about which we can say the same. IMHO, it is because (while a hard nosed competitor) they deal in a straight fashion with partners. They are seen as trustworthy.

    1. Re:IBM can work with the Japanese by Anonymous Coward · · Score: 0

      unlike the M$. The japanese know that if they
      work with M$, they would get screwed big time..
      Look at AMD and M$ where AMD was supposed to
      supply the processor for the Xbox but they chosen
      Intel instead. And especially IBM and M$ over
      OS/2.

    2. Re:IBM can work with the Japanese by Anonymous Coward · · Score: 0

      will you stop immitating me?

    3. Re:IBM can work with the Japanese by Anonymous Coward · · Score: 0

      The answer is simple: they are reliable and as you said: trustworthy.

    4. Re:IBM can work with the Japanese by Nicolay77 · · Score: 1

      It also helps that IBM was the model they copied to make the Japanese dream company.

      So in their corporate culture they all share an admiration towards IBM.

      --
      We are Turing O-Machines. The Oracle is out there.
  43. hype vaporware by Anonymous Coward · · Score: 0

    yeah yeah sure. Together with diamond seminconductors at 81GHz and block-ordered execution and code morphing.

    aren't you just tired of all these buzzwords.

    DO SOME REAL WORK IBM cretins.
    LAZY sons-o-bitches...

  44. Unit testing by yerricde · · Score: 1

    How are they going to plug in and test an incomplete CPU core designed to work exclusively in tandom?

    In each testing station, have three known-good cores. Connect them to each sample to be tested. If the processor works, move a known-good core to packaging; otherwise, reject the new core. I am not an electrical engineer; is it hard to make cores that can be attached and removed like this?

    --
    Will I retire or break 10K?
    1. Re:Unit testing by Anonymous Coward · · Score: 0

      I am not an electrical engineer, but I have to say that anybody who can make CPUs and production-line robotics perform technological gymnastics like that deserves a medal.

    2. Re:Unit testing by Wesley+Felter · · Score: 1

      See the "chip rework process" section on page 8 of An advanced multichip module (MCM) for high-performance UNIX servers, IBM Journal of R & D, Vol. 46, No. 6, 2002.

    3. Re:Unit testing by anthonyrcalgary · · Score: 1

      The problem is that the chip can't be fully tested until it's mounted in it's packaging, because the heat would not be dissipated fast enough to avoid damage. At least it used to be that way with the Pentium Pro's...

      Also, having the processor cores on different die(s?) would dramatically reduce the efficiency of communication between them, and would dramatically reduce the density of the resulting system.

      --
      When someone might yell at me, it has to be OpenBSD.
  45. Memory by dpilot · · Score: 1

    Do you want it cheap, or do you want it fast?

    We know how to design faster memory, we've done it. Other than a few niches, the marketplace hasn't been willing to pay for it. So we're back to dirt cheap DRAM, because "It's what the customers want," or at least will pay for.

    That said, there are inherent limits to reducing latency, mostly having to do with size. That's why L1 is the smallest cache, and L2 is a bigger cache. L1 is typically the biggest cache that can meet the fastest performance requirements. Because L2 performance is 'shielded' by L1, it's allowed to be slower, and can therefore be bigger. Size is the enemy of speed.

    --
    The living have better things to do than to continue hating the dead.
  46. TRIPS by mistermax · · Score: 1

    Big Blue has gone all Hunter S Thomson then...

  47. Yeah, and we'll get Bono Act II and DMCA II by yerricde · · Score: 1

    Imagine what the film editing and production companies could do with this.

    They could make more films to sell more tickets to buy more bad laws.

    --
    Will I retire or break 10K?
    1. Re:Yeah, and we'll get Bono Act II and DMCA II by Mostly+a+lurker · · Score: 1

      You may well be right. Sigh! But there is a more optimistic scenario. Perhaps by reducing the costs of production, it may give small independent companies a chance to compete and use market pressure to force the big guys to back off.

  48. Wasn't TRIPS... by yerricde · · Score: 1

    Wasn't "TRIPS" the name of the "trade-related intellectual property" treaty that set up WIPO, which in turn created the model legislation for the Digital Millennium Copyright Act?

    --
    Will I retire or break 10K?
  49. Nothing new... just faster by DaHat · · Score: 1

    that's pretty much what a FPGA is, like a Xilinx which will execute many commands in parallel, not just a few pipelines, but entire large blocks, imagine executing 500 if statements in parallel rather then sequentially.

    I'd love to learn to program one... I just don't want to have to learn Verilog.

    --
    Help Brendan pay off his student loans
  50. But really, just *imagine*... by adeyadey · · Score: 0

    but can you just *imagine* a beowulf cluster of these? Oh you already did.. /* If it wasn't for C we would be using OBOL, BASI and PASAL. */

    --
    "You lied to me! There is a Swansea!"
  51. TRIPS are WANCAs by zarniwhoop · · Score: 1

    Wildly Artificial Names for Catchier Acronyms

  52. Linguistic trap by fstanchina · · Score: 1

    It's fun how they had to skip the "adaptive" and put "Intelligent" in there, otherwise the MTTLA would have become "TRAPS"...

  53. No, please, MORE doubleclick.net links and MS by Anonymous Coward · · Score: 0

    I disagree. We need MORE links to doubleclick.net in the original /. stories that go to Microsoft marketing pages.

  54. Re:Wow... by Kasoni · · Score: 0

    Imagine a Beowolf cluster of Beowolf clusters of these :-) Then again that's be to kick ass to be allowed to be public knowledge.

  55. Manditory... by Valar · · Score: 1

    We're not still in the stone age comment, being posted from a real University of Texas tech desk. A lot of the features in the Pentiums and up were based on papers written by professors in my department. AMD has a fab right here in town (well, ok, a little bit outside of town).

    --

    ====
    Crudely Drawn Games
  56. How is Gentoo doing it? by roystgnr · · Score: 3, Interesting

    Besides, Win2 boots some services in parallel, while in Linux we still boot all of them sequentially, waiting for [OK] string before starting the next one. The only way to paralelize the sequence is to track dependencies between services. In Gentoo there are some efforts to do the parallel boot.

    How are they doing it?

    I've often thought that we should be booting up our computers with a parallel invocation of "make". Then when adding a new service you would have none of this "what number between 0 and 100 should I assign?" foolishness: just write a three line makefile that includes all the dependencies that your service has on others.

    1. Re:How is Gentoo doing it? by pmz · · Score: 1

      The only way to paralelize the sequence is to track dependencies between services.

      Then why are we bothering with this System V rc directory structure that encodes dependency orders in the service start-up symbolic link? All that is required is to launch services with the same number simultaneously, and, bam, parallel booting.

      --
      Healthcare article at Kuro5hin
    2. Re:How is Gentoo doing it? by mkldev · · Score: 3, Interesting
      You mean kind of like Mac OS X does? From the docs on OpenDarwin:

      The Property List

      Each startup item bundle contains a property list file at the root level named StartupParameters.plist. The property list is an XML or NeXT-style text file that describes the contents of the bundle. It enumerates the services the bundle prov ides, the services the bundle requires, and other information useful for determining the proper order of execution of the bundles.

      The property list contains the following attributes:

      OPEN CURLY BRACE
      Description = "My Startup Item";
      Provides = "MyService";
      Requires = ("AnotherService", "Network", ...);
      Uses = ("YetAnotherService, ...);
      OrderPreferece = "time";
      Messages EQUALS OPEN CURLY BRACE
      start = "Starting My Item.";
      stop = "Stopping My Item.";
      restart = "Restarting My Item.";
      CLOSE CURLY BRACE
      CLOSE CURLY BRACE
      Apologies for the EQUALS, OPEN CURLY BRACE, and CLOSE CURLY BRACE, but Slashdot considers them to be 'junk'. Oddly enough, it also thinks double quotes are junk. Talk about encouraging plagiarism.

      Here's a modest proposal: if somebody has a Karma bonus, it should be clear that the person doesn't post intentional trolls or other useless crap. Don't subject those of us who actually try to consistently post useful information to these sorts of stupid filters. It only ends up preventing us from being helpful and informative and leads to the decline of the signal-to-noise ratio that it was designed to improve.

      --
      120 character sigs suck. Make it 250.
  57. Another Link by Valar · · Score: 1

    By the way, here's another link: News. This is from the general public friendly news thing on the UT home page...

    --

    ====
    Crudely Drawn Games
  58. TRIPS Does Deal with Latency by G4from128k · · Score: 1

    If you delve further into the project ( http://www.cs.utexas.edu/users/cart/trips/ ) then you will see that the problem of latency is the #1 motivation for the project. TRIPs appraoch to reconfiguring a grid of ALUs should help it maximize utilization. Even so, I doubt that TRIPs is a panacea because so many software problems feature patterns of execution that are undecidable without access to a large space of memory (thus the desire for huge high-speed caches). Yet a more flexible, configurable set of ALU cores and interconnecting pipes might let a computer rebalance itself for maximum performance on a wide range of different tasks including (in their words) workloads as diverse as control-bound integer codes, highly parallel threaded codes, and regular, computationally intensive streaming codes. This ability to perform well, not perfectly, on a wide range of tasks should help the design deliver good performance on mixed and variable environments such as desktop computing and complex database-driven webserving applications. Certainly, TRIPs should be superior to the more rigidly fixed designs of current CPUs or the modestly flexible VLIW-like architecture embodied in Itanium.

    Those that think that multiple cores on a single die mean low yields are assuming that each core must be a multi-million transistor monstrosity like those in current desktop CPUs. They forget that you can create a useful CPU in under 100,000 transistors (e.g., the 68000). Indeed I know of one company, back in the early 90s, that sold a parallel processing board that contained 64 simple, operational transputer cores per chip(CNAPS 1064-64). Moreover, the morphware concept in TRIPs should be able to handle some density of defects in the grid of cores, including end-of-life failures, by remapping the processor net to route around dead/dying ALUs.

    --
    Two wrongs don't make a right, but three lefts do.
    1. Re:TRIPS Does Deal with Latency by SiJockey · · Score: 1

      Your point about yields was right on ... we have been discussing implementing redundant rows of arithmetic units, similar to how they do it in DRAM, so that the large area doesn't whack you in future technologies. The prototype won't have anything like that, of course ...

      --
      --+-- Doug Burger, UT-Austin Computer Sciences
    2. Re:TRIPS Does Deal with Latency by G4from128k · · Score: 1

      Cool. I know that the CNAPs chip actually had 80 transputers per chip, of which only 64 would be enabled.

      It seems to me that a relatively dense, but semirregular interconnect architecture would provide the greatest flexibility for morphing the TRIPS grid to both handle different types of code and to route around internal damage. Admittedly, more complex physical topologies raise the cost of dynamically optimising the logical topology. Have you ever looked into notions like Golumb rulers to set the physical interconnection design?

      Best wishes with the project.

      --
      Two wrongs don't make a right, but three lefts do.
  59. Sir, I must report you.... by wirelessbuzzers · · Score: 1

    You, sir, will be reported to the American Association Against Acronym Abuse.

    --
    I hereby place the above post in the public domain.
  60. Reimporting CPU's from outside the U.S. by Latent+Heat · · Score: 1
    See, the big cost in CPUs is engineering development, not chip manufacture. These foreign governments with socialized computing are going to negotiate low-cost purchases from the American CPU companies, who in turn will have to charge high prices in the U.S., especially to individuals without CPU coverage in their IT insurance.

    Of course Americans will try to sneak over to Taiwan or use the Internet to buy cheap CPUs using purchase orders signed by unethical sysadmins. At that time, the director of the FDA (Federal Dataprocessing Administration), will issue warnings that these foreign CPUs (really repackaged American CPUs) are "insecure" on account of inadequate "testing", and then we will know that the FDA has become a shill for the American CPU companies.

    1. Re:Reimporting CPU's from outside the U.S. by Anonymous Coward · · Score: 0

      Oh no, you don't understand. It is about provide the American CPU companies with money for "research". That's why they rape the U.S. market for money and make your grandma go without food to pay for her CPU prescription. Don't worry though, Congress is going to take care of grandma with prescription CPU subsidies that don't lower the price but line the pockets of American CPU companies.

  61. Dude, ALL chips have defects. by caveat · · Score: 1

    Thats why theyre sold at different speeds - all a P4 2GHz is is a P43GHz with enough flaws to keep its speed down. Nothings actually *broken*, but the defects are still there. IIRC, IBM does sell the Power4 with failed cores on the cheap (I could be wrong though, too lazy to go checking up), as do most other manufacturers (the on-die caches are often sold like that - 32K is just 64K with a broken half).

    --

    Facts do not cease to exist because they are ignored. - Aldous Huxley
  62. And finally one of our generation by Anonymous Coward · · Score: 0

    has started putting some of "our" words into mainstream acronyms. So it begins.

  63. Not just four by Wesley+Felter · · Score: 1

    The prototype is going to have four cores; a final version could have as many as 16.

  64. info and links to related projects by angra · · Score: 1
    this is a link to a collection of links to pages with information on the various projects on the same DARPA funded program as TRIPS.

    This is a link to the software program attempting to provide productive ways to fully exploit this type of tiled, reconfigurable architecture. Not a ton of info there, but some links to papers, presentations, etc., on the general techniques being used.

    1. Re:info and links to related projects by mkramer · · Score: 1

      Just want to add that the info on the non-protected portions of the morphware.org website is generally quite out of date. The technologies and techniques used by the individual teams and the joint efforts have matured considerably.

  65. all we realy need is.... by HaveBlue34 · · Score: 1

    a hardware accelerator for MS office. imagine the sales of TurboOfficeXtreeeeem!(TM)

  66. Re:Wow... by Anonymous Coward · · Score: 0
    Wow. I'm impressed. The first post is moderated redundant. I guess there's no point in reading anything after it, as apparently everything that needs to be said has already been.

  67. A shame by ajole · · Score: 1

    I know it's cliche, but isn't it amazing how kids that young write things that intelligent and don't put themselves to good use?

    --
    -P ...and the boy pulled open his bleary eyes an discovered the python he always knew he was.
  68. It will be CaptainTRIPS, not SkyNet... by Anonymous Coward · · Score: 0

    Enuff said.

  69. Starbridge Systems Revisited by aphxtwn · · Score: 1

    This technology isn't completely revolutionary. Starbridge Systems has taken fractal arrays of programmable chips to help developers/scientists automatically tune chips to help run their algorithms run faster. Most of their clientele is in R&D, pharm, and defense. www.starbridgesystems.com

  70. Re:The promise of the iConomy fulfilled by proverbialcow · · Score: 1

    Dear moderators,
    I defy you to point me to the post previous to this one where such a sentiment is expressed.

    --
    The only surefire protection against Microsoft infections is abstinence. - The Onion
  71. Yes! by TexasCowboy23 · · Score: 1

    Woohoo! Go Longhorns! Longhorns forever!

    (Okay, I'm done. I just had to show some school spirit; I would be evil otherwise.)

    Oh yeah ... As a side note, good for the processor too.

    --
    Seth Anderson BTW, I'm not 23 anymore -- I am TexasCowboy26 now. =)