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Strained Silicon Chips From Intel
Quirk writes "NewScientist is reporting...
"Intel has taken the wraps off a secret technique it is using'Strained silicon' chips to increase the speed of its Pentium and Centrino chips. The technique boosts the rate at which transistors switch, without having to make them smaller.""
Chip Architect was speculating on this way back when intel's 64 bit extensions were still called Yamhill. They make some interesting observations that lead them to belive the second 32 bit ALU was to allow for 64 bit integer operations in a 2x32 bit format. And not to assist with eliminating resource shortages in HT as some others had suggested.
And even if that does pan out it's highly unlikley to appear in desktop Prescott core chips anytime soon. Seems much more like something you'd find in Xeon MPs and later DPs to eliminate the need for that hack they call PAE.
Though i hardly see how 'somebody told us a seinor exec said' makes Slashdot.' (I understand that's what the Inquirier bases most of their news on, i thought we had slightly higher standards of reliability)
There is no god
There was a problem with Fujitsu hard disks a few months back because of a problem with their silicon boards being strained. It turns out that the factory from which they were receiving their silicon from wasn't cleaning the silicon of enough impurities and this resulted in the resulting products based on the bad silicon up and dying with no warning.
While this is not the same type of straining that Intel is doing, it is important to see whether this new technology can function in real world situations without failure. And it is important to test this over a long period of time.
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I know IBM has been publically working with this, at least in research, for a long time, and it's a fair bet other firms were too.
IIRC they've even used SSoI (Strained Silicon on Insulator) for some production ASICs...
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had actually been doing this for years.
Dupe, Maybe read this 2.5 year old story
Shoot, I should tell you about strained silicon. That overclocking experiment I did a couple years ago went horribly wrong when the water pump failed and smoke started pouring out of the case. THAT was decidedly strained silicon. :-)
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Intel sees chip futures strained
Intel strains to find new chips
Intel strains to make chips faster
etc... ad nauseum.
Pulling on my processor with two pairs of pliers just bent a few of the pins and made it smoke a bit...
All of this is at the atomic level, but I do wonder how these things hold up to mechanical and thermal stress.
To stretch the silicon lattice, Intel deposits a film of silicon nitride over the whole transistor at high temperature. Because silicon nitride contracts less than silicon as it cools, it locks the silicon lattice beneath it in place with a wider spacing than it would normally adopt. This improves electron conduction by 10 per cent.
What temperature ranges does this become an issue? If my processor gets warm, will its performance decrease because the strain dissapeared?
Would mild mechanical stress on the chip (i.e. application of heat-sink) alter the strain?
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at least now I could have my silicon pre-strained, instead of having all those Viagara spams do it...
C|N>K
Doesn't this really just focus on the clock speed of the processor which has already been proven not to be the focal point of performance? Switching faster won't increase the bandwidth, maybe it will just be able to push more through the same amount of space then?
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Look Here for Strained Silicon Secret.
Help fight continental drift.
...who claim we're coming to the limits of silicon, and XXXX MHz is the highest that can be achieved. Technology will keep on advancing relentlessly, changing and adapting.
Pick an absolute limit for the speed of a CPU... then proceed to completely ignore it. Can't go wrong there.
Intel potentially uses a new technology that AMD doesn't have, and fan boy talks about how much better AMD will be than Intel when AMD implements said technology. ROFL.
The announcement, at the International Electron Devices Meeting in Washington DC last week, gives a glimpse into the intensely secretive way chip firms attempt to gain an edge over their competitors in a market worth over $100 billion a year. Chip market worth 100 billion dollars ? Wow. That is the thing that stood out for me in the article.
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Still, Butler is frustrated with what he thinks of as myopia in the US computer business. "Europe and Japan have been investing in diamond semiconductor research," he says, citing the Japanese government's announcement in December that it would begin allocating $6 million a year to build a first-generation diamond chip. "Bob Linares has given the US the advantage, but nobody's paying any attention," he says. "If we're not careful, the Japanese or the Europeans are going to claim the diamond niche."
Indeed, Intel's top materials executives weren't aware of the latest research breakthroughs when I spoke to them in June, although they certainly understood the potential for diamonds in computing. "Diamonds represent a seismic change in semiconductors," says Krishnamurthy Soumyanath, Intel's director of communications circuits research. "It takes us about 10 years to evaluate a new material. We have a lot of investment in silicon. We're not about to abandon that."
Click here for full article.
...to remember the last time this was posted.
I'd like to know if the lattice could be stretched in all three directions, rather than just one. And if so, would that provide any benefit? Or does the benefit come from that directionality?
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I've been able to Strain my chip in the bios for years....
Intel may be right on this one - they always have been conservative and this worked out very well for them. Large companies often wait for smaller companies to take the risk and prove or disprove the viablity of new tech. Nobody knows how well diamond is going to work out!
Remember GaAs?
In a response, AMD announced development of "stressed silicon", while VIA reportedly has only managed to "get their silicon slightly worried", according to one unnamed source. China, meanwhile, announced a multi-million dollar project to have silicon going into hysterics within five years.
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Silicone? I was expecting a story about Pamela Anderson.
Damn.
Microsoft has been stressing silicon, including Intel's, for many years!
It's somebody else's joke (I think I read it on the Register or the Inquirer), I can't take credit for it.
I found it pretty funny though.
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Anything P4 and later has the built in temp sensor that slows down the cpu if it overheats. If your cpu is getting so hot that its melting silicon then you have bigger problems to deal with. The tomshardware video still gives me a chuckle when the AMD chip goes *poof* and smokes without a heatsink. Trying to save a few cents I suppose.
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Note that Intel improved the P channel devices 25% and the N channel devices 10%. Since N channel devices are usually 2 to 3 times stronger than P channel devices, this reduces the difference and makes CMOS design a little bit nicer.
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Headline-Intel sees IBM and AMD tech doing well, decides to copy.
link
Silicon on Insulator, Copper Interconnects, DDR memory, dual core, but not HyperTransport yet.
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Strained silicon? Sounds like used processors. Maybe strained silicon is only used to make Celerons.
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Strained Silicon: Ancient Chinese Secret....
-gong-
nothing.can.stop.me.now
Performance is directly related to the speed of the input clock and the internal multiplier.
If the strain were to disappear due to heat, the sole result would be your chip would malfunction or crash. It wouldn't cause it to slow down.
Much as a regular chip can be overclocked to failure and has no internal mechanism to prevent it, these chips have no way to know that their strain mechanism is no longer working.
I thought straining silicon was how they got the impurities out.
Sure strained silicon is great, but the real advance was the world's smallest colander.
Letter To Iran
There are several new technologies that either are speeding up chips, or will speed up chips, and the best part is that they'll all work together.
For some time, SOI (silicon-on-insulator) has been helping chip manufacturers squeeze out extra performance. And the straining of the silicon lattice (strained silicon) helps as well. And you can combine them into SSOI, strained-silicon-on-insulator.
Well, there's also one other technology that's been developed, called "fully depleted silicon". And guess what - it should/will be possible to make fully-depleted, strained silicon-on-insulator chips. (FDSSOI?)
Between moving to 90 nm, then 65nm, and then further, as well as integrating high-K dialectrics and fully-depleted, strained silicon-on-insulator manufacturing technologies, we've still got a lot of headroom to keep cranking out faster and faster processors. Moore's law has still got a long time to live. And that's even if we don't make any new breakthroughs, but my guess is that the chip makers will continue to pull aces out of their sleeves, so to speak.
steve
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Opter? Damn near K-lined her!
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Francis Smit
The article states that compressing p-doped regions improves hole conduction and stretching n-doped regions improves electron conduction. Fair enough, but to me the p-doped and n-doped designations are either backwards or irrelevant.
For example, an n-channel MOS device is built in a p-type well. The channel (region between source and drain) is p-type when the device isn't conducting current, but the channel must be inverted to n-type before electrons can flow from source to drain. Correct me if I'm wrong, but it would make more sense to say that the p-well is stretched so that when it is inverted, electron conduction in the channel is improved.
I wonder how much layout re-work had to be done to implement moats of SiGe around individuel transistors or groups of transistors. Yikes!