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Intel Shows 48-Core x86 Processor

Vigile writes "Intel unveiled a completely new processor design today the company is dubbing the 'Single-chip Cloud Computer' (but was previously codenamed Bangalore). Justin Rattner, the company's CTO, discussed the new product at a press event in Santa Clara and revealed some interesting information about the goals and design of the new CPU. While terascale processing has been discussed for some time, this new CPU is the first to integrate full IA x86 cores rather than simple floating point units. The 48 cores are set 2 to a 'tile' and each tile communicates with others via a 2D mesh network capable of 256 GB/s rather than a large cache structure. "

366 comments

  1. Meh. I'm holding out for a kilocore. by jeffb+(2.718) · · Score: 1

    ...or perhaps a megacore?

  2. Codenames by VorpalRodent · · Score: 1

    Why can companies not come up with decent code names. For instance, this would be the perfect case for it being codenamed "Beowulf".

    --
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    1. Re:Codenames by Anonymous Coward · · Score: 0

      They called it Bangalore because they are going to farm out your processes.

    2. Re:Codenames by somersault · · Score: 1

      Just imagine.. a Beowulf cluster^2!

      --
      which is totally what she said
    3. Re:Codenames by revlayle · · Score: 3, Funny

      Could you imagine a Beowulf cluster of Beowul.... *head explodes*

    4. Re:Codenames by Knara · · Score: 1

      Intel has always had less than catchy code names, IMHO.

    5. Re:Codenames by Acapulco · · Score: 2, Funny

      *head asplodes*

      There, fixed that for you.

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    6. Re:Codenames by azrael29a · · Score: 5, Informative

      Why can companies not come up with decent code names. For instance, this would be the perfect case for it being codenamed "Beowulf".

      They're using geographical names (cities, places, lakes, rivers) to avoid having to register the codename as a trademark. Geographical names can't be trademarked so no one will use your codename for his trademark.

    7. Re:Codenames by Fulcrum+of+Evil · · Score: 1

      Or rather, a Beowulf^2 cluster.

      --
      "We returned the General to El Salvador, or maybe Guatemala, it's difficult to tell from 10,000 feet"
    8. Re:Codenames by Anonymous Coward · · Score: 0

      > They called it Bangalore because they are going to farm out your processes.

      To Maine..??

      (Oh, sorry, that's Bangor. My bad!)

    9. Re:Codenames by Chees0rz · · Score: 3, Funny

      > They called it Bangalore because they are going to farm out your processes.

      To Maine..??

      (Oh, sorry, that's Bangor. My bad!)

      Uh, no. That's Bang-ah, Maine. Bangor is a Myth.

    10. Re:Codenames by somersault · · Score: 1

      Either way, I don't want to be paying for that power bill..

      --
      which is totally what she said
    11. Re:Codenames by JWSmythe · · Score: 1

          Where do you think they got the cheap labor to design it? Not here in the US. Oh no, farm everything out to keep our costs down. {sigh}

      --
      Serious? Seriousness is well above my pay grade.
    12. Re:Codenames by jimmydevice · · Score: 1

      Wow, That totally escaped me.

    13. Re:Codenames by biryokumaru · · Score: 1

      Bangor is in Washington

      --
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    14. Re:Codenames by Whiteox · · Score: 1

      Actually, Bangor is in Wales.

      --
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    15. Re:Codenames by evilbessie · · Score: 1

      Bangor is in Wales.

    16. Re:Codenames by cheekyboy · · Score: 1

      They could have choosen some names from this list.
      http://www.i-r-genius.com/rudeplaces.html

      Lord Berkeley's Knob

      --
      Liberty freedom are no1, not dicks in suits.
    17. Re:Codenames by Brad+Eleven · · Score: 1
      --
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      (click)
      "Release to detonate."
  3. Re:Meh. I'm holding out for a kilocore. by Anonymous Coward · · Score: 0

    manticore?

  4. Windows 12 by Anonymous Coward · · Score: 0

    Windows 12 will require a minimum 48-core 1.4 THz processor and 8TB of RAM. Microsoft are already planning for this one.

    1. Re:Windows 12 by mikael · · Score: 4, Interesting

      Microsoft once had a podcast where they were talking about multi-core CPU kernels. Their belief was that once you had 50+ cores, you would be able to have a mutex for every single COM object element, simply because you could.

      --
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    2. Re:Windows 12 by poetmatt · · Score: 1

      my idea when you had enough was that each process thread can be on it's own processor, is the idea of a mutex for every com object similar? I don't really get 100% what a mutex is.

    3. Re:Windows 12 by Rockoon · · Score: 5, Informative

      A mutex (MUTually EXclusive) is a software methodology in which one thread or process can (usually temporarily) lock a resource (such as a memory location) so that another thread or process may not access it.

      It is most often required because resources are normally not 'atomic.' For instance, a string in memory is made up of many machine words and a CPU cannot read or write multiple machine word values in one operation. The danger is that while one CPU is writing to such a non-atomic collection of values, another might be trying to read from (or write to) it.. creating a situation where that second process reads part of the old data and part of the new data (essentially garbage data.)

      So the idea of a MUTEX is born, in which an atomic value is leveraged to allow a thread to reserve such resources, signaling others (if they respect the MUTEX as well) to wait their turn.

      --
      "His name was James Damore."
    4. Re:Windows 12 by greensoap · · Score: 1

      A mutex is a way of controlling access to a shared resource. Imagine you have a car with one key. If you and your sibling both want to use the car for the night, the key is the mutex. Whoever gets the key first gets to use the car until they put the key back.

      /. loves car analogies, right?

    5. Re:Windows 12 by Fred_A · · Score: 1

      A mutex is a way of controlling access to a shared resource. Imagine you have a car with one key. If you and your sibling both want to use the car for the night, the key is the mutex. Whoever gets the key first gets to use the car until they put the key back.

      But, wait, don't cars come with two keys ?

      Now I'm confused.

      --

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    6. Re:Windows 12 by afidel · · Score: 1

      How silly, I have a couple hundred threads running right now and each of those probably has numerous COM objects. That's with a few startup apps, a few addon services, a browser and a minimum of windows services (I disable everything I don't need which is about half the default Windows install).

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    7. Re:Windows 12 by JWSmythe · · Score: 3, Informative

          It doesn't matter much. The first sibling to grab key 1a is usually running for the car. Even if the other sibling grabbed key 1b, they'll be looking at an empty parking spot, complaining to mom. :)

      --
      Serious? Seriousness is well above my pay grade.
    8. Re:Windows 12 by Anonymous Coward · · Score: 0

      That would be a funny name for Windows, at least for portuguese speaking people.
      Hint: 12 = doze.

    9. Re:Windows 12 by PerfectionLost · · Score: 1

      Which will let their developers be even less efficient with their code.

  5. 'Single-chip Cloud Computer' by Anonymous Coward · · Score: 0

    What the heck? Just, what the heck?

    1. Re:'Single-chip Cloud Computer' by eln · · Score: 1

      What's the big deal? You're going to need a single-chip cloud computer if you want to operate in the Semantic Web.

    2. Re:'Single-chip Cloud Computer' by Tetsujin · · Score: 1

      What the heck? Just, what the heck?

      Yeah, a better code-name would have been "Lakitu"...

      Damn cloud, always following me around throwing things at me...

      --
      Bow-ties are cool.
    3. Re:'Single-chip Cloud Computer' by amirulbahr · · Score: 1

      Agreed. Since when did "cloud" mean multi-core computer or CPU?

  6. Re:Code Name is Offensive by eln · · Score: 4, Insightful

    It was called Bangalore to remind you where to call if you need any support for it.

  7. 2D mesh networks are not technically viable by Anonymous Coward · · Score: 0

    They may work fine in towers but drop right out of side mounted desktops and small media units.

  8. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    Far more likely to remind you WHERE it was designed.

  9. Re:Code Name is Offensive by RManning · · Score: 1

    Intel an American company, with the American economy in the shape it's in, I am offended at the codename Bangalore.

    Not to be dense, but why is that offensive?

  10. Larrabee? by Anonymous Coward · · Score: 1, Interesting

    This seems like it would be very related to their Larrabee GPU project.

    1. Re:Larrabee? by V!NCENT · · Score: 1

      What? Vector units inside?

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    2. Re:Larrabee? by Rockoon · · Score: 0

      It has been leaked that Larrabee will include many (8 or more) x86 "light" cores. Some instructions from the x86 gone, but most still available (including a wider SSE.)

      --
      "His name was James Damore."
    3. Re:Larrabee? by V!NCENT · · Score: 2

      Leaked? Dude I got the freaking instruction set in my mailbox. Want the public PDF? It's an ordinary x86-64 CPU that is capable of vector processing stuff...

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    4. Re:Larrabee? by hattig · · Score: 1

      This 48-core CPU is hopefully leveraging the Larrabee CPU (minus the vector unit), otherwise it's yet more Intel developmental waste. That, or it's the original Pentium, shrunk down (Larrabee's core started out with a Pentium-like design/specification too).

      The core is under 6mm^2 when you look at the die. L2 cache, router, intra-core communications are about another 5mm^2.

  11. Re:Code Name is Offensive by Anonymous Coward · · Score: 0, Interesting

    It makes sense, afterall.

        Intel made a new 48 core x86 chip called cloud computing on a chip.
        Funny thing is, cloud computer is like outsourcing your computer hardware to a bigger machine that's cheaper to use due to the rental pricings... etc...
        The name of the chip you ask?
        BANGALORE (outsourcing capital of the world)

  12. Re:Code Name is Offensive by MobileTatsu-NJG · · Score: 3, Funny

    Intel an American company, with the American economy in the shape it's in, I am offended at the codename Bangalore.

    As the last remaining operational Soong type android, I am offended by the name Bang-A-Lore.

    --

    "I like to lick butts!" by MobileTatsu-NJG (#32700246) (Score:5, Informative)

  13. Advantages over just adding more FPUs? by Hadlock · · Score: 1

    Can someone elaborate on why you'd want 48 full processors, rather than a processor with two (dual) or four (quad) "cores" (I'm presuming core in this case == FPU in the article). Supposedly Win7's SMP support becomes much more effective at the 12-16 core thresehold.

    --
    moox. for a new generation.
    1. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 2, Funny

      To enable system administrators to say "Fuck it, we'll go to one blade!"

    2. Re:Advantages over just adding more FPUs? by h4rr4r · · Score: 1

      For a server.
      Probably not running windows, as linux and other *n.x type OSes support monstrous amounts of CPUs already.

    3. Re:Advantages over just adding more FPUs? by Locke2005 · · Score: 2, Insightful

      Current memory architecture has trouble keeping data fed to just 2 CPUs; unless each of the 48 cores has it's own dedicated cache and memory bus, this is a pretty useless design.

      --
      I've abandoned my search for truth; now I'm just looking for some useful delusions.
    4. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      Yes. YES! Raytracing! And emulating a D3Dn card in software (Google: pixomatic) and run the latest game with acceptable framerates.

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    5. Re:Advantages over just adding more FPUs? by Yaztromo · · Score: 4, Insightful

      Can someone elaborate on why you'd want 48 full processors, rather than a processor with two (dual) or four (quad) "cores" (I'm presuming core in this case == FPU in the article).

      Bad assumption. In this case, we're talking about (what you would consider) a 48 core CPU. Previous designs would have apparently contained only a small number of full processing cores, and a large number of parallel units suitable only for floating point calculations (which can be great for various types of scientific calculations and simulations). This new design contains 48 discrete IA x86 cores.

      Seems like the type of processor Grand Central Dispatch was designed for.

      Yaz.

    6. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      Yes. Serial RAM acces. Damn. When are people going to realise that RAM, which has a lot of, what are they called, banks?, hysically seperated from each other, could be made paralell?

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    7. Re:Advantages over just adding more FPUs? by eabrek · · Score: 1

      Each core has an FPU, so # of cores == # of FPU.

      Adding the rest of the core effectively gives you # of instruction pointers == # of FPU. So now, you can run more branchy code (like raytracing and physics simulations).

    8. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      Heh. I remember the old CDC Cyber mainframes, which had like 1 ms core memory... 64-way interleaved. Serial location access wasn't all that bad, as a result: 16 us sequential access time.

    9. Re:Advantages over just adding more FPUs? by eabrek · · Score: 1

      You can overlap memory accesses to different banks. But the data bus will always be a chokepoint.

    10. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      So why not multiple busses to the CPU?

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    11. Re:Advantages over just adding more FPUs? by RyuuzakiTetsuya · · Score: 1

      webserver on a high traffic site. Either serving up lots of db connections or a lot of http connections, either way, I can imagine this having specific uses.

      --
      Non impediti ratione cogitationus.
    12. Re:Advantages over just adding more FPUs? by eabrek · · Score: 4, Informative

      That's what each channel is. I forget exactly, but each DDR channel is almost 200+ pins (RDRAM was considered a big win because it is about 80). And pins == money (mainly in die area).

    13. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      NUMA?

    14. Re:Advantages over just adding more FPUs? by qmaqdk · · Score: 1

      For a server.
      Probably not running windows, as linux and other *n.x type OSes support monstrous amounts of CPUs already.

      If you're thinking of virtualization, then I don't think it necessary (in typical cases). The bottleneck is usually disk access.

      --
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    15. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      Is there a programming language or some kind of lib to let a programmer take advantage of this?

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    16. Re:Advantages over just adding more FPUs? by h4rr4r · · Score: 1

      Then you need a faster connection to your discs.

      I was not talking about virtualization. Just several very high cpu usage but trivially parallelizeable things we use here.

    17. Re:Advantages over just adding more FPUs? by vertinox · · Score: 4, Interesting

      Can someone elaborate on why you'd want 48 full processors, rather than a processor with two (dual) or four (quad) "cores" (I'm presuming core in this case == FPU in the article). Supposedly Win7's SMP support becomes much more effective at the 12-16 core thresehold.

      The first thought comes to mind if video processing and CGI animations because those applications are embarrassingly parallel.

      And those companies usually have the money to spend on top of the line hardware.

      Eventually this will trickle down to consumer level as always and people at home can now do real time movie quality CGI on their home computers in 10 years.

      --
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    18. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      Yeah, but then again, no...

      Each memmory bank linked to each core. Letting the programmer sort it out...

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    19. Re:Advantages over just adding more FPUs? by eabrek · · Score: 3, Informative

      Multiple channels and overlapped memory access? The hardware does it automatically. No need to program anything different (well, I guess there is BIOS code somewhere that configures all the channels and bank information - but most people shouldn't see that).

      Now, programming a 48 core FPU monster? That is a much harder problem!

    20. Re:Advantages over just adding more FPUs? by Belial6 · · Score: 1

      Multi-user systems? If 1 user can max out a dual core processor now, what would happen if you put 48 people on that same system?

    21. Re:Advantages over just adding more FPUs? by RotateLeftByte · · Score: 0, Troll

      Imagine being able to run 48 copies of solitaire or Notepad at once?

      Oh silly me. you can do that already.

      Apart from Vidoe type apps this is a pure server type CPU but unless Intel can sort out the memory access there is going to be an awful lot of cache misses and waiting for data & code from RAM. Unless, it has 10Gb of L1 cache.

      --
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    22. Re:Advantages over just adding more FPUs? by Locke2005 · · Score: 3, Interesting

      No need to program anything different Actually, I believe performance can be improved by pre-fetching data into cache ahead of time, so you know it will be there when you need it. I was doing this in software on MIPS to improve Linpack performance; I suspect you can do much the same with Intel processors as well.

      GPUs are using 256 bit wide data paths now to improve data throughput; I think it is only a matter of time until the memory bus is a whole cache line (256 bits?) in width, enabling read/writing of entire cache lines in a single operation. Seems simple to me, but your pin count and power usage go up, as well as the number of separate DRAM chips you need for a wider memory bus.

      --
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    23. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      There have been independent channel designs for years now. Most current consumer accessible independent channel design for PC CPUs would be the recent products from AMD. The Nehalem don't seem to support independent operation of the three memory channels.

    24. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      But what if I want to NUMA style do everything parallel? I am trying to figure out a way to make a realtime ray tracing renderer for the desktop. HD gaming is going to be hell... With every idea that I've come up I am constantly smashing my head against the serial RAM problem... And I do not want to wait for more than 5 years for this to work...

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    25. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      Does that include the Phenom 9950 x4?

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    26. Re:Advantages over just adding more FPUs? by drinkypoo · · Score: 1

      Bad assumption.

      What's so bad about it?

      Previous designs would have apparently contained only a small number of full processing cores, and a large number of parallel units suitable only for floating point calculations (which can be great for various types of scientific calculations and simulations).

      Contemporary processors have many functional units, but they are only segregated into a small number of cores to minimize issues with inter-core communication, communication with memory, et cetera. AMD has generally had shorter pipelines (reduced cost of branch misprediction) and since the K7, superior memory bandwidth (not to mention a highly successful NUMA architecture.) Having more cores with the same number of functional units demands the use of a high number of processes and/or threads for maximum utilization, so a processor with a similar number of functional units but segregated into more cores is going to be suitable for different workloads than what you can buy right now.

      --
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    27. Re:Advantages over just adding more FPUs? by Enderandrew · · Score: 0, Troll

      What are you talking about? With 48 distinct cores, I can finally turn on Aero!

      --
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    28. Re:Advantages over just adding more FPUs? by Hadlock · · Score: 1

      What happens if you put 47 people on that system? Or what happens if 100 people are only checking email and doing word processing? And two people playing quake live in firefox??? What then???

      --
      moox. for a new generation.
    29. Re:Advantages over just adding more FPUs? by Korin43 · · Score: 1

      You could run a pretty fast quicksort.. Not sure if that counts as 'useful' ;)

    30. Re:Advantages over just adding more FPUs? by TheRaven64 · · Score: 3, Informative
      Processors access memory via a cache. When you load a word from memory to a register, it is loaded from cache. If it is not already in cache, then you get a cache miss, the pipeline stalls (and runs another context on SMT chips), and the memory controller fetches a cache line of data from memory. Cache lines are typically around 128 bytes. Modern memory is typically connected via channel that is 64 bits wide. That means that it takes 16 reads to fill a cache line. If you have your memory arranged in matched pairs of modules then it can fill it in 8 pairs of reads instead, which takes half as long.

      On any vaguely recent non-Intel chip (including workstation and server chips for most architectures), you have a memory controller on die for each chip (sometimes for each core). Each chip is connected to a separate set of memory. A simple example of this is a two-way Opteron. Each will have its own, private, memory. If you need to access memory attached to the other processor then it has to be forwarded over the HyperTransport link (a point-to-point message passing channel that AMD uses to run a cache coherency protocol). If your OS did a good job of scheduling, then all of the RAM allocated to a process will be on the RAM chips close to where the process is running.

      The reason Intel and Sun are pushing fully buffered DIMMs for their new chips is that FBDIMMs use a serial channel, rather than a parallel one, for connecting the memory to the memory controller. This means that you need fewer pins on the memory controller for connecting up a DIMM and so you can have several memory controllers on a single die without your chip turning into a porcupine. You probably wouldn't have 48 memory controllers on a 48-core chip, but you might have six, with every 8 cores sharing a level-3 cache and a memory controller.

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    31. Re:Advantages over just adding more FPUs? by Jeremy+Erwin · · Score: 2, Interesting

      Embarrassingly parallel is right. Cache coherency was sacrificed in order to up the number of cores, though I suppose a Beowulf on a chip is still useful for some things.

    32. Re:Advantages over just adding more FPUs? by rjcwlgnz · · Score: 1

      Raytracing is moving to programmable gpus

    33. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      To run Ruby on Rails.

    34. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      There is no cache coherency. Each pair of cores acts is effectively a separate computer. So Grand Central Dispatch won't do you much good.

      Give that processor some more memory bandwidth and it could be a reasonble GPU.

    35. Re:Advantages over just adding more FPUs? by NemoinSpace · · Score: 1
      i agree, it was presumptuous of him to assume that his assumption was based on fact. Clearly, it was simply a narrowly defined bad presumption. His cited example of the grand central dispatch shows why -- "...Apple states that 15 instructions are required to queue up a work unit in GCD, while creating a traditional thread could easily require several hundred instructions." See how a well defined argument is better than a generalized presumption?

      Anyway, I actually learned a little today, Either way you look at it, it's only 48, when they get to 640 - that should be enough for either of you.

    36. Re:Advantages over just adding more FPUs? by Bengie · · Score: 2, Interesting

      I was recently reading an article about multi core designs and they said they'll have to drop cache coherency at some point soon and redesign locking a bit. Some other architectures don't use cache coherency to help with scaling, but that's not x86.

    37. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      For a server. Probably not running windows, as linux and other *n.x type OSes support monstrous amounts of CPUs already.

      Yet still can't run Flash smoothly. :(

    38. Re:Advantages over just adding more FPUs? by Bengie · · Score: 1

      cache lines are 64bytes. Prefetch is pretty good on recent CPUs. Any idea how often cache misses happen?

      Many benchmarks show the Corei7 gaining almost no performance doing from double to triple channel memory. Cache misses going all the way out to main memory must not be happening too often if the CPU's are handling 8 strong threads on only dual channel memory.

      I wonder how going to so many small cores will affect cache misses. Typically they reduce the cache per core to, so more chances to cause misses and more bottlenecks at the memory controller.

    39. Re:Advantages over just adding more FPUs? by maraist · · Score: 4, Informative

      What is worse is that theyve done away with cache coherence. So I dont think you can take a 48 thread mysql / java process and just scale it. You COULD use forked processes that don't share much. (ie postgres/apache/php).

      --
      -Michael
    40. Re:Advantages over just adding more FPUs? by maraist · · Score: 2, Interesting

      Im not sure "separate computer" is accurate. you get copy on write performance benefits. So fork based processes would work like gang busters. Multi threading COULD work if they never modified common data pages. I'll just assume they have some kind of support for high performance mutexes.

      --
      -Michael
    41. Re:Advantages over just adding more FPUs? by LUH+3418 · · Score: 1

      If it's one of those "let the programmer sort out memory access and cache management" kind of architecture, that will make developping any kind of software for it much harder than traditional SMP, and it kind of defeats the point of having x86 cores in the first place. Just look at the cell processor in the PS3... Lots of games don't use it, simply because it's hard to program.

    42. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      Then the two people playing quake live start whining about 'the man' on the mainframe keeping them down, wonder who really keeps their data, and decide to get personal computers.

      oh, wait...

    43. Re:Advantages over just adding more FPUs? by afidel · · Score: 1

      2008 is certified up to 256 cores because that was the biggest box available during development, the kernel can support more easily.

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    44. Re:Advantages over just adding more FPUs? by afidel · · Score: 1

      Actually the OS or Hypervisor really needs to be NUMA aware for optimal performance, that way it can allocate RAM from the pool that is close/attached to the core on which the requesting process is running if available. Windows and ESX do this fairly well, not sure about Linux though I assume it's fine by now. Applications can also help but my experience with the NUMA patches for Oracle have been less then great, I would guess the code is just less mature and less used but we had no end of issues with it and so backed off to the non-NUMA tree.

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    45. Re:Advantages over just adding more FPUs? by afidel · · Score: 4, Informative

      The reason the i7 gains nothing going from double to triple channel memory is that the memory controller is power limited and so can only run at reduced clocking on triple channel configurations 800Mhz down from 1333Mhz. Of course for most workloads having 50% more data in RAM instead of glacially slow storage is a win =)

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    46. Re:Advantages over just adding more FPUs? by Avtuunaaja · · Score: 4, Interesting

      A cache line on a modern Intel/AMD processor is actually 512 bits, or 64 bytes.

      A memory bus 512 bits wide wouldn't really help much, though -- right now when dealing with memory, most of the time is spent in the various latencies. When you are fetching a lot of memory sequentially, you can get insane speeds even today. But that's not how you usually read memory -- instead, you read a few words from different locations, and the memory controller needs to activate the correct bank, row and column before you get what you need. On typical PC-10600 DDR3, that means at least 15 bus cycles just waiting around for the memory to adjust. Making the bus 512 bits wide would speed up the actual transfer to one bus cycle from the 4 what it takes currently, but that would only mean an improvement of about 15% -- at a huge cost for having to accommodate those 384 extra data lines on the chip, socket, motherboard and ram. It's better just to try to speed up the memory so burst transfers happen "fast enough".

      I don't know about nvidia cards, but at least for ati the card doesn't actually have a 256 bit memory interface -- instead, it has 4 completely separate 64-bit memory channels connected to a fast ring bus. The interleaving of data on those separate memory channels is done very coarsely -- basically, entire textures and such are allocated on a single channel. This means that when that texture is being fetched, the 3 other channels can serve other requests.

      This is the way I see cpu's evolve too -- even on current hardware, namely phenom 2, you get better performance when you ungang the memory channels, and wait 8 cycles for a single memory transfer instead of 4, because that way you get to wait on separate latencies on the separate channels at the same time. Of course, in the perverse case all the data you want to access resides on one of the channels, but the chance of that happening by accident is pretty much nil.

    47. Re:Advantages over just adding more FPUs? by symbolset · · Score: 1

      Don't worry. All those guys will get test samples and port their stuff. When the chip is available your favorite software will be well on the way.

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    48. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      Mod this guy up, heavily. It's a shame this point will go over so many people's heads. The article glossed over it as well.

      I read that part and I couldn't say I was surprised (cache coherence is what screws up parallel performance, and all the most scalable architectures for this have relaxed memory models or otherwise assume data sharing not to happen). However, this is going to be tough to adopt for mainstream use. Threads are pretty much the dominant mainstream programming model and it's going to be impractically annoying to port stuff to it.

    49. Re:Advantages over just adding more FPUs? by Bengie · · Score: 1

      ohh, dang.. ty for the info

    50. Re:Advantages over just adding more FPUs? by daVinci1980 · · Score: 1

      How many single workloads do you think were already pushing the 2G or 4G in the numbers that Intel was trying to sell into? And how many of those workloads do you think would've benefited from less than 50% more memory?

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    51. Re:Advantages over just adding more FPUs? by afidel · · Score: 1

      Not many desktop workloads are memory bandwidth bound but plenty could benefit from more HDD cache. The same restriction also applies to the Nehalem Xeon's but again *most* workloads benefit from more RAM, though there the exceptions are more numerous (some DB workloads are performance limited by the number of objects tracked so more cache doesn't improve performance but they do benefit from more memory bandwidth). For the people that really need to care about such things the information is readily available so they can make the determination based on their needs. One funny result of the intricacies of Nehalem memory controllers is that if you are using Windows x64 standard you get WAY better performance with 36GB of memory than with 32GB despite the fact that the OS will only access 32GB because you are filling the bank and that makes the whole system significantly faster than with 1 DIMM missing.

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    52. Re:Advantages over just adding more FPUs? by Bengie · · Score: 3, Informative

      Cache coherency should be handled by the programmer, not by the hardware. Cache coherency protocols consume more bandwidth the more cores you get. The more cores you get, the more important that bandwidth becomes. At some point Cache coherency will become a bottleneck. We've been holding quite well to doubling transistor count every 18 months. If we suddenly go from strong single cores to somewhat weaker multi cores, not only will they pack more cores in for the same transistor count, but more transistors.

      Imagine, our 4 core cpus will be 8 core in ~18months, then 16 ~18 more month. Intel has hyper-threading and AMD has a similar thing, so now it's like 32 cores. So, in ~ 3 years, at our current rate, we could have 32 logical CPUs reporting for low-mid sub $1.5k computers

    53. Re:Advantages over just adding more FPUs? by smallfries · · Score: 2, Insightful

      What's so bad about it?

      The worst thing about his assumption is that it is wrong. But that is sufficient to make it bad.

      Contemporary processors have many functional units, but they are only segregated into a small number of cores to minimize issues with inter-core communication, communication with memory, et cetera

      This is simplistic and wrong. It is true that fewer cores implies less inter-core communication, but this is not a design criteria for putting fewer cores in a system. While it is true that having more cores requires more threads/processes to achieve high utilisation it is not necessarily true that having fewer cores with more functional units per core allows high utilisation across workloads with few threads.

      Increasing the number of functional units per core runs into diminishing returns quickly as keeping all of them fully fed requires lots of implicit parallelism in the program. To be able to execute sequential workloads well on a system with few cores and many functional units, there must be lots of independent chains of operations within the program. Not many sequential programs exhibit this property, and those that do can often be rewritten into a threaded form. Hence a system with more cores is more efficient on server-style workloads (lots of fully independent requests) and on workloads with lots of fine-grained parallelism if the programmer can rewrite the code using threads.

      The last if is a big one, and it is the only reason that we are seeing mainstream designs with "few" cores. If we knew how to parallelise the code better then designs with many cores, and fewer functional units per core are a lot more efficient. One of the main reasons is that the size of the register file needed on a core is proportional to the amount of data needed to be kept in-flight to keep the functional units full. But as the number of registers increases, and the number of read ports into functional units increases the complexity of the register file does not grow linearly (if memory serves I think it is quadratic).

      So designs with few cores, but large register files, are less efficient than more cores (even with more associated issue/despatch) with more registers per core. Of course this is not an exact science as finding representative benchmarks is hard, and then creating a design to hit the right set of parameters is also hard. But that is the reason that Intel have tried this design - research. It's also the reason that designers don't just throw their transistor budget at maximising the number of units within a single core.

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    54. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      Or TBB : http://software.intel.com/en-us/intel-tbb/

      http://en.wikipedia.org/wiki/Intel_Threading_Building_Blocks

    55. Re:Advantages over just adding more FPUs? by X0563511 · · Score: 1

      Blame Adobe for that one.

      --
      For large sets, this will be our guide even unto death, for the LORD will work for each type of data it is applied to...
    56. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      "If it's one of those "let the programmer sort out memory access and cache management" kind of architecture, that will make developping any kind of software for it much harder than traditional SMP"
      And more powerfull. If a developper wants max performance and he can't do that, then well that sucks. For everyone else there is Ruby & Crap.

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    57. Re:Advantages over just adding more FPUs? by apposite · · Score: 2, Informative

      parent++ (I'm not saying much more than parent post has already said.)

      We've more or less hit the limits of useful gains from increasing pipeline depth (and thus increasing clock frequency) or increased Instruction Level Parallelism (which gives you superscalar/multiple dispatch per clock cycle). The silicon required to do the book keeping starts being more of an overhead than you can get by simply rolling back to a simpler core and having more of them- which is precisely what has happened. As of about 2007 clock rates were generally down from their peak with increased throughput coming from the addition of multiple cores.

      Multiple cores- full cores with FP and everything!- are useful for Task Level Parallelism, which can be difficult to achieve on a single job but is a very nice fit for many server loads (like web serving) where individual threads have very little interaction. Desktops will no doubt inherit many core (8+) CPUs from the server world, but I'd guess that we'll actually see desktop CPUs shrinking- requiring less power and following the laptop power curves. There may even be a more pronounced separation between the "power desktop user" who uses their CPU for intensive graphic rendering (i.e a graphics workstation or gamer machine) and everyone else (who ends up using a mere 4 or 8 core machine which requires little or no active cooling).

      Servers will continue to pack more and more cores with more and more memory. The bandwidth bottleneck is RAM, not Disk as was mentioned in one comment (any serious server setup uses a variety of strategies to serve most content from RAM and only writes to Disk for persistence or tail end performance). This also means they'll have more NICs, and there will be pressure to push the network speed up to keep the CPU and RAM busy.

      The reference book on this sort of thing (and apologies for anything I got wrong) is "Computer Architecture: A Quantitative Approach" by Hennessy and Patterson. Very readable and amazingly comprehensive.

    58. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      You fire those two people for not doing their jobs.

    59. Re:Advantages over just adding more FPUs? by smallfries · · Score: 1

      I bought Hennessy and Patterson as an undergrad textbook for an Architecture course many moons ago. Brilliant book. Your predictions seem very reasonable - "medium" numbers of simple cores will probably provide more throughput than small numbers of complex cores at a given power budget.

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    60. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 0

      Haha... yeah that would extremely stupid. I don't even know where to begin to explain it. There are so many reasons why.

      A single ray has serial execution. Serial execution is the fastest on a CPU. CPU's are getting so much cores that in a few years time they will beat the GPU at parallel execution as well... Then each time a ray bounces it is checked against a massive texture and geometry database. Imagine hdd to RAM to CPU to GPU RAM to GPU to RAM to CPU to the graphics framebuffer.

      Then we are heaving stuff like pure calculations that do not have to acces an entire database like fluid animation, digital molecular matter and other physics stuff and the power you save from not wasting your rays in the GPU could be spend on the GPU instead, which executes faster with GPGPU's.

      Given the fact that realtime interactive recursive raytracing is something that is only possible in 3-5 years time, anyone that says that raytraced games should rendered on a GPU is a complete moron. This is not a flaimebait post, this is just a pure fact.

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    61. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      No, I'd rather blame the distros for *knowingly* shipping buggy code. Oh well, cant expect quality from free stuff...

    62. Re:Advantages over just adding more FPUs? by drinkypoo · · Score: 1

      Increasing the number of functional units per core runs into diminishing returns quickly as keeping all of them fully fed requires lots of implicit parallelism in the program.

      Yes, that's why I said Having more cores with the same number of functional units demands the use of a high number of processes and/or threads for maximum utilization, so a processor with a similar number of functional units but segregated into more cores is going to be suitable for different workloads than what you can buy right now. So actually, I understood everything you said already, and your entire comment was a big jerkoff waste of time. Why don't you read it next time instead of getting your panties bunched? Then you can save yourself a lot of wasted time.

      --
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    63. Re:Advantages over just adding more FPUs? by smallfries · · Score: 1

      Yes. Well done, and that's why I said This is simplistic and wrong... While it is true that having more cores requires more threads/processes to achieve high utilisation it is not necessarily true that having fewer cores with more functional units per core allows high utilisation across workloads with few thread.

      In particular your claim that but segregated into more cores is going to be suitable for different workloads is wrong.

      Ironic, eh?

      --
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    64. Re:Advantages over just adding more FPUs? by scruffy · · Score: 1

      Cache coherency should be handled by the programmer, not by the hardware.

      I hope you meant compiler, not the programmer.

    65. Re:Advantages over just adding more FPUs? by X0563511 · · Score: 1

      They don't.

      When is the last time you installed a distro and had Adobe flash installed out-of-the-box? I thought so.

      --
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    66. Re:Advantages over just adding more FPUs? by TheLink · · Score: 1

      > > Cache coherency should be handled by the programmer, not by the hardware.

      > I hope you meant compiler, not the programmer.

      Sounds like everyone wants to make it someone else's problem :).

      I thought Intel and AMD were running out of ideas on what to use their transistors for. Can't the hardware people sit down with the software guys and work out a better way to fix it _together_? Rather than keep shoving the problem at each other... It seems to be a common problem whether your "units" are CPUs or servers or racks or datacenters. While it is mainly a software problem, I'm thinking the CPU bunch can still lend a hand for the "lower levels".

      Or have they given up?

      --
    67. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      A GPU is a perfect match for raytracing - running the same algorithm side by side multiple times. A 1600 shader core could in theory calculate 1600 pixels at the same time. What else is a GPU good at - texture and geometry! Mostly RAM -> GPU directly via DMA, maybe lesser used textures will be paged out to HD, but you should try to have enough memory for the task in my opinion.

      GPUs are also very good at physics.

      Everything you said was wrong, unless you've got CPU and GPU mixed up.

    68. Re:Advantages over just adding more FPUs? by jd2112 · · Score: 1

      Simple: With 48 processors you can run the full Symantec utilities suite and still have a somewhat usable system, at least until the 2011 version is released anyway...

      --
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    69. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      Yes. The whole lineup from K10 and up. It's called the unganged mode of the memory controllers.

    70. Re:Advantages over just adding more FPUs? by Locke2005 · · Score: 1

      A 15% improvement is nothing to sneeze at, but you are right -- you would probably get a better improvement by optimizing your software for locality of reference, and at a much lower cost.

      --
      I've abandoned my search for truth; now I'm just looking for some useful delusions.
    71. Re:Advantages over just adding more FPUs? by Locke2005 · · Score: 1

      Embarassingly parallel problems are embarassingly easy to solve (e.g. Beowulf clusters of cheap PCs). What is really needed is a technique for optimizing highly interdependent parallel processes. I believe these processes are currently frequently I/O bound. meaning the memory controllers and cache schemes still need to catch up with the CPU speed.

      Enforcing cache coherence over 48 CPUs is a non-trivial problem; you run the risk of several processors constantly invalidating each other's cache. dropping your performance to the same as having no cache at all. Ultimately the hardware and software designers need to work hand in hand to acheive optimum performance.

      --
      I've abandoned my search for truth; now I'm just looking for some useful delusions.
    72. Re:Advantages over just adding more FPUs? by Locke2005 · · Score: 1

      We've replaced the race for higher clock speeds (regardless of power consumption) with a race for more cores (regardless of whether or not the memory controllers can keep those cores fed with data). I assume this is a response to the Cell processor, which is designed to do only one thing really well: encoding and decoding of streaming video and audio (which means it processes very predictable small blocks of data really well.) I believe the current quad processors only achieve maximum performance on one core by throttling back the other cores (otherwise power consumption goes through the roof), so there is no way that 16 core chip is going to achieve anything even close to the performance of 16 times the performance of a single core.

      --
      I've abandoned my search for truth; now I'm just looking for some useful delusions.
    73. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      Google EPIC/IA64. The compiler should take care of scheduling... Or google Cell where each SPE has local memory and no cache coherrency towards other SPEs. It is the "easy" way out of scaling. Makes the hardware scalable and fast, but you gain very little in general.

    74. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 1

      Game loop: game mechanics + rendering
      CPU: rendering
      GPU: game mechanics

      What else do you want? A CPU doing fluid animation and the GPU doing the rendering with massive latency? Are you out of your mind?

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    75. Re:Advantages over just adding more FPUs? by V!NCENT · · Score: 0

      Ok let me explain why ray tracing is dead stupid on a GPU: Texture overlay, mega texture/virtual texture is the future. This is streamed from the HDD in realtime while the overal texture set is in RAM. Now what happens with every bounce is that a ray moves across a LOT of textures, even outside of the camera's view, right? So for each bounce one you need to acces the HDD.

      Do the math: 1650x1050 rays times 8 bounces. That is, for each frame, 1,386e7 times hitting the HDD.

      GPGPU work is only usefull if you can send one large amount of data back and forth from the CPU to the GPU and in that timeframe it should have calculated more than the CPU could do in that timeframe. Fluid animation can be easily done on the GPU. 1,386e7 times hitting the HDD is fscking stupid. Imagine the latency!

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    76. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      I'm not saying you're not right (hence I said I wasn't surprised), but the truth is, it's going to be painful to migrate existing software to this. As someone who's ported parallel x86 software to POWER or Alpha can tell you...

      But nobody ever said good scalable parallel code is generally easy.

    77. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      What have you been smoking? Software cache coherency is much slower than hardware supported cache coherency.
      It does make the hardware much more complicated (and harder to verify) - but in most cases it is similar or faster than non coherent hardware.

      As I have been designing and verifying the hardware (rtl level) of several SMP processor to memory controller sub-systems for that last couple years - I damn well know what I am talking about.

      In fact it is near impossible to sell a non hardware coherent multi-core processor chips (like for example an IBM 440 - PLB4 system - IP you can get from Synopsys DesignWare - if you have the right $$ and connections).

      Any processor designer or architect will tell you the same. You sound like a software guys who really does not know what is up.

      How software (and OS) handles coherency (and interacting with hardware) does make a big difference. Often that means knowing the specifics of the hardware implementation.
      For example, one of the cores that I work with - certain Write-Thru coherent ops can thrash either the cache/memory controller and lock out one of the processors for a long time. 1000-20000 clock cycles in some of the assembly test that I have written (designed to verify HW coherency but not at all good for performance).
      Pathological cases like that are to be avoided.
      How the hardware implements Atomic Ops (like lwarx/stwcx) can also mean drastic differences in performance. E.g. can a lock be broken (reservation) or not by another system master.

      The software bringup and os guys come by my cube every so often to find out why this or that does not work (or is real slow).
        Usually we tell them - don't do that or do this instead (yeah those CSR bit or TLB entries really do make a difference (RTFM - CPU programmers manual).

    78. Re:Advantages over just adding more FPUs? by Anonymous Coward · · Score: 0

      Yeah that is what good compilers are for. Software guys just give the compiler hints about what you want to do.
      To optimize a modern three level cache a program needs to requires track of around 100-200 variables to really optimize.
      Often different CPUs will have different quirks.
      e.g. pass a reference to int array instead of an int point in a C function definition (if using arrays). Most compiler will optimize better with the array reference.

      Can tell you how many times I hear software pukes think they know how to write optimized functions (usually badly and full of bugs)/
      Example writing the own arrays implementations instead of using STLs. And doing this before they know that the performance they need from the code (or if its a problem).

      Pre-mature optimization is like pre-mature ejaculation.
      Just makes a embarassing mess!!!

  14. Re:Code Name is Offensive by Threni · · Score: 5, Funny

    > This post is copyrighted by Robert Nelson for the private use of his audience. Any other use of this post or of any pict

    Your sigfile is offensive. What have ye got against the Scots?

  15. Yet another cloud? by Mortiss · · Score: 5, Insightful

    Why is everything called cloud these days? Yet another du jour buzzword. Is this really justified here?

    1. Re:Yet another cloud? by hibiki_r · · Score: 5, Insightful

      When it comes to marketing cliches, when it rains, it pours.

    2. Re:Yet another cloud? by Lord+Ender · · Score: 2, Interesting

      The term "cloud" is over-used, but a 48-core chip is certainly a good match for anyone who uses virtualization, and cloud-style data services are absolutely big users of virtualization.

      Cloud computing is certainly a big deal. I recently explained to my boss that instead of spending weeks going through tickets, bureaucracy, approvals, and procurement to get a server in our own datacenter, we could go to Amazon, type the credit card number, and be up-and-running with a few clicks!

      I don't know if he understood exactly what cloud computing *is*, but he knows it is important and will have a major impact on IT. So when someone mentions the word "cloud" he listens. Marketers are aware of this sort of thing, so they deliberately use these terms as liberally as possible.

      --
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    3. Re:Yet another cloud? by MobileTatsu-NJG · · Score: 1

      Why is everything called cloud these days? Yet another du jour buzzword. Is this really justified here?

      Given that making effective use of these cores would call for engineering code to work with any number of cores, as opposed to just 2, 4, or 8, then yes it is semi-justified, especially if aimed at the server market. I do say 'semi', though, because I partially agree with you about its silliness.

      --

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    4. Re:Yet another cloud? by ArsonSmith · · Score: 5, Funny

      Why can't it just be cloudy?

      sorry.

      --
      Paying taxes to buy civilization is like paying a hooker to buy love.
    5. Re:Yet another cloud? by V!NCENT · · Score: 1

      http://en.wikipedia.org/wiki/File:Cloud_computing_types.svg

      Now imagine you'd have this 'cloud CPU' as your server at home that runs apps that you could acces with Google Chrome OS... Great family server... Or remote X and play Doom3 at work from your netbook.

      Sounds interesting now? ;)

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    6. Re:Yet another cloud? by hazydave · · Score: 1

      They're Intel... they have this buzzword department, and those kiddies have to make a living, too. Remember the Intel Pentium 4 "Netburst" architecture. Nothing whatsoever to do with nets, networking, the internet, etc.... other than the fact Intel Marketroids were trying to convince all the Mundanes (Muggles, to you kiddies) that this CPU would magically make their internet go faster. Yup, that's it.. not the fact you're on a frickin' POTS modem.

      --
      -Dave Haynie
    7. Re:Yet another cloud? by zullnero · · Score: 1

      No, it's just that it's a hot keyword, and a whole lot of people can't be bothered to look up what it really means. And knowing Intel pretty well, their guys most likely know full well what it is, and they took the name as a taunt to anyone who would dare consider distributing workload instead of buying more server hardware and doing it the way that benefits Intel's bottom line.

    8. Re:Yet another cloud? by Voulnet · · Score: 1

      Why can't it just be cloudy?

      sorry.



      I would like to promote your post. How can I do that?
    9. Re:Yet another cloud? by DragonWriter · · Score: 1

      Why is everything called cloud these days? Yet another du jour buzzword. Is this really justified here?

      Sure, as one of the main uses of a 48-core processor, I would expect, is to be able to dynamically provision slices of it as different logical machines, which is what cloud computing is. So calling this a "cloud" processor makes as much sense as calling two different subsets of the Atom line "Netbook" and "Nettop" processors, after the kind of use for which they are intended.

    10. Re:Yet another cloud? by RelliK · · Score: 4, Funny

      I don't have the foggiest idea.

      --
      ___
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    11. Re:Yet another cloud? by nschubach · · Score: 1

      Just wait for Cloud 2.0!

      --
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    12. Re:Yet another cloud? by spencerg83 · · Score: 1

      When it comes to marketing cliches, when it rains, it pours.

      Bring the Rain!©®

    13. Re:Yet another cloud? by Anonymous Coward · · Score: 0

      doom 3 maybe not.

      latency and jitter would be an utter bitch.
      if you were inside your house on gigabit ethernet sure it would work great.

      Remember folks, when dealing with microseconds and nanoseconds, C starts to kick your ass.

    14. Re:Yet another cloud? by hampton · · Score: 1

      Because then it would just be vapor.

    15. Re:Yet another cloud? by Enderandrew · · Score: 1

      Your post is in the cloud. Does that make your post some meta-commentary? Is my post meta-meta?

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    16. Re:Yet another cloud? by lewiscr · · Score: 2, Funny

      I can't wait to run Drizzle on it.

    17. Re:Yet another cloud? by TheRaven64 · · Score: 1

      I always assumed it came from the fact that if burst into flames when you clicked on a flash movie or JavaScript-heavy site on the 'net.

      --
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    18. Re:Yet another cloud? by Anonymous Coward · · Score: 0

      It's a fuzzy concept.

    19. Re:Yet another cloud? by ruiner13 · · Score: 1

      You're all nimbus-iles.

      --

      today is spelling optional day.

    20. Re:Yet another cloud? by Anonymous Coward · · Score: 0

      Too many people brainstorming :-P

    21. Re:Yet another cloud? by dbIII · · Score: 1

      It makes sense here.
      The chip turns into a cloud if you apply power without a heatsink.

    22. Re:Yet another cloud? by ground.zero.612 · · Score: 0

      Why is everything called cloud these days? Yet another du jour buzzword. Is this really justified here?

      Cloudgate?

      --
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    23. Re:Yet another cloud? by Whiteox · · Score: 1

      I like the multi-redundant iCloud

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    24. Re:Yet another cloud? by FreakyGreenLeaky · · Score: 1

      It's like this "ICT" crap. IT wasn't hip enough anymore, so some (marketing, probably) dummy somewhere decided to splice in Communication. It's like they feel the need to give existing technology a fresh coat of paint every few years.

    25. Re:Yet another cloud? by TheLink · · Score: 2, Funny

      Cirrusly?

      --
    26. Re:Yet another cloud? by mpe · · Score: 1

      Cloud computing is certainly a big deal. I recently explained to my boss that instead of spending weeks going through tickets, bureaucracy, approvals, and procurement to get a server in our own datacenter, we could go to Amazon, type the credit card number, and be up-and-running with a few clicks!

      Without any idea where your data actually is or who has access to it...

    27. Re:Yet another cloud? by bullfrawg · · Score: 1
      Over-internet clouds (like Google's) constitute a threat to Intel's business model. Cloud computing says you don't need to buy your own powerful CPU; someone will buy just enough CPU's to support the average load, and you'll rent them when you need them. And you can have your computing finished sooner because of parallelism in the cloud.

      Intel seems to be intentionally muddying the terminology to defend their business model. "Here's a cloud on your desk" says you can have parallelism while owning (and buying) your own CPU.

      As an aside, Intel is right and Google is wrong, IMHO. Most of the money in a CPU is in the development, not in the hardware. And chip manufacturing benefits greatly from scale. If Google makes it so that people don't buy their own CPUs, it will only save money in the short run. The more people rely on Google's Clouds, the more Google will have to pay for each CPU. Meanwhile Intel can sell cheap versions of what Google needs to the consumer. Cut out networking overhead, get a workstation . . . I mean a Cloud on your desk!

      We've seen this pendulum swing before, and it always comes back. Those who want computing have to pay for the development of computers somehow. In a world in which the incremental cost is low to own your personal copy of Intel's (or AMD's or whoever's) Intellectual Property in silicon, the workstation will always win out.

      Until silicon is replaced with something much more expensive.

    28. Re:Yet another cloud? by QuantumRiff · · Score: 1

      Because Cloud Computing signifies the new Paradigm of collaboration in the digital age. It is opening up new avenues of cohesive synergies.

      --

      What are we going to do tonight Brain?
  16. Re:Code Name is Offensive by _merlin · · Score: 0, Offtopic

    Insightful WTF? If you get offended that easily, you'd better:

    1. Not come out from your basement, lest you see something being worth upset over
    2. Go running to mummy so she can make it better
    3. Or grow up
  17. Obligatory by sajuuk · · Score: 1

    Now imagine a beowulf cluster of these things...

  18. Only 48? by Kingrames · · Score: 4, Funny

    Only 48 cores? I'd ask them to double that, but reasonably, 64 cores should be enough for anybody.

    --
    If you can read this, I forgot to post anonymously.
    1. Re:Only 48? by Locke2005 · · Score: 1

      You do know why Asynchronous transfer mode uses 48 byte packets don't you? The advocates of 32 byte and of 64 byte packets could not reach agreement, so they compromised. Perhaps the Intel designers reached a similar accomadation. (As a software engineer, I too am frequently puzzled when hardware engineers do things that are not powers of 2, e.g. the triple channel memory that Intel's socket 1366 chips currently use, forcing you to by DDR RAM in multiples of 3.)

      --
      I've abandoned my search for truth; now I'm just looking for some useful delusions.
    2. Re:Only 48? by yuhong · · Score: 1

      Yea. the APIs of Windows versions prior to Windows 7/Server 2008 R2 used bitfields for processor affinity, meaning that the 64-bit version was limited to 64 logical processors. Which was fine until the 8-core Nehalem-EX came along with hyper-threading too. 8 cores times 2 threads times 4 physical processors equals 64 logical processors. Windows 7 had to introduce new APIs for processor affinity in order to allow more than 64 logical processors.

    3. Re:Only 48? by eabrek · · Score: 1

      SDRAM uses a lot of pins. Four channels would just be too much. That's all.

      In this case, 48 cores is already 2x a normal processor die area. 64 would be too much.

    4. Re:Only 48? by Anonymous Coward · · Score: 0

      Modded you as insightful, but meant to hit Funny. Enjoy the Karma!

    5. Re:Only 48? by Anonymous Coward · · Score: 0

      Only 48 cores? I'd ask them to double that, but reasonably, 64 cores should be enough for anybody.

      "640k should be enough for anybody..." - Bill Gates, 1981

    6. Re:Only 48? by Anonymous Coward · · Score: 0

      What was that? 640 Kb should be enough for anybody?
      O'h... 64 CORES...
      Same answer though ;)

  19. Idle benchmarks by Colin+Smith · · Score: 4, Insightful

    With 48 processors you can have your system 98% idle running your typical application at full speed rather than just 50% or 75% idle as is the norm now.
     

    --
    Deleted
    1. Re:Idle benchmarks by h4rr4r · · Score: 1

      Please tell me where I can find boxes that would run 50% idle for my use. My company would pay handsomely for such CPUs. Current Quad Xeons fail to do this.

    2. Re:Idle benchmarks by olsmeister · · Score: 2

      So would this have saved that guy's ass who spent $1M in electricity running SETI@Home on the school's computers?

    3. Re:Idle benchmarks by Hadlock · · Score: 1

      Your xenons probably underclock themselves to 50% clockspeed when idle. That's 50% right there. My nearly 3 year old core2duo does that, so I would assume your new(ish) xenons do as well.

      --
      moox. for a new generation.
    4. Re:Idle benchmarks by Anonymous Coward · · Score: 0

      Aww... you don't understand. It would be cute if this wasn't slashdot.

    5. Re:Idle benchmarks by mario_grgic · · Score: 1

      Obviously you don't write software for a living. Software always expands to eat up any advances in hardware users might otherwise gain from upgrading to latest technology.

      --
      As the island of our knowledge grows, so does the shore of our ignorance.
    6. Re:Idle benchmarks by ascari · · Score: 1

      Not if you have one of them Dell laptops!

    7. Re:Idle benchmarks by StuartHankins · · Score: 1

      Dual 8-way HP 460C blades are what I use, connected to an EVA4400. They make the quads seem slow... but then again more than half of what I need is I/O. Our production RHEL5 server typically runs at 70% idle with > 300 users and > 400 connections. It's also running a bunch of other services -- CUPS print server, XML server for the DB backend, MySQL server (mostly active in the mornings), Samba server (used lightly), etc etc.

      Same setup on an HP DL380 with dual quad Xenons was 30-40% idle. CPU% from iowait has also been reduced significantly from 40%-60% to a typical 10% under the same or larger load.

    8. Re:Idle benchmarks by afidel · · Score: 1

      You should try the 685C with 4x hex core Istanbul's with the FusionIO module in the first mezzanine slot, of course for ~$50k I would hope it's blazing fast =) Personally all my current purchases are Dl380 G6 with 2x 5560's and 72GB's of ram, looking to 144GB next year when the price on 8GB DIMM's come out of the stratosphere.

      --
      There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
    9. Re:Idle benchmarks by StuartHankins · · Score: 1

      Those sound nice -- I wish I had a load that was CPU bound to test them -- although they are considerably more than what I'm paying for the dual 8-way 460c's with (8? 16? GB RAM I forget how the last few were bundled). I get them for around $5k each which is practically nothing (compared to the $12-15K we spent on DL380's and the huge expense of the MSA30's only 5 years ago). The memory costs the most, so while we still have slots in the cabinet available, we will probably buy blades then go back and consolidate / upgrade memory.

      We just emptied an entire colo rack and moved all the DL320's / 360's / 380's and accompanying MSA30's to a handful of blades... and they seem to run better as VM's under ESX.

      On a couple of servers we haven't been able to test them as VM's and because they're critical to our business we may not take that chance. For only $5K each it's probably not worth messing with.

    10. Re:Idle benchmarks by afidel · · Score: 1

      The FusionIO card's good for ~120k IOPS, about the same as my entire maxed 220 drive array =)

      --
      There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
    11. Re:Idle benchmarks by Anonymous Coward · · Score: 0

      And why not 100 so you can have a true 99% idle time? Tilera's got you covered. http://www.internetnews.com/hardware/article.php/3845421

    12. Re:Idle benchmarks by hey! · · Score: 1

      Well, I think of this way. Suppose I needed a size 22 shoe and there is no such thing manufactured. I might decide to buy two pairs of size 11, but I'd still have to go barefoot despite having enough shoe *in total*.

      --
      Post may contain irony: discontinue use if experiencing mood swings, nausea or elevated blood pressure.
    13. Re:Idle benchmarks by mb1 · · Score: 1

      Nope... he would've had waaay more buckets in the alien lottery, though :)

    14. Re:Idle benchmarks by Anonymous Coward · · Score: 0

      Well, I think of this way. Suppose I needed a size 22 shoe and there is no such thing manufactured. I might decide to buy two pairs of size 11, but I'd still have to go barefoot despite having enough shoe *in total*.

      Well duh! You just cut your foot in half before walking and rejoin the two parts when you reach your destination.

  20. Re:Code Name is Offensive by girlintraining · · Score: 0, Troll

    Intel an American company, with the American economy in the shape it's in, I am offended at the codename Bangalore.

    First, I agree with you completely. That said, if the processor core is anything like the city it's named for...a 48 core processor on a mesh topology is a good digital analogy to Bangalore -- it is the 3rd most populous urban area in India. It'll also smell horrible, the electrons will be subject to depraved working conditions, and they'll be paid crap for their work, etc. Despite it being a so-called "economic powerhouse", only about 60k of its inhabitants have more than US $1 million net worth. It has over 5.8 million people living there. It makes the wage gap in this country look postively equalitarian.

    --
    #fuckbeta #iamslashdot #dicemustdie
  21. Re:Code Name is Offensive by sexconker · · Score: 2, Funny

    What have ye got against the Scots?

    Damn Scots!
    They ruined Scotland!

  22. Re:Code Name is Offensive by Monkeedude1212 · · Score: 2, Funny

    Does the fact that none* of the Apple Operating system names are of animals not native to America?

    *After 5.1, which is "Kodiak" - which can be found in Alaska.
    5.2 Mac OS X v10.0 "Cheetah"
    5.3 Mac OS X v10.1 "Puma"
    5.4 Mac OS X v10.2 "Jaguar"
    5.5 Mac OS X v10.3 "Panther"
    5.6 Mac OS X v10.4 "Tiger"
    5.7 Mac OS X v10.5 "Leopard"
    5.8 Mac OS X v10.6 "Snow Leopard

  23. Obligatory by cowtamer · · Score: 1

    Imagine a Beowulf Cluster of These !!

  24. Great cost savings by joeflies · · Score: 5, Funny

    because now school administrators only have to install SETI@HOME on 100 48-core computers instead of 5000 standard computers.

    1. Re:Great cost savings by n5yat · · Score: 0

      But how much will the power cost the school district? :^)

    2. Re:Great cost savings by topcoder · · Score: 1

      More precisely 104.1666... 48-core computers :)

    3. Re:Great cost savings by HRbnjR · · Score: 2, Funny

      This is an Intel chip we are talking about here... you can just round off that result ;)

  25. Re:Code Name is Offensive by Anonymous Coward · · Score: 1, Funny

    With a code name like "Bangalore", I would expect it to be a RISC based CPU that's very slow, requires instructions to be repeated and confirmed, and late to service any interrupts.

  26. Re:Meh. I'm holding out for a kilocore. by stakovahflow · · Score: 2, Funny

    Manticore. Mmm. Manticore... Jessica Alba? I'll cast my vote for manticore any day of the week with Jessica Alba in there... [Dark Angel (Comic/Show) references? Yes, I went there... I'll do it again, too!] Personally, though, I think 48 cores in one proc are enough to float my boat... Then, too, so could Ms. Alba... --Stak

    --
    Holy happy hippy crap!
  27. Re:Code Name is Offensive by jcnnghm · · Score: 1

    How awful of them to use the name of San Fransisco's sister city, the "Silicon Valley" of India, as a product codename. Were you equally offended when Ibex Peak, Tylersburg, Alviso, Calistoga, Lakeport, Broadwater, Eaglelake, Crestline and Cantiga were used as codenames?

      You don't need to get your panties in a twist over this. Although it is worth mentioning that it makes you look like a racist when you assume that an innocuous naming decision is some form of racial bigotry or social commentary.

    --
    You don't make the poor richer by making the rich poorer. - Winston Churchill
  28. So ... by Anonymous Coward · · Score: 1

    So, what operating system are designed to take advantage of that many processors? Also, Is it just me or will this make microsoft per core licence policies really expensive?

    1. Re:So ... by Avtuunaaja · · Score: 2, Informative

      Linux can handle 4096 cores without trouble in the main kernel tree, with support for much larger images already existing in trees forked by people who actually need such things.

    2. Re:So ... by Nadaka · · Score: 2, Funny

      All of them except windows.

    3. Re:So ... by Anonymous Coward · · Score: 0

      Linux does only supports "coherent" SMP. These processors have no memory cache coherency. Linux wont work on these processors.

    4. Re:So ... by chill · · Score: 1

      It isn't that Windows can't run on it, it is that there are only 5 or 6 companies in the world that could afford the per-core pricing on Microsoft's products at that level.

      --
      Learning HOW to think is more important than learning WHAT to think.
    5. Re:So ... by TheRaven64 · · Score: 3, Informative

      Ugh, I hate seeing this repeated so often. The 4096-processor SGI machines that Linux works on run 'with the main tree' are clusters. They run a separate instance of Linux on each node and have some very complex hardware managing cache coherency between them. Architecturally, they are nothing like a standard SMP system.

      --
      I am TheRaven on Soylent News
    6. Re:So ... by Anonymous Coward · · Score: 0

      So, what operating system are designed to take advantage of that many processors?

      These days? Just about all of them.

      Also, Is it just me or will this make microsoft per core licence policies really expensive?

      Only for people who license software from Microsoft, so yes, it's just you.

    7. Re:So ... by hlge · · Score: 1

      OpenSolaris comes to mind, Sun have a long history of building systems with > 48 cores that scales well. A UltraSparc T2 based T5440 would give you 256 HW threads to play with.

    8. Re:So ... by afidel · · Score: 1

      Uh, unlike say Oracle MS has standardized on per socket licensing. When we bought our ERP system in mid-2006 we got Oracle Enterprise for less per socket than MS was willing to match for SQL Enterprise. Today those same licenses will only get us one Nehalem EX because they are per core whereas the MS licenses would get us 4x as many cores. It still wouldn't help as SQL Server has too many conditions where tables get locked so concurrency is lower but theoretically we should be able to get more out of the MS licenses.

      --
      There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
    9. Re:So ... by walshy007 · · Score: 1

      Architecturally, they are nothing like a standard SMP system.

      Neither are typical multicore setups these days, long gone are the days when it was just a few processors sharing a front-side bus. Modern multicore setups can be thought of as a kind of mini-numa. With the various forms of local cache etc. Having multiple multicore chips in an smp setup kind of makes it like a hybrid I guess.

  29. But by Anonymous Coward · · Score: 0

    Can it run Crysis?

    1. Re:But by V!NCENT · · Score: 1

      At about 20-30 fps, according to Intel, with Pixomatic 3 :')

      --
      Here be signatures
  30. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    As the last remaining operational Soong type android, I am offended by the name Bang-A-Lore.

    At least they didn't name it Bangkok.

  31. Hmm... by Anonymous Coward · · Score: 0

    ....But can it run Crysis....

  32. Synergy! by HRbnjR · · Score: 5, Funny

    This new Cloud processor should create synergies with my SOA Portal system and allow me to deploy Enterprise B2B Push based Web 2.0 technologies!

    1. Re:Synergy! by cyber-vandal · · Score: 1

      If this isn't Score: 5, Funny by the time I wake up tomorrow I will be most disappointed.

    2. Re:Synergy! by atheistmonk · · Score: 1

      Bingo! inb4whoosh

    3. Re:Synergy! by Anonymous Coward · · Score: 0

      it's sad that that almost makes sense, i think you must have a PHB... or work for General Electric

    4. Re:Synergy! by Anonymous Coward · · Score: 0

      I'll buy some!

    5. Re:Synergy! by Anonymous Coward · · Score: 0

      Cool! Is your company having and IPO anytime soon? This sounds like a sweet thing to invest in!

    6. Re:Synergy! by Anonymous Coward · · Score: 0

      I hope no one is playing the /. buzzword drinking game tonight.

  33. Re:Code Name is Offensive by EdipisReks · · Score: 2, Informative

    Does the fact that none* of the Apple Operating system names are of animals not native to America? *After 5.1, which is "Kodiak" - which can be found in Alaska. 5.2 Mac OS X v10.0 "Cheetah" 5.3 Mac OS X v10.1 "Puma" 5.4 Mac OS X v10.2 "Jaguar" 5.5 Mac OS X v10.3 "Panther" 5.6 Mac OS X v10.4 "Tiger" 5.7 Mac OS X v10.5 "Leopard" 5.8 Mac OS X v10.6 "Snow Leopard

    there are pumas in the American west and in Florida, they are just called Mountain Lions or Cougars or Floida Panthers. same thing.

  34. New GPU for Crysis 2?? by capnhowdy24 · · Score: 1

    Maybe if Nvidia partners with Intel and develops a new GPU out of this, it will handle Crysis 2!

  35. 48 is sufficient for most Ph.D. dissertations. by reporter · · Score: 5, Interesting
    A big market for this chip is the computer-science department of 2nd-tier universities like the University of California-Santa Barbara (UCSB).

    Unlike Stanford University, UCSB lacks the money to build a full-blown multiprocessor system. If UCSB had such a system back in the 1990s, then UCSB would likely have produced as much multiprocessor research as Stanford University.

    This 48-core processor chip, due to the fact that it will eventually be a commercial product mass-produced by the millions of units, will be economically cheap. This chip will enable UCSB to build or buy a cheap multiprocessor system.

    A bunch of graduate students is already salivating at the prospect. They are drooling.

    1. Re:48 is sufficient for most Ph.D. dissertations. by erikscott · · Score: 1

      But if they didn't start two years ago, their stuff won't be publishable by the time it's finished. 48 cores isn't really jack these days. To get on the Top 500 list, you need, very roughly, >2K cores. It's still a big, expensive game to play in, and if your institution doesn't have a pretty big machine, you need to look at the solicitations from the national labs and get some processor-hours there.

    2. Re:48 is sufficient for most Ph.D. dissertations. by kharchenko · · Score: 3, Informative

      >If UCSB had such a system back in the 1990s, then UCSB would likely have produced as much multiprocessor research as Stanford University
      Actually, UCSB had exactly such a system in the 90's, called Meiko: "The Department of Computer Science at UCSB purchased a 64-processor CS-2 in June 1994."

    3. Re:48 is sufficient for most Ph.D. dissertations. by afidel · · Score: 1

      So basically a small cluster that was less powerful then the commercially available CS6400.

      --
      There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
    4. Re:48 is sufficient for most Ph.D. dissertations. by ceoyoyo · · Score: 4, Funny

      Word gets pretty slow when you hit a hundred pages with figures on a Core Duo, but you could always just use LaTeX or a file per chapter. I managed to get my dissertation done with just two cores and my parents managed with a typewriter (although those were masters, not PhDs).

    5. Re:48 is sufficient for most Ph.D. dissertations. by cerberusss · · Score: 2, Interesting

      That's pretty funny.

      Made me think about how I created beautiful reports, using LaTeX, on a simple 100 MHz Pentium machine running Slackware Linux. Now there's Office 2010 coming up, and I'm not sure what the system requirements are, but I'm pretty sure it doesn't do ligatures.

      (Ligatures: when you write "finally", the dot on the i looks funny next to the top of the f, thus LaTeX creates one specially designed character, a ligature, just to make it look good.)

      --
      8 of 13 people found this answer helpful. Did you?
    6. Re:48 is sufficient for most Ph.D. dissertations. by Anonymous Coward · · Score: 1, Informative

      called Meiko

      Meiko was the company who built the machine.

      INMOS begat the Transputer, which begat Meiko and the CS-2, which begat the Elan/Elite interconnect, which begat Quadrics, which begat QsNet & QsNet II (& almost, but not quite, QsNet III), which begat a whole bunch of redundent people in spring 2009 when they finally folded.

    7. Re:48 is sufficient for most Ph.D. dissertations. by Anonymous Coward · · Score: 0

      Yeah, I know there are Word macros to do ligatures (usually font dependent, e.g., with the Wyld medieval font) because it doesn't support them, even if the font specifies the replacements. Appalling, really.

    8. Re:48 is sufficient for most Ph.D. dissertations. by cthulhu11 · · Score: 1

      How many man-weeks did it take you to hammer LaTeX into working, though? Since you write "beautiful" I have to assume that you broke from Knuth's view that the only typeface in use should be the bundled Computer Modern, and thus went through the nightmare of getting postscript fonts to work.

    9. Re:48 is sufficient for most Ph.D. dissertations. by cerberusss · · Score: 1

      Actually, I copied a nicely looking template file from another student, and didn't pay attention to whatever he put in the header. Not sure if it used PostScript fonts.

      --
      8 of 13 people found this answer helpful. Did you?
    10. Re:48 is sufficient for most Ph.D. dissertations. by cthulhu11 · · Score: 1

      Template files don't automagically create a functional software installation.

    11. Re:48 is sufficient for most Ph.D. dissertations. by jamesbulman · · Score: 1

      Word 2010 supports ligatures.

  36. Is there enugh cpu to chipset bandwith to make use by Joe+The+Dragon · · Score: 4, Interesting

    Is there enough cpu to chipset bandwidth to make use of all this cpu power?

  37. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    One could argue a Puma is essentially the same thing as a Cougar/Mountain Lion... Not much in the way of big cats native to the United States.

  38. Re:Code Name is Offensive by Nadaka · · Score: 1

    I thought a bangalore was a man portable explosive, telescoping lance used to take out pill boxes in WW2?

  39. Re:Code Name is Offensive by Monkeedude1212 · · Score: 1

    I refuse to call a Mountain Lion a Puma.

  40. Re:Code Name is Offensive by zach_the_lizard · · Score: 1

    Damn Scots! They ruined Scotland!

    Scotland? What is that? All I know of is Pictland.

    --
    SSC
  41. Sun HAS a 64 thread processor: UltraSPARC T2 by IYagami · · Score: 3, Informative
    1. Re:Sun HAS a 64 thread processor: UltraSPARC T2 by RyuuzakiTetsuya · · Score: 1

      All intel has to do is re implement Hyper Threading in each core.

      48 cores = 96 threads, IIRC.

      --
      Non impediti ratione cogitationus.
    2. Re:Sun HAS a 64 thread processor: UltraSPARC T2 by raftpeople · · Score: 1

      64 threads processed in semi-round-robin fashion is not the same as 48 cores. Different strengths and weaknesses.

    3. Re:Sun HAS a 64 thread processor: UltraSPARC T2 by argent · · Score: 1

      Maybe they can do hyperthreading in software.

      *rimshot*

    4. Re:Sun HAS a 64 thread processor: UltraSPARC T2 by hattig · · Score: 1

      64 threads at 1.6GHz (I believe its available at that speed now), with the round-robin hiding memory access latency (i.e., each thread sees a 200MHz CPU with very low latency memory)? Note these cores are all cache coherent, unlike this 48-core creation.

      This creation is more like a collection of x86 versions of the Cell SPU. Calculations are most optimal on local memory, main memory is highly contended even with 4 channels of DDR3, you want to run bits of algorithms in a chain rather than in parallel.

      If it runs faster than 300MHz, it'll probably outperform the T2. OTOH it's nearly 600mm^2 in size, with the associated cost difference. Also it's not available.

  42. Rather than Larrabee, Intel should've focus on CPU by Taco+Cowboy · · Score: 1

    Intel ought to focus. They need to focus more on CPU rather than Larrabee, which is an obvious mistake.

    --
    Muchas Gracias, Señor Edward Snowden !
  43. Re:Code Name is Offensive by Grendel70 · · Score: 1, Redundant

    And last I checked, Alaska IS part of America.

    --
    Perhaps you mean a different thing than I do when you say "science."
  44. That's nothing, how about 64 cores for $435? by Anonymous Coward · · Score: 1, Informative

    Here's the Wired story.

    http://www.wired.com/gadgetlab/2007/08/64-core-chips-a/

    1. Re:That's nothing, how about 64 cores for $435? by raftpeople · · Score: 1

      I was thinking of that chip when I read this story about Intel, they are probably announcing it now to reduce interest in tile64.

      Unfortunately, the tile64 chip only costs $435 if you order 10,000 (and the dev tools are not cheap). I hope the costs come down quickly because I could make use of one of those.

  45. Re:Code Name is Offensive by snspdaarf · · Score: 2, Funny

    Are you making up imaginary animals again?

    --
    Why, without your clothes, you're naked, Miss Dudley!
  46. Re:Code Name is Offensive by Taco+Cowboy · · Score: 2, Insightful

    Oh please don't go over your head in this.

    India's tech field has improved, but not to the point of design such a chip yet !

    Without the West, India is still a big nothing !

    --
    Muchas Gracias, Señor Edward Snowden !
  47. Helmer by dandart · · Score: 0

    Zomg. Twice as fast as Helmer and probably twice as expensive.

  48. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    At least they didn't name it Bangkok.

    Why? Would it offend yo mama?

  49. Obligatory "Fixed that for you" by powerlord · · Score: 2, Funny

    Imagine a Beowulf Cluster on one of These !!

    There, fixed that for you.

    --
    This space for rent. All reasonable inquiries will be entertained at proprietors discretion.
  50. Just imagine... by Anonymous Coward · · Score: 0

    A beowulf cluster of those!

    (yes, yes, I'm old, but old memes are sticky)

  51. Re:Code Name is Offensive by powerlord · · Score: 5, Funny

    I thought a bangalore was a man portable explosive, telescoping lance used to take out pill boxes in WW2?

    That was an offshoot technology. They've finally got all the bugs ironed out and the CPU is much less prone to "uncontrolled exothermic reactions" then it use to be.

    --
    This space for rent. All reasonable inquiries will be entertained at proprietors discretion.
  52. Anonymous Dunster by Anonymous Coward · · Score: 0

    Maybe Bill Gates will say, "48 cores is more cores than anyone will ever need." Cor blimey.

    1. Re:Anonymous Dunster by Tetsujin · · Score: 1

      Maybe Bill Gates will say, "48 cores is more cores than anyone will ever need." Cor blimey.

      Or maybe in the future he'll be well-known for saying "I never said that 48 cores is all anyone would ever need"...

      --
      Bow-ties are cool.
  53. 48 what cores ? by psergiu · · Score: 0

    48 what cores ?

    Will a chip with 48x 486 CPUs be of any use today ?

    How much L2 cache in each core ? 64Kb ?

    --
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  54. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    Rotate it 45 degrees and add four more

    JJJJ ?

  55. Re:Code Name is Offensive by farlukar · · Score: 3, Insightful

    Without the West, India is still a big nothing !

    And vice versa :p

    --
    Ceci n'est pas une .sig
  56. Sounds like Sinclair's waffer scale intergration. by LWATCDR · · Score: 1

    It does sound a lot like it. Truth is that it is probably a lot more like the old Pentium D packages but still kind of interesting.
    So how many Coretex A8 cores could you fit on one of these?

    --
    See my blog http://ilovecookes.blogspot.com/ for light hearted technical information.
  57. Re:Is there enugh cpu to chipset bandwith to make by V!NCENT · · Score: 1

    If you need very little data per core but are executing sick calculations, then yes. But probably not anything realistic...

    --
    Here be signatures
  58. Re:Meh. I'm holding out for a kilocore. by farlukar · · Score: 1

    hardcore

    --
    Ceci n'est pas une .sig
  59. Re:Code Name is Offensive by powerlord · · Score: 2, Insightful

    One could argue a Puma is essentially the same thing as a Cougar/Mountain Lion... Not much in the way of big cats native to the United States.

    True. We don't have many BIG cats in the U.S. ... just a lot of FAT cats (greater concentrations can be found in the vicinity of State Capitols and Washington D.C.).

    --
    This space for rent. All reasonable inquiries will be entertained at proprietors discretion.
  60. Re:Code Name is Offensive by Sigilium · · Score: 2, Funny

    It's like this: It's hot and loud and there's so many cores.

    As in The Big Bang Theory season 3 episode 4: "I don't want to go to India. It's hot and loud and there's so many people. You have no idea, they're everywhere."

  61. Re:Code Name is Offensive by Tetsujin · · Score: 1

    Intel an American company, with the American economy in the shape it's in, I am offended at the codename Bangalore.

    As the last remaining operational Soong type android, I am offended by the name Bang-A-Lore.

    So you're B4, then?

    Well, I guess it was several years ago that you were known as B4... What's the name you're using these days... "Pryor", isn't it?

    --
    Bow-ties are cool.
  62. Mummy? by Tetsujin · · Score: 2, Funny

    Insightful WTF? If you get offended that easily, you'd better:

    1. Not come out from your basement, lest you see something being worth upset over
    2. Go running to mummy so she can make it better

    Mummy?

    Are you my mummy?

    Mummm-myyy...

    --
    Bow-ties are cool.
    1. Re:Mummy? by Zordak · · Score: 1

      That was okay, but "Blink" was scarier.

      --

      Today's Sesame Street was brought to you by the number e.
    2. Re:Mummy? by Carewolf · · Score: 1

      Insightful WTF? If you get offended that easily, you'd better:

      1. Not come out from your basement, lest you see something being worth upset over
      2. Go running to mummy so she can make it better

      Mummy?
      Are you my mummy?
      Mummm-myyy...

      If he lives in his mothers basement and has a gasmask permanently fused to his face, I think he has issues.

  63. Re:Is there enugh cpu to chipset bandwith to make by Kjella · · Score: 1

    Well, the current solutions don't seem bandwidth starved, looking at the dual-channel vs triple-channel Nehalems. With a setup like that you could probably do multiple memory controllers and NUMA too, if you needed so I imagine there'll be enough.

    --
    Live today, because you never know what tomorrow brings
  64. Re:Code Name is Offensive by clbyjack81 · · Score: 2, Funny

    I refuse to call a Mountain Lion a Puma.

    Just don't call a Warthog a Puma. Sarge doesn't like that.

    --
    Cole's Axiom: The sum of the intelligence on the planet is a constant. The population is growing.
  65. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    No, that was Bangawhore.

  66. Re:Code Name is Offensive by MobileTatsu-NJG · · Score: 1

    So you're B4, then?

    I am 1D-10-T. Legend has it I was named after one of America's most notable Kings.

    --

    "I like to lick butts!" by MobileTatsu-NJG (#32700246) (Score:5, Informative)

  67. Just in time... by cmeans · · Score: 1

    for Windows 8!

  68. lazy by trb · · Score: 1
    1. fabricate x86 silicon wafer
    2. don't bother slicing it up into separate chips
    3. profit
  69. Re:Code Name is Offensive by DragonWriter · · Score: 1

    there are pumas in the American west and in Florida, they are just called Mountain Lions or Cougars or Floida Panthers. same thing.

    Jaguars are also found in the American southwest.

  70. Re:Code Name is Offensive by naveenkumar.s · · Score: 1

    they'll be paid crap for their work, etc. Despite it being a so-called "economic powerhouse", only about 60k of its inhabitants have more than US $1 million net worth. It has over 5.8 million people living there. It makes the wage gap in this country look postively equalitarian.

    Let me introduce something for you... Purchasing Power Parity. I hope you are merely making an observation and not being judgmental. If the latter, I should point out that more people are moving in to the middle-class than ever before. Places in South America and the Near East probably have a wider gap, but what's the point in fixating on one little metric.

  71. Re:Meh. I'm holding out for a kilocore. by Anonymous Coward · · Score: 0

    Sounds like a Transformer.

    Optimus Prime: What's for dinner?

    Mega Core: Electricity

  72. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    > This post is copyrighted by Robert Nelson for the private use of his audience. Any other use of this post or of any pict

    Your sigfile is offensive. What have ye got against the Scots?

    He feels safe sayin' that from his side o' Hadrian's Wall but as soon as we figure out how to climb over it he's fucked!

  73. Buzzzzzzzzword! by Quiet_Desperation · · Score: 1

    Single-chip Cloud Computer

    Wow. That actually caused physical pain in my frontal lobe. Way to live the corporate buzzword stereotype, Intel.

    1. Re:Buzzzzzzzzword! by Anonymous Coward · · Score: 0

      The brain cannot sense pain inside itself, so I think you are lying.

  74. Re:Sounds like Sinclair's waffer scale intergratio by eabrek · · Score: 2, Informative

    "ARM states that the Cortex-A8 occupies up to 3 mm when fabricated in a 65 nm process." (Source).

    Each dual core "tile" is 3mm^2. So only 1 per tile, or 24.

  75. The only way it could have been called "Bangalore" by Anonymous Coward · · Score: 1, Funny

    Is if some of the cores are only allowed to perform menial tasks (they were born that way) and the rest of the cores will only do something if you slip them a little cash. Oh, and code with comments doesn't run.

  76. Catching up by pckl300 · · Score: 1

    When combined, the 48 cores approach the processing power of one i7...

    --
    In the beginning, there was null.
  77. Don't forget. by jonaskoelker · · Score: 1

    Don't forget to leverage turn-key best-of-breed uhh... consumer-focused... enterprise social matrix uh... what are we selling again?

  78. Re:Code Name is Offensive by Penguin+Follower · · Score: 1

    +1 Awesome, Red vs. Blue reference :D

  79. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    anyway it's in Gaelic: Bang Galore, more bangs for your buck

  80. It could just be... by jonaskoelker · · Score: 1

    Well, it could just be that Intel wants to sell a really, really big e-peen to business decision makers ;-)

    (You know, the ones with short, pointy hair)

  81. Not the same thing by Sycraft-fu · · Score: 3, Informative

    Sun's processors are heavily multi-threaded per core. It is an 8 core CPU where each core can handle 8 threads in hardware. Intel's solution is 48 separate cores, doesn't say how many threads per core.

    The difference? Well lots of threads on one core leads to that core being well used. Ideally, you can have it such that all its execution units are always full, it is working to 100% capacity. However it leads to slower execution per thread, since the threads are sharing a core and competing for resources.

    Something like Sun's solution would be good for servers, if you have a lot of processes and you want to avoid the context switching penalty you get form going back and forth, but no process really uses all that much power. Web servers with lots of scripts and DB access and such would probably benefit from it quite a lot.

    However it wouldn't be so useful for a program that tosses out multiple threads to get more power. Like say you have a 3D rendering engine and it has 4 rendering threads. If all those threads got assigned to one core, well it would run little faster than a single thread running on that core. What you want is each thread on its own core to give you, ideally, a 4x speed increase over a single thread.

    So in general, with Intel's chips you see not a lot of thread per core. 1 and 2 are all they've had so far (P4s and Core i7s are 2 threads per core, Core 2s are 1 thread per core). They also have features such as the ability for a single core to boost its clock speed if the others are not being used much, to get more performance for one thread and still stay in the thermal spec. These are generally desktop or workstation oriented features. You aren't necessarily running many different apps that need power, you are running one or maybe two apps that need power.

    As for this, well I don't know what they are targeting, or how many threads/core it supports.

    1. Re:Not the same thing by TheRaven64 · · Score: 1

      However it wouldn't be so useful for a program that tosses out multiple threads to get more power. Like say you have a 3D rendering engine and it has 4 rendering threads

      Check out the Erlang benchmarks on the T1. The performance scales just short of linearly with the number of Erlang processes they spawn. The T1 and T2 don't slow down when more than one thread is working, they just don't run as fast individually as competing chips. Sun's SMT is very different from IBM's. If you're putting 48 complete cores on one die, you probably won't be able to get as many functional units as the T1/T2, where 4 or 8 contexts share fetch, decode, and issue pipeline stages (and are overlapped on the execute stages so there's rarely any contention. FPU is the one exception, so if you average more than about one FPU instruction per 3-4 instructions in all of your threads on the T2 then you may see some slowdown).

      There's a reason IBM isn't putting more than 8 cores on the POWER7: there isn't enough space on an affordable die for any more without sacrificing (and affordable is used in a very loose sense when it comes to the POWER7). Typically, you have to sacrifice one or more of cache size, execution units, or speculative execution (out-of-order / branch prediction). The T2 has no out-of-order execution, and compensates for this by spreading instructions apart (issuing one from each context in turn) so one has usually finished by the time the next one needs its data, reducing the dependencies. Larabee removed some execution units, so everything except vector arithmetic is slow. Most GPUs lack branch prediction, so if you have more than one branch every few hundred instructions performance is poor (typical code has one branch every 7 instructions).

      --
      I am TheRaven on Soylent News
    2. Re:Not the same thing by Anonymous Coward · · Score: 0

      "Like say you have a 3D rendering engine and it has 4 rendering threads. If all those threads got assigned to one core, well it would run little faster than a single thread running on that core"

      How is it possible for a multithreaded render to be faster than a single threaded render ON THE SAME CORE?

    3. Re:Not the same thing by Anonymous Coward · · Score: 0

      Are there any information about scaling of other functional systems on an T1 or T2 besides Erlang? Do you know if the IBMs SMT is still of CMT variety (not the AMDs CMT) from the RS64 time?

  82. Stupid questions by rumblin'rabbit · · Score: 1

    How many gigaflops will this sucker do? How is parallel programming done? Is it standard multi-threading, or something else? What's the expected cost of these babies? Bottom line me here.

    1. Re:Stupid questions by maraist · · Score: 1

      No cache coherence so dont get your hopes up for general computing. though its probably not as bad as the PS3 chip with no virtual memory in the multi-core processing part.(forget the name.. aaaaarg)

      --
      -Michael
    2. Re:Stupid questions by TheThiefMaster · · Score: 1

      PS3's annoying things are called SPUs.

  83. Re:Code Name is Offensive by TheRaven64 · · Score: 2, Informative

    Not sure why you think that. Intel's owes its current existence to their Israeli team, which was the only group producing working designs with a usable power envelope while the American design team was following the US automobile industry in concept. Most Intel products are codenamed based on a location near the design team. Several recent Intel chipsets have been designed in east Asia. Plugging 48 x86 cores onto a die, when you have access to Intel's designs, is not a particularly hard task compared to chipset design, so I wouldn't be at all surprised if one of their Indian teams did it. There are a billion people in India; it's not hard to imagine that among that population there are some who are at least as competent as any of Intel's American designers.

    --
    I am TheRaven on Soylent News
  84. Re:Meh. I'm holding out for a kilocore. by norminator · · Score: 1

    64 cores ought to be enough for anyone.

  85. Awesome by Anonymous Coward · · Score: 0

    I'd be more impressed by a 6GHz quad-core though.

  86. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    But they can see Russia from their houses!

  87. Re:Code Name is Offensive by nullchar · · Score: 1, Informative

    I thought it was ID10T (eye dee ten tee).

  88. Re:Code Name is Offensive by kaini · · Score: 0

    What have ye got against the Scots?

    Damn Scots! They ruined Scotland!

    No true Scotsman would say that!

    --
    please restate bitrate in libraries of congress per hour.
  89. why use a GPU??? by logicassasin · · Score: 1

    If something like this works like I think it should, there probably wouldn't be a need for a GPU at all, just a rasterizer. Everything would be done on the host CPU, likely with power to spare.

    --
    Fifty watts per channel, baby cakes.
  90. Re:Is there enugh cpu to chipset bandwith to make by Angst+Badger · · Score: 3, Interesting

    Is there enough cpu to chipset bandwidth to make use of all this cpu power?

    That's really going to depend on the intended use. And on whether the intended use involves problems that a) can be efficiently parallelized, and more importantly, b) actually have been efficiently parallelized. But unless each core gets its own memory bus and its own dedicated memory with its own cache, I rather expect that the only things that are going to be parallelized to their maximum potential are wait states. All that said, it will still probably run faster than a two- or four-core CPU for many tasks, but it won't be running 48 times faster. I would not, however, refuse a manufacturer's sample if one was handed to me. ;)

    On the positive side, if this beast actually makes it to market, it might help spur the development of new parallel software.

    --
    Proud member of the Weirdo-American community.
  91. Re:Code Name is Offensive by Anonymous Coward · · Score: 1, Informative

    ...which is why he pointed it out as an exception to his statement. You have bad reading comprehension.

  92. Re:Code Name is Offensive by sconeu · · Score: 1

    That's why they changed the name. Whenever they tried to get it to do something, it would only follow a script, even if the program didn't follow that same script.

    --
    General Relativity: Space-time tells matter where to go; Matter tells space-time what shape to be.
  93. Completely new processor design by nurb432 · · Score: 1

    That uses existing IA86 core technology..

    Marketing guys are smoking too much 'cloud' i think.

    --
    ---- Booth was a patriot ----
  94. Re:Code Name is Offensive by mgblst · · Score: 1

    We are not talking about hair color, or birthdays. People aren't born with the ability to build chips, it takes many years of uni (which india has), as well as many years working in a CPU design company (which india doesn't have).

  95. Obligatory by mhajicek · · Score: 0

    640 cores aught to be enough for anybody!

  96. Re:Code Name is Offensive by Jah-Wren+Ryel · · Score: 1

    Damn Scots!
    They ruined Scotland!

    If it's not scottish, it's crrrrrrrap!

    --
    When information is power, privacy is freedom.
  97. Re:Rather than Larrabee, Intel should've focus on by Anonymous Coward · · Score: 0

    I would actually say the opposite: Intel needs to focus *MORE* on something Larrabee like than less. AMD bought ATI for that exact reason, and honestly ATM it seems to be the one division where AMD is staying competitive or ahead of the competition.

  98. NUMA vs SMP by mario_grgic · · Score: 2, Interesting

    In my experience Windows 7 64 bit is noticeably faster with NUMA configuration (Windows experience index is significantly higher because of improved memory throughput) and majority of application also run up to 10 % faster.

    I don't know if this is because of Nehalem Xeon CPUs having faster access to CPU local memory in NUMA configuration or if windows is also optimized for this?

    --
    As the island of our knowledge grows, so does the shore of our ignorance.
    1. Re:NUMA vs SMP by walshy007 · · Score: 1

      numa always wins when you scale things up enough, smp doesn't scale well above a certain point (4-8 processors) it could be argued that because of local caches that the current multi core cpu's are a kind of mini numa design themselves.

  99. Re:Code Name is Offensive by gandhi_2 · · Score: 1

    Bangalore torpedoes are still in use today, and one of the most effective man-portable wire breaching techniques.

    They are basically 3ish-foot long pipe bombs filled with Comp B, which can be connected end-to-end creating a pipeline bomb to/thru the target area. Great for clearing a lane thru mined/wired obstacles.

  100. Re:Meh. I'm holding out for a kilocore. by Curate · · Score: 5, Funny

    I think it's more likely we'll see kibicores and mebicores.

  101. Beurhg by Karem+Lore · · Score: 1

    Wake me up when the processor is $100

    --
    When all is said and done, nothing changes...
  102. Re:Sounds like Sinclair's waffer scale intergratio by sznupi · · Score: 2, Informative

    The 48-core chip that Intel demonstrated is 45nm!

    Also, Cortex-A9: "For 2000 DMIPS of performance when designed in a TSMC 65 nanometer (nm) generic process the core logic costs less than 1.5 mm^2 of silicon." ( http://www.arm.com/products/CPUs/ARMCortex-A9SingleCore.html ) So it seems "up to 3 mm^2" in your quote really means "up to" (and for a much older core of course, when it was just launching 4 years ago)

    And Cortex-A9 "consumes less than 250mW per core"...

    --
    One that hath name thou can not otter
  103. Re:Code Name is Offensive by Sulphur · · Score: 1

    Do you mean bangalore torpedo?

  104. Re:Code Name is Offensive by treeves · · Score: 1
    --
    ...the future crusty old bastards are already drinking the Kool-Aid.
  105. Re:And yet it's still... by ascari · · Score: 1

    48 cores. Duuude.

  106. Re:Code Name is Offensive by ravenshrike · · Score: 1

    Look, just because Tina Fey had a picture of Vladivostok painted onto her windows is not a reason to insult the rest of Alaskans.

  107. Re:Code Name is Offensive by hlge · · Score: 1

    Bangalore > lots of cheep labor for simple tasks (Simple x86 core) -> code name makes perfect sense

  108. Re:Code Name is Offensive by Moonrazor · · Score: 1

    Pictland? What is that? All I know of is Caledonia.

    --
    Burn the land and boil the sea........
  109. Re:Meh. I'm holding out for a kilocore. by Anonymous Coward · · Score: 0

    It took you some release cycles too long to be original: MegaCore.

  110. Re:Code Name is Offensive by Foredecker · · Score: 1

    Man, if that offends you, you must be offended quite often. Do you really think its that important that you should be offended? Do you think things are so fragile that a mere product code name is important?

    --
    Jibe!
  111. Re:Meh. I'm holding out for a kilocore. by Anonymous Coward · · Score: 0

    If one fails, does that make it a mebinotcore?

  112. thrashtastic by funkboy · · Score: 1

    At this level of parallelism, it seems to me that the routing/switching and data management between the cores will become far more important than the raw number of cores or how fast each core is. Very similar to cluster computing in that the topology of the cluster (and the interconnect bandwidth & latency) is just as important as the power of each individual node.

    Projects like Grand Central Dispatch are a good step in the right direction to making general-purpose computing reasonably multithreaded, but the chip itsself still has to deal with shuffling all that data around. If there's any hope of keeping the pin count within modern package limitations (e.g. socket 1366) then either a solid percentage of the die's real estate will be have to be devoted to interconnect & routing logic, or some serious compromises will have to be made.

    BTW, can anyone explain how this architecture is substantially different from Larabee, which is also a whole mess of x86 cores on one die?

  113. INMOS Transputer was right after all... by Anonymous Coward · · Score: 0

    Imitation *is* the sincerest form of flattery.

  114. Re:Meh. I'm holding out for a kilocore. by jimmydevice · · Score: 1

    When the designers figure out that simple Multi-core architectures with lots of external/internal bandwidth and fixed partitioning of processes can we finally get on with the move from the cpu centric / one processor mindset.

  115. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    OS X v10.7 "Chupa-Thingy"

  116. Re:And yet it's still... by Anonymous Coward · · Score: 1, Insightful

    No, mentioning a bad architecture, like Itanium, is not going to put a dent into that argument. ^^

    Similarly, just repeatedly calling the x86 architecture "crappy" does not actually make it "crappy." Despite having compatible instruction sets, the architecture behind Intel's modern processors has practically nothing else in common with legacy chips like the 386 or 486. Why don't you actually tell us what makes this 48-core processor so much worse than anything else out there?

    Or would that require you to stop being a jackass?

  117. This sounds REMARKABLY like IBM POWER by zevans · · Score: 1

    ...doesn't it? Multiple cores, strongly interconnected? What have Intel done that is new here?

    --
    "... and more and more now there are all kinds of electronic goodies available" -- Pink Floyd 1972
  118. Re:And yet it's still... by afidel · · Score: 2, Insightful

    x86-64 is actually a pretty good architecture with a decent tradeoff between registers and instruction compactness. Since the instructions are compact you can fit more of them per RAM clock cycle which is an advantage vs a pure RISC architecture which is why POWER has come much more towards the CISC side of thing then x86 has gone towards RISC (externally, internally it's pretty much a RISC machine).

    --
    There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
  119. 2K cores by symbolset · · Score: 2, Insightful

    It's probably rude to point this out, but 2k cores is roughly 43 of these. That's 11 4 socket servers. Less than 1/2 a rack using blades. That's pretty small for a top500 system.

    --
    Help stamp out iliturcy.
    1. Re:2K cores by totally+bogus+dude · · Score: 2, Insightful

      It's probably even ruder to point this out, but by the time these 48-core processors are commercially available and affordable by institutions with lesser budgets, those with large budgets will be on to bigger and better things. At the very least, if these procs are the best way to do things, then the larger institutions will simply have a dozen racks full of blades with these processors, so the rack or two others can afford will still be way behind the curve.

  120. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    Intel likes to hire a bunch of fresh kids from school to design their processors. I accidentally walked into a group of microcode developers working in JF3 a few years ago. Nobody was over 25. You get what you pay for. The Jew designed core was smaller and faster. Yanks need to drink less and stay away from antidepressants. Depression in a natural state. Get Over IT.

  121. RAM / io by smash · · Score: 1

    now all we need is memory density and IO throughput to catch up. for most server/vm deployments memory and IO are your bottlenecks. Sure, this will be useful in niche markets such as scientific research, but a "cloud" processor it is not... without the IO and RAM to back up all those cores very few people will be able to actually make use of them in a single machine.

    --
    I run: Windows, OS X, Linux, FreeBSD. Just because you have a hammer, doesn't mean everything is a nail.
  122. Re:Code Name is Offensive by Anonymous Coward · · Score: 1, Informative

    Firstly stop being xenophobic.
    Maybe the name is Bangalore because of this?
    http://nextbigfuture.com/2009/12/intel-makes-single-chip-cloud-computer.html
    "This represents the latest achievement from Intel's Tera-scale Computing Research Program. The research was co-led by Intel Labs Bangalore, India, Intel Labs Braunschweig, Germany and Intel Labs researchers in the United States. "
    And Intel is an international company headquartered in the US. Intel gets just 20% of its revenue from the Americas
    http://www.forbes.com/feeds/businesswire/2009/10/13/businesswire130140595.html

    And Bangalore has nothing to do with the current or the previous US recession. India imports more from the US than it exports to the US. Hence the US has a trade surplus with India. The current crisis was caused by reckless behavior by American financial institutions and the American housing bubble and it has affected the rest of the world.

    Stop being so driven by hatred and country sentiments. We all live in this same world, are humans, dependant on each other and deserve respect from all other human beings. Hatred is so 2008.... grow up.

  123. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    Pumas and Jaguars are native to America.

    May be not native to the gringo part of it, but there are plenty of them here at the south of the Equator.

  124. Re:Code Name is Offensive by Whiteox · · Score: 1

    I suppose the Hebrides is naught?

    --
    Don't be apathetic. Procrastinate!
  125. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    It wasn't Robert Nelson. His name was Robert Paulson.

  126. Re:Code Name is Offensive by hey! · · Score: 1

    The experience you speak of is not held by *countries*, but by individuals.

    Remember, India is a very populous country. It has a larger middle class than the US. It has comparable numbers of engineers to the US.

    Now how many of those engineers would have to work on cutting edge design teams, and how long, before enough of them would have the skills to form the core of an all Indian team capable of doing something nobody had tried before? Especially if that wasn't coming up with a new processor design, but rather a way of interconnecting more cores than people thought was practical? That kind of creative work isn't the kind of thing you can parse out to a giant army of engineers. The key insights are probably the product of a small number of engineers, maybe even a single individual.

    --
    Post may contain irony: discontinue use if experiencing mood swings, nausea or elevated blood pressure.
  127. 48-way hyper threading by Anonymous Coward · · Score: 0

    Does this chip have HT? I suspect that Intel, as usual, hide facts about this things. Maybe they "forgot" to tell everyone that the cores was *logical* ones?
    48 physical cores+2x HT for each cores would have been nice though, but they would have marketed it like a 96 processor chip for sure then.

    1. Re:48-way hyper threading by Tim+C · · Score: 1

      Well they aren't marketing any of their consumer grade chips that have HT as 2x the physical core count - for example, when I first installed my Core i7 and checked Task Manager, I was surprised to see 8 graphs - I knew it was a quad-core model, I'd forgotten about HT.

  128. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    Does the fact that none* of the Apple Operating system names are of animals not native to America?

    *After 5.1, which is "Kodiak" - which can be found in Alaska.
    5.2 Mac OS X v10.0 "Cheetah"
    5.3 Mac OS X v10.1 "Puma"

    The cougar (Puma concolor), also known as puma, mountain lion, mountain cat, catamount or panther, depending on the region, is a mammal of the Felidae family, native to the Americas. http://en.wikipedia.org/wiki/Cougar

    5.4 Mac OS X v10.2 "Jaguar"

    The Jaguar (Panthera onca) is a big cat, a feline in the Panthera genus, and is the only Panthera species found in the Americas. http://en.wikipedia.org/wiki/Jaguar

    5.5 Mac OS X v10.3 "Panther"

    See cougar above.

  129. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    If it's not Scottish, it's crap!

  130. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    The cougar, a type of panther, is found in the wild in western north america.

  131. Re:Meh. I'm holding out for a kilocore. by phishtahko · · Score: 1

    ULTRACORE!!!

  132. fuck doing research to figure out new apps by mofag · · Score: 1

    just hand it over now - we'll find uses for it.

  133. Re:Code Name is Offensive by peater · · Score: 1

    Heh, yeah there was this secretary at my workplace in India who had a doc file called "Bangme.doc" which one of us noticed while shoulder surfing. Out of curiosity we opened the document while she wasn't around only to find out that it was a schedule of the partner's Bangalore Meetings. Big big let down.

  134. Re:Code Name is Offensive by mqduck · · Score: 1

    It was called Bangalore to remind you where to call if you need any support for it.

    Perhaps, but it was just as likely to have been named Bangalore to remind you of the people who designed it. (Disclaimer: I don't know if statement is true)

    --
    Property is theft.
  135. Bangalore == Humpalot by FreakyGreenLeaky · · Score: 1

    I'm probably the only one, being married and denied sex, but Bangalore reminds me of Humpalot, Ivana Humpalot.

  136. This sounds a lot like the Transputer by crispytwo · · Score: 1

    In the late '80s a networked computer chip for multiprocessing was created http://en.wikipedia.org/wiki/Transputer

    It was pretty awesome and used C with some libraries or Occam2 as the programming language. You could link up as many of these babies as you would like and they would communicate between themselves for your parallel programs.

    It's nice to see something similar in scale coming into the main stream more/again.

  137. Now with 10 blades! by Anonymous Coward · · Score: 0

    Hey, if it works for Gillette, I say go for it

  138. Re:Code Name is Offensive by cheekyboy · · Score: 1

    Will there be an 11.0 or 10.10 called Pussy Power? or Hello Kitty

    --
    Liberty freedom are no1, not dicks in suits.
  139. Re:Meh. I'm holding out for a kilocore. by jaggeh · · Score: 1

    ULTRACORE!!!

    GODLIKE!

    --
    I would give everything i own for a little bit more.
  140. Code Name is Offensive - this isn't: read please by Anonymous Coward · · Score: 0

    http://slashdot.org/comments.pl?sid=1435180&threshold=-1&commentsort=0&mode=thread&cid=30021114 [slashdot.org] [slashdot.org]

    Per my subject-line: Read that, & get back to us (since you are allegedly a dev mgr. @ MS)... this isn't to "antagonize you", but, rather to help you folks @ MS spot possible problems in Windows VISTA/Windows Server 2008/Windows 7 especially, due to their WFP/NDIS6 firewall design, problems in the local DNS cache client, & in HOSTS files.

    Thanks for your time.

    APK

    P.S.=> I am not sure WHY you've avoided my points, because they are to help "make a better Windows" is all, but I assume because of your being busy. However, your business is making Windows allegedly, so why not take a peek @ something that may point to issues!

    (Definite possibles per:

    1.) ROOTKIT.COM's findings on unhooking the WFP/NDIS6 firewall easier than the older Windows 2000/XP/Server 2003 setup apparently, WITH CODE THE SAID DOES SO NO LESS in the url pointing to it

    2.) Problems in the local DNS Client cache (fails/lags for folks that use "LARGISH" HOSTS files (plenty of us, many 1000's, per Spybot S&D users + folks @ mvps.org (to only name a small few) & even folks like Mr. Oliver Day espouse the use of HOSTS files, finding they make him go faster, AND SAFER, online by far as evidence to it, as well as users who have used a security guide of mine, of which HOSTS are a major part, not seeing any malware intrusions AND GOING FASTER ONLINE TOO)

    3.) MS seemingly intentionally removing the ability to use the smaller & faster 0 based blocking IP address in a HOSTS file (when it was MS who put it into Windows, from 2000 in a SERVICE PACK, not its original OEM CD release distro mind you, & leaving it there clear into VISTA, until 12/09/2008 MS patch tuesday, when it (a good thing) was removed for SOME reason (makes no sense, unless somehow the dual IPv4 + IPv6 setup in VISTA onwards facilitates the need for this, & I do NOT think it does @ this point)

    AND, more...)

    Again, thanks for your time, & I hope this aids MS in "making a better Windows than Windows is", per those points... apk

  141. SIngle chip cloud computer? by Anonymous Coward · · Score: 0

    I'm waiting for Cloud 2.0

  142. Re:Code Name is Offensive by mrboyd · · Score: 2, Informative
    Really? then wtf is that job offer on intel website for a CPU Architect in bangalore for?

    In this position, you will be responsible for architecting advanced client platforms for 2015 and beyond. We are now in the early research and pathfinding for the 2015 generation of CPU products. Our team engages in early architecture analysis, microarchitecture research and/or development, performance and/or power modeling and analysis, including detailed architecture validation versus RTL

    Here's what they do in Bangalore: http://www.intel.com/jobs/india/iidc/index.htm. Seems like some people in India have enough skills to design a CPU.

  143. Re:Code Name is Offensive by R2.0 · · Score: 1

    Haggis and the glottal stop

    --
    "As God is my witness, I thought turkeys could fly." A. Carlson
  144. Re:Code Name is Offensive by CharlyFoxtrot · · Score: 1

    In the hope of staving off further controversy the codename has now been changed to Pussygalore.

    --
    If all else fails, immortality can always be assured by spectacular error.
  145. Re:Meh. I'm holding out for a kilocore. by Forge · · Score: 1

    I like Hardcore. But that may be because of y pr0n bias. I'm shocked to see that nobody has yet asked us to imagine a Beowulf cluster of Hardc... Ouch, stop hitting me.

    --
    --= Isn't it surprising how badly I spell ?
  146. Re:Code Name is Offensive by Anonymous Coward · · Score: 0

    I laughed. +1 funny (no points today, sorry)

  147. Re:Sounds like Sinclair's waffer scale intergratio by eabrek · · Score: 1

    TFA says "Technology: 65nm CMOS Process". Is that a bug in TFA?

  148. Ligatures by AlpineR · · Score: 1

    What happens if you copy some text with ligatures and paste it into a program that doesn't expect them? What happens if you search for "finally" in a document where "fi" was replaced with a ligature?

    1. Re:Ligatures by cerberusss · · Score: 1

      Well, it's really a print feature. The ligature shouldn't appear unless it's actually printed.

      --
      8 of 13 people found this answer helpful. Did you?
  149. Re:Code Name is Offensive by morgen_m · · Score: 2, Informative

    Do you have any idea what you are talking about? Intel,AMD and many other companies design their chips in Bangalore. e.g: Xeon 7400 series by Intel and AMD's competitor to the Xeon, called Opteron were designed in B'lore. Infineon, Cisco, GE and whole lot of other companies have chip designing operations in Bangalore.

  150. Re:Sounds like Sinclair's waffer scale intergratio by hattig · · Score: 1

    Look lower down.

    The top diagram and technology is the older 80-core test-chip - but the article doesn't make it immediately obvious.

    The core in the 48-core chip is around 6mm^2 (excluding L2 and other uncore) on 45nm, at 567mm^2 total area.

    You could fit 4 65nm Cortex A9s in that space. But maybe the x86 core is quad-threaded, like Larrabee's cores.

  151. Re:Is there enugh cpu to chipset bandwith to make by mpe · · Score: 1

    That's really going to depend on the intended use. And on whether the intended use involves problems that a) can be efficiently parallelized, and more importantly, b) actually have been efficiently parallelized.

    There's also the degree to which a task can be effectivly done in parallel (things get interesting when the number of parallel subtasks is greater than the number of execution units, especially where this isn't a multiple of the number of EUs and/or the subtasks are diverse.) which may well vary throughout the task including having to wait until the last of a set of subtasks has finished.
    But unless each core gets its own memory bus and its own dedicated memory with its own cache,

    Which is likely to give issues with memory coherence, "memory" effectivly becoming additional "cache" With a need for a sophisticated MMU to sort things out.

    I rather expect that the only things that are going to be parallelized to their maximum potential are wait states. All that said, it will still probably run faster than a two- or four-core CPU for many tasks, but it won't be running 48 times faster.

    Performance never scales linearly to number of CPU/cores even in an idea situation.

  152. x86? by gravis777 · · Score: 1

    Guess I will wait for AMD to make an x64 version of it. I don't care how many cores you have, I am not going back to 32 bit! Expecially if I have 48 cores, I REALLY want to use more than 3 gig of RAM!

  153. It still isn't reversible computing! by bradbury · · Score: 1

    If one notes from the articles on the architecture Intel is *still* not biting the bullet of reversible computing [1]. There has to be a fair amount of the architecture built into the frequency and voltage management of the chips (not to discuss chip layer layers involving voltage management (I would like to know whether they are doing all the voltage management on-chip or require new power supplies and/or motherboards (meaning one is unlikely to see plug-in replacements of CPUs on desktop/laptop PCs. One could adopt a conspiracy perspective and argue that this is Intel's attempt to redefine the "standard" computing platform and forcing all "modern" users to purchase new computers! (Wouldn't that sell hundreds of millions or billions of chips???)

    1. For those unfamiliar with "reversible computing" it evolved from the work of H. Bremermann, R. Landauer and C. Bennett, largely at IBM in the 1960's and 1970's and pointed out that one could not "destroy" bits without generating heat (Laws of entropy). As a result the only way to do computing without generating wasteful energy consumption (in the form of heat radiated and therefore bumping into the limits of heat dissipation per chip) would be to perform computations reversibly. I.e. you never destroy mass/energy/charge during a computation -- you simply return it to its original state. That is "reversible computatuion". Unfortunately manufacturers like Intel and AMD have not chosen to pursue this aggressively (one would have to believe that there may be some financial motivation behind this). I would tend to view this as pushing existing designs, technologies, instruction sets and limits to their farthest bounds before executing a shift to reversible computing. It may be observed that Eric Drexler, in Nanosystems, Chapter 12, "Nanomechanical Computational Systems" (published in 1992) explained the operation of an atomic scale mechanical gate array that did function as a reversible computational architecture, very much like a "reversible" abacus, because the energy required to reset the calculations was significantly less than that required to erase the matter/energy contained in them.

    So the information is out there -- and the question remains when will manufacturers bite the bullet and transform the entire framework into a reversible one? Now in general one doesn't want to accept the delays of reversing the computation when a simple CLR will do.

  154. Re:Is there enugh cpu to chipset bandwith to make by narcberry · · Score: 1

    In order to achieve the highest efficiency, we keep the same instructions loaded on 47 of the processors, and reserve the full bus for the 48th.

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    Modding me -1 troll doesn't make me wrong.
  155. Re:And yet it's still... by Hurricane78 · · Score: 1

    -1, Troll? Yeah right.

    And yet another “I don’t get the depth of what you said in the slightest, and don’t even want to. Because I have no experience in life and never thought about anything deeply. But this goes against my primitive beliefs that I cling to, to give my weak life meaning. So I disagree and would like to censor”.

    Weak, people... Weak!

    --
    Any sufficiently advanced intelligence is indistinguishable from stupidity.