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https://www.tomshardware.co.uk...

And a quick comparison:
https://www.samsung.com/semico... - 1200TBW
  vs
https://www.intel.com/content/... - 17,520TBW

Optane data density has increased to 32 TB per ruler, you need to catch up.

Because of the unique shape and characteristics of the drive, based on EDSFF, vendors like Supermicro are able to fit 32 Intel “ruler” drives at 32 TB each into a single 1U server, providing up to one petabyte of data per server.

In a world where the consumer that forks over the cash actually owns the device, all devices should expose a JTAG port, and none should be so stupid as to connect it to a Management Engine running secret signed and encrypted firmware that the rightful owner can't change.

Depends on your chip, bios, and motherboard chipsets, but it is possible to modify all of that.
There is no real standard between board makers and BIOS and all the tools are far from user friendly, but if you have the desire, the know-how is out there.

I've reflashed a core i7 to upgrade management engine, both ME in the PCH and MEBX in the EFI bios, and one was a v3 to v9 upgrade to gain features you normally buy like VNC access.
I've patched in ATM to my bios from an OEM that normally charges for that and only for corporate customers.
I've updated and replaced SLIC modules for completely bad reasons.
I've decompiled, modified, recompiled and patched in memory bus and video PCI bootstrap code.
I've even ripped the intel AMT code for LMS-SOL out of one HP Proliant server to patch into an HP compaq pro desktop.

I've even added software to the Minix OS running on the PCH, what you seem to be calling "management engine"

This can be done on award, phoenix, and intel efi bios. On asus, dell, hp, gigabyte, and via boards.

None of this is encrypted and unchangeable. It is signed of course and verified by the previous step of the boot process, but everyone has access to that at the most root level, yes even you (hit control-p during your next boot up), and you can certainly replace all keys to verify against with your own, so long as you also sign with that keypair everything you reflash (modified or not)

It's also not secret

What they're saying is just PR speak, and probably has absolutely nothing to do with the market realities which prompted this decision. The most likely scenario is simply that someone else came into the market with a better product, and ate Intel's lunch. You don't keep making a product when nobody is buying it!

I mean, just take a look at Intel's webpage for Compute Cards; I don't know if this was always the case, but the specs and prices of the offerings on that page right now strongly suggests that they were targeting low-end computing stations. (Which admittedly does make sense when we're talking about point-of-sale terminals and the like.) But maybe their target audience didn't actually want workstations which were so drastically restricted in performance... or at least, not at the prices that Intel wanted to charge.

Of course, with that price bracket, it's also quite plausible that a fair portion of their target audience just went with tablets instead.

Why do I hate Apple so much? Because they are literally raping their fanboy customers. Let's do a comparative breakdown of this so-called "$16k Build" based on NewEgg's prices:
-256GB DDR4 RAM: Around $1,000
-16GB GPU (Radeon VII): $700
-18-core Intel CPU (Intel i9 9980XE): $2,000

Intel's ark says

Memory Specifications
Max Memory Size (dependent on memory type) 128 GB
Memory Types DDR4-2666
Max # of Memory Channels 4
ECC Memory Supported No

Half the memory and no ECC support.

Frankly, I find it difficult to imagine why someone would need a graphics workstation with more than 128 GB RAM (as opposed to offloading the work to a server, or a HPC cluster) So I can't say that ECC is an absolute must...

Took long enough. When I was working at Intel, they were developing a dedicated set-top SOC (Canmore I recall?). The salespeople were all excited and drooling on the meeting table about "a dollar and a dollar"; money from the chip, and money from a cut of ad revenue. The core software came from Yahoo and it was some of the worst code I've ever seen. Ugly inside, undocumented, very broken, and even more ugly outside.

Like all things Intel, much money was burned, flaky dev kits were sent out, and the project killed and the work thrown away.
https://www.intel.com/pressroom/archive/releases/2008/20080820comp_a.htm/

Firstly the EMI envelope within a PC is controlled and far lower than what you compare it to. Short lengths of very low current very low voltage signals at high frequencies radiate but do so poorly.

The PC envelope is specifically designed to be an EMI shield due to EMI generated by the PC. It's an FCC compliance point.

And that is not remotely true. The data lines are twisted to prevent radiation and have been for a long time.

Twisting the data lines causes them to self-shield against near-end cross-talk (for round-trip pairs e.g. Ethernet, they'll have opposing magnetic fields which self-cancel), and also causes LVDS pairs to remain at the same base voltage when acting as antenna (these pairs don't self-shield against NEXT). It doesn't prevent them from radiating outward in an LVDS setup.

and in fact USB 3.0 all things being equal would be less likely to cause external interference than USB 2.0 based on signalling alone.

Oh really?

With the HDD connected, the noise floor in the 2.4 GHz band is raised by nearly 20 dB. This could impact wireless device sensitivity significantly.

With a wireless mouse, performance is fine at 2, 3, and 5 feet. Attach a USB 3.0 hard drive (no writing to it) and the mouse is fine at 2 feet, but lags at 3 feet and 5 feet. Modifying the USB 3.0 connector at the host device itself improves performance of the wireless mouse.

Here's the thing: wifi signals don't cause autism; they just cause other wifi signals to fail. That's true when the signal isn't even a wifi signal, but is in the same band. USB 3.0 emits EMI in that band.

but has anyone actually gotten a root shell prompt to the MINIX layer in their i7?
(No, I'm not asking because I'm concerned about security breaches, I just want to be able to play with it, I'm a nerd not a security expert.)

Pretty close.

https://www.win-raid.com/t596f39-Intel-Management-Engine-Drivers-Firmware-amp-System-Tools.html

An i7 will already come with the management engine (ME) and a partial ATM, enough to gain console bios setup menu access and control the power state.
You can access that by hitting control-P at system post, usually the same time or before you see the message to hit a key for bios setup.

The above link has the BIOS modules to add a full ATM, so you can use VNC to access the computers video buffer and redirect block-devices to boot a remote system.

From that point you can access the web-management app in the ME and access the trusted execution engine.
You can also take control of the secure boot system here, although you don't want to erase the built in microsoft keys if this is a system you ever want to run Windows 8/10 on again.

https://software.intel.com/en-us/articles/getting-started-with-intel-active-management-technology-amt

The above link has the ATM client software you can use after changing the ME keys so you can remotely manage it.

There is also a SDK to write your own ME and ATM modules.
The build of Minix in the ME doesn't include any console or shell support to itself (AKA there is no root shell there to get) however you can make one and install it with the SDK.

You might also find this open source tool helpful:
https://github.com/platomav/MEAnalyzer

It will tell you what ME components you have, what are active, and what you can add in.
Normally the "enterprise" feature modules to ME need purchasing and are installed at the factory before your bulk order of PCs is shipped, but many are "out there" having been extracted and shared.
This will point you at the names to Google for.

Universal drivers are distributed through Windows Update

https://docs.microsoft.com/en-...

Or you could read the fucking article and see that there is a download link on Intel's website.

https://downloadcenter.intel.c...

Oh no Microsoft is doing something, time to shit your pants in terror!

What the article didn't emphasize is that Intel's main market is internal consumption (Intel-branded chips), while companies using the foundry model that TSMC pioneered sell to the industry as a whole. (I note that Intel does have a small, and not successful, attempt at a foundry business.)

Intel must amortize the cost of its IC process development, plus the cost of new fabs every generation, based solely on the revenue it can generate from the sale of its own chips, while TSMC can spread that cost over the manufacture of chips for the entire industry.

As the cost of building a single fab doubles with each process generation, and is now in the $10 billion - $20 billion range, it's fast approaching the point where no single semiconductor company has enough revenue to support such capital expenditures -- Intel included. TSMC has a little more headroom since, as a foundry supplier, the upper bound on its production volumes is the volume of the semiconductor industry as a whole.

Right now, TSMC and Samsung are the only two suppliers of state-of-the-art lithography. It will be interesting to watch the political events that unfold as a result of the discovery by the public that the US no longer has state-of-the-art semiconductor processes. It will be even more interesting to watch what happens when people realize the degree to which the US economy is dependent upon three or four Asian semiconductor fabs.

Processor

1.6GHz dual-core Intel Core i5, Turbo Boost up to 3.6GHz, with 4MB L3 cache

Intel ARK doesn't list such a beast. This is either something like an i5 9200Y or, if the ship date is anytime soon, a custom bitch based off of the i5-8200Y. https://ark.intel.com/products...

Either way, it'll be suuuuuuuuuuuuuuper slow. At least the 4MB cache implies that it has HyperThreading. Intel tends to give you 2 MB of L3 cache per core when HT is enabled, and 1.5 MB of L3 otherwise.

It's probably this one: https://ark.intel.com/products... it's the only 8th generation i3 that runs at 3.6GHz stock.

2920X = $649 i9-9900K = $580

Frankly you'd be nuts to go for the intel chip when you can get 50% more cores AND an upgrade path to 64 cores for around the same price.

Intel Atom® Processor C3958, 16-core, 16-thread (no hyper-threading) low power (full load 47W), fan-less design, with 16MB cache, up to 2.0GHz, can access up to 256GB of RAM, and can be used as a edge-computing device or a dedicated web server.

https://ark.intel.com/products...

Server motherboards from Supermicro, TYAN, or Gigabyte, with CPU attached, for less than $800.

https://b2b.gigabyte.com/Serve...
https://www.tyan.com/Motherboa...
https://www.supermicro.com/pro...

When can AMD offer us something similar?

Any chip that's old by "several years" would have at best pcie2, at roughly half the bandwidth per lane of pcie3.

Nonsense, CPUs with 16x 3.0 lanes were available more than 5 years ago.

https://ark.intel.com/products...

There is no excuse for 16 lanes in 2018.

https://ark.intel.com/products... Was the one I found the specs on so I went with it.

But none of this locked down the PC itself in the way that major consoles are. I7

What do you think windows 10 is you idiot? It's the slow baking of locking in drm, windows 10 + more trusted computing models + encrypted computing is slowly being put into everything.

https://www.intel.com/content/...

These "security technologies" will slowly ebb out from centalized servers into desktops.

. . . computer chips with state-of-the-art lithography soon all will be manufactured overseas. Specifically, they will be made by exactly two companies, Samsung and TSMC, with GlobalFoundries' recent announcement that it is stopping development of its 7nm process. GF operated the old IBM facility in Fishkill, NY, and AFAIK was the last company offering state-of-the-art foundry services with a fab in the US.

Intel is still in business, of course, and even has a foundry business, but it cannot seem to successfully operate it -- substantially all of its wafer starts are chips of its own design. With the capital cost of each new-generation fab reaching $20 billion, it's only a matter of time until Intel -- which has only its internal product base of chip designs to fill its fabs, while Samsung and TSMC make chips for the entire industry -- can no longer afford the move to the next generation.

If the rest of the semiconductor industry (or the US DoD) wants high-performance computer chips, there's now nowhere to go except Samsung and TSMC. It will be interesting to see what politicians do when they realize that the best digital chips can no longer be manufactured in the US. The choice seems to be either (1) have our economy -- everything from cell phones to missiles -- dependent on chips manufactured overseas, or (2) subsidize Intel's foundry business and the semiconductor equipment manufacturers to the tune of tens of $billions, just to keep a US source of high-performance semiconductors.

niittyniemi railed:P

So Intel, as a condition of using your patch to fix the broken shit you sold us, you don't want us to use the patch to empirically determine just how broken your shit was, or else you'll sue us?

I've got the message loud and clear: you're crooked dirtbags.

Mmm ... no.

As another Anonymous Coward pointed out halfway up the page from here, the summary is (surprise!) poorly written. It leaves the reader with the impression that Intel is trying to use its EULA to suppress benchmark reviews of its microcode fixes for the latest set of predictive execution bugs. It's not.

What it IS doing is forbidding developers from sharing benchmark data about its own, proprietary microcode development tools, to whit:

“Development Tools” means the development, evaluation, production, or test tool software, and associated documentation or other collateral, identified in the “development_tools.txt” text files, if any, included in the Materials.

You're perfectly free to publish before-and-after benchmarks of the impact of Intel's current - and previous - microcode fixes on CPU performance to your geeky heart's content. You're simply forbidden from using the tools in Intel's own developer software (which you have to buy from Intel) to obtain the results you publish.

(And, of course, you're forbidden to give, resell, reverse engineer, or share the tools themselves, because they're commercial software, the redistribution terms of which are protected by international copyright law. Nota bene: the topic under discussion here is NOT international copyright law. Therefore, please confine any rants about the evils of copyright to your mother's basement.)

There are ZERO restrictions imposed by the license terms for Intel's own developer tools on the use of third-party test software to establish performance benchmarks and evaluations - and no trace of attempted prior restraint on publishing those results.

Once again, the problem is that The Guardian has conflated Intel-proprietary test software with the microcode fixes themselves, and has invented a scheme by Intel to suppress publication of all benchmarks, including those produced by third-party tools, because Richard Speed, its reporter, misunderstood the EULA about which the Debian people are complaining. And, unfortunately, Bruce failed to catch Speed's mistake before posting this story.

Early in this discussion, he mentions in a comment that he "screws up" as often as anybody else around here - and this is an exemplar of that.

I think Mr. Perens is a real asset to the Slashdot community. His comments are usually thoughtful, informed, and often well-documented. I admire the fact that, when he gets things wrong, unlike many users here, he swiftly and cheerfully admits his errors and disavows them.

Would that more of Slashdot's users had that kind of intellectual honesty ...

(Posting as AC only so as not to undo prior upmods in this thread.)

--

Check out my novel ...

Do you mean this E5-1680 v2, that launched Q3 2013?

"In which universe does a 4 core part have the same TDP as an 8 core part, other things being equal?"

You do die level cherry picking to fit a small volume top bin, the same way you get i7 SKUs with the same core count and TDP but slower clocks.

The old 4 core i7-7920HQ has a core clock of 3.1 GHz and a TDP of 45W: https://ark.intel.com/products...
The new 6 core i9-8950HK has a core clock of 2.9GHz and a TDP of 45W: https://ark.intel.com/products...

"In which universe does a 4 core part have the same TDP as an 8 core part, other things being equal?"

You do die level cherry picking to fit a small volume top bin, the same way you get i7 SKUs with the same core count and TDP but slower clocks.

The old 4 core i7-7920HQ has a core clock of 3.1 GHz and a TDP of 45W: https://ark.intel.com/products...
The new 6 core i9-8950HK has a core clock of 2.9GHz and a TDP of 45W: https://ark.intel.com/products...

The I5 2500K was a 2011 release, not 2010. The Q6600 was 2007, not 2008. Your timelines are vastly different from reality. See the links direct from Intel regarding release dates

https://ark.intel.com/products...
https://ark.intel.com/products...

The I5 2500K was a 2011 release, not 2010. The Q6600 was 2007, not 2008. Your timelines are vastly different from reality. See the links direct from Intel regarding release dates

https://ark.intel.com/products...
https://ark.intel.com/products...

Hyper-threading (HT) is Intel's proprietary implementation of Simultaneous Multithreading (SMT), a technology that allows processors to run parallel operations on different cores of the same multi-core CPU.

Um nope.

If you bothered to follow the link to Hyper-threading (HT) it says:

Intel® Hyper-Threading Technology (Intel® HT Technology) uses processor resources more efficiently, enabling multiple threads to run on each core

That's parallel operations per-core not parallel operations on different cores. One is HT, the other is SMT.
Different things.

Where's the tablet-optimised website? This one's just a few tweets, it doesn't even have a logo! Where's the superbowl ad?

And yeah, msmash, you really should have added links like this one; just some barely-not-bleepingcomputer website is not enough. You should have picked up on this by now.

Intel: https://newsroom.intel.com/edi...
"the first Intel processor with a 5.0 GHz turbo frequency"

Intel actually qualifies their statement and all the reporters parroted it without the qualification. So basically, just another news day.

Venturebeat: https://venturebeat.com/2018/0...
"the first-ever CPU with a 5.0GHz turbo frequency, said Intel’s Gregory Bryant"

CNET: https://www.cnet.com/news/inte...
"the first-ever CPU with a 5.0GHz turbo frequency." ...

Generally speaking, you're going to need to trigger some kind of pre-BIOS/UEFI failure to get anything out of it, and even that seems to be dying out as my last few mobos have all had a pair of seven-segment LED displays that show a sequence of hex status codes as the system progresses through the boot process.

LED display on the MB is civilized, but most don't have it and blink some LED instead, which nearly all new MBs have and is getting universal. Even NUCs do this. Way more useful imho. I never did like the lame little beep on boot, can't shed a tear for its demise.

What does Intel think about using a similar name to their Core X-series processor range?
https://www.intel.com/content/...

I use a cheap Pentium motherboard (also low power),

This sounds suspicious to me. Define cheap, Pentium, and low power.

Well there is the current generation Pentium G5500T, 2 cores, 3.2 GHz, $85, 35W, ... ?
https://www.intel.com/content/...

Or the previous generation Pentium G4400, 2 core, 3.3 Ghz, $45, 54W, ...?
https://www.intel.com/content/...

There is a G4400T at 2.9 Ghz and 35W but I don't know if its still available.

I use a cheap Pentium motherboard (also low power),

This sounds suspicious to me. Define cheap, Pentium, and low power.

Well there is the current generation Pentium G5500T, 2 cores, 3.2 GHz, $85, 35W, ... ?
https://www.intel.com/content/...

Or the previous generation Pentium G4400, 2 core, 3.3 Ghz, $45, 54W, ...?
https://www.intel.com/content/...

There is a G4400T at 2.9 Ghz and 35W but I don't know if its still available.

I use a cheap Pentium motherboard (also low power)

The first Pentiums were nicknamed "Coffee Warmers" for good reason.

You realize Intel still makes "Pentiums"? Not really anything like the original, but this is probably what the GP is referring to. 25-35W.
https://www.intel.com/content/...

Most likely by mistake last Sunday Intel released Z390 chipset information. The page has since been pulled down because this chipset was rumored to be accompanied with octa-core Coffee Lake CPUs which are yet to be announced.

Next time I'm gonna web-archive their mistakes ;-)

The documentation can be found here on page 2876 of this PDF file

https://software.intel.com/sit...

"6-8 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
If an interrupt or exception occurs after the new SS segment descriptor has been loaded but before the ESP register
has been loaded, these two parts of the logical address into the stack space are inconsistent for the duration of the
interrupt or exception handler (assuming that delivery of the interrupt or exception does not itself load a new stack
pointer).
To account for this situation, the processor prevents certain events from being delivered after execution of a MOV
to SS instruction or a POP to SS instruction. The following items provide details:
  Any instruction breakpoint on the next instruction is suppressed (as if EFLAGS.RF were 1).
  Any data breakpoint on the MOV to SS instruction or POP to SS instruction is inhibited until the instruction
boundary following the next instruction.
  Any single-step trap that would be delivered following the MOV to SS instruction or POP to SS instruction
(because EFLAGS.TF is 1) is suppressed.
  The suppression and inhibition ends after delivery of an exception or the execution of the next instruction.
  If a sequence of consecutive instructions each loads the SS register (using MOV or POP), only the first is
guaranteed to inhibit or suppress events in this way. Intel recommends that software use the LSS instruction to
  load the SS register and ESP together. The problem identified earlier does not apply to LSS, and the LSS
instruction does not inhibit events as detailed above"

Why document the MOV SS and POP SS instructions first, when the safer option is the LSS instruction.

This seems to be the problem with technology these days. We are offered a dozen different ways of doing things in C++
or assembly language, but only one way is the fastest.

https://hardware.slashdot.org/...

"There's a "z390" (?) is a cannonlake chipset or "PCH" - and it's coming out next year - but that chipset is only for cannonlake processors, except there are (apparently) none of those planned for desktop."

No sign of this chipset, no sign of an 8 core processor.
Note this: https://www.intel.com/content/...

The new chipsets do include the rumoured 'free' "Intel® Wireless-AC MAC"
As well as a newer USB revision, 3.1 vs 3.0

So what you end up with is the 'premium' z370 chipset, now a 'gimped' product, lacking several of the new features (I'd also heard Bluetooth 5 on the H370 also?)

A real mess Intel has got itself into with product launch delays, push forwards, branding changes, just totally sloppy. One would normally assume you get the be-all and end all solution at the top end, sadly not the case.
(I will say the 6 core CPUs from late last year are a good move forward, if you're wanting to hang on though, in another 12 months we might see 8 core with that free Wifi AC and USB 3.1 support)

Oh and when is 2.5 and 5 GBit going to become common? I could really do with this soon. Knowing Intel? Not for a while.

https://en.wikipedia.org/wiki/...
A table like the above, will explain the breakdown of the numbering. It hasn't changed much with each generation since the core series lineup came in 10 years ago.
Here is a better breakdown with more words than numbers. https://www.intel.com/content/...

But perhaps youre a casual and that's all a bit too esoteric for you?

If you want to easy it up, just go to www.cpubenchmark.net and you can easily compare all cpus and pricepoints. Look at single thread performance if that's all your application can handle (or you are a gamer..), and total performance if its multithreaded. There is a wealth of user submitted data there that i would never view processor advertisements without.

Its really not something you need to spend more than an afternoon getting acquainted with. An exercise that anyone who wants to spend $500+ on a new PC should be more than willing to do. As others have said, basic research is important when buying most things.

Aside from the fact that you can't clearly define any simple set of tasks as being indicative of "real world performance", you also can't dictate to manufacturers what they call their products. As soon as you come up with a suite of tests that is your "real world" benchmark, then you can guarantee that manufacturers will optimise their designs specifically for the suite of tests you're running and game the benchmarks.

Re: the numbers, this would be like telling Audi that they can't sell a car called an RS3 that is faster than an A4 because the number at the end is smaller. But what defines better for "real world" use in an automobile? Some people would say that a bigger car is more useful because you can fit more stuff in it. In this case, the A4 would be better than the RS3. Some people say a smaller car is better as it's more manoeuvrable and easier to park. Some would say a faster car is better. Some would say a cheaper car is better. Some would say a more fuel efficient car is better. Some would say a larger engine is better. Who is right and who is wrong?

What does the number at the end mean? It's simply a model identifier, a family name. Intel follow a fairly strict naming convention for the model names, they're not simply plucked from thin air (well, in part they may be, but that's a minor part of the name).
https://www.intel.com.au/conte...
https://www.intel.com/content/...

Tracing Rays Through the Cloud is a pretty good example of what was "next-gen" 6 years ago. None of the imagery there was generated real-time (just read the paper), but was still a good read about what goes into ray tracing. Intuitively we know what it is, but what it means for computation with reflective/refractive surfaces is a ton of work.

Of course, I won't believe it's real-time until it can render a house of mirrors at 60fps+.

I smell a conspiracy. You know who else is based in Israel? THE JEWS!!! No, just kidding. But seriously folks, who know who there's a lot of in Israel? Jews, that's who. No, no no, actually there's a lot of Intel employees and facilities in Israel. Intel is desperate for anything that makes them look good right now, and the next best thing is anything that makes the competition look bad. There may be Jews involved, but I suspect what's most relevant is that if there are, they're connected to Intel somehow. Nobody ever heard of CTS Labs before now...

Well

https://downloadcenter.intel.c...

finds only ancient, 2017 microcode version :-(

The structure alignment rules for anything that's not a packed structure are likely to be the same for both

I found this for Android - long long is aligned to 8 bytes on ARM but 4 bytes on x86

https://software.intel.com/en-...

Microsoft compilers have an option to align. It seems like /Zp8 is the default

https://msdn.microsoft.com/en-...

What that means is that anything up to 8 bytes will be naturally aligned

And if you look here it confirms it

https://msdn.microsoft.com/en-...

I still think there'd be some corner case where the layout in memory of a structure would be different. Bitfields for example, though Windows usually doesn't use those because of portability concerns. Or SIMD data.

Another issue is that x86 and x64 are strongly ordered and ARM is not. You have to add in explicit barriers to for ARM to work the same. ARM I&D caches are not coherent too - self modifying code works on x86 because writes to the D cache automagically end up in the I cache. That's not true in ARM. x86 goes to great lengths in hardware so that code now sees the same machine that code back in the 386 days did and one which is very different from both a moder x86/x64 chip and any Risc chip. Modern x86/x64 chips have extra hardware to maintain the illusion and Riscs like ARM do not.

Intel have a handy graph of when each SIMD instruction set was patented here

https://newsroom.intel.com/edi...

MMX is 1996
SSE is 1999
SSE2 is 2001
SSE3 is 2004

and so on

The original x64 specification made support for SSE and SSE2 mandatory, but of course some applications might require later versions.

It's pretty clear that Intel are saying that if you write an emulator to run patented SIMD instructions on non Intel hardware and don't have a patent license, they may sue.

x64 is a nice pragmatically designed extension to x86 but it is almost covered by patents from both Intel and AMD.

You can't patent or copyright an ISA. Most of their patents would cover hardware implementations of various features.

Intel claim patents on SIMD instruction sets and say that those preclude anyone who doesn't have a license executing those instructions even in emulator

https://newsroom.intel.com/edi...

Intel carefully protects its x86 innovations, and we do not widely license others to use them. Over the past 30 years, Intel has vigilantly enforced its intellectual property rights against infringement by third-party microprocessors. One of the earliest examples, was Intel's enforcement of its seminal "Crawford '338 Patent." In the early days of our microprocessor business, Intel needed to enforce its patent rights against various companies including United Microelectronics Corporation, Advanced Micro Devices, Cyrix Corporation, Chips and Technologies, Via Technologies, and, most recently, Transmeta Corporation. Enforcement actions have been unnecessary in recent years because other companies have respected Intel's intellectual property rights.

However, there have been reports that some companies may try to emulate Intel's proprietary x86 ISA without Intel's authorization. Emulation is not a new technology, and Transmeta was notably the last company to claim to have produced a compatible x86 processor using emulation ("code morphing") techniques. Intel enforced patents relating to SIMD instruction set enhancements against Transmeta's x86 implementation even though it used emulation. In any event, Transmeta was not commercially successful, and it exited the microprocessor business 10 years ago.

Only time will tell if new attempts to emulate Intel's x86 ISA will meet a different fate. Intel welcomes lawful competition, and we are confident that Intel's microprocessors, which have been specifically optimized to implement Intel's x86 ISA for almost four decades, will deliver amazing experiences, consistency across applications, and a full breadth of consumer offerings, full manageability and IT integration for the enterprise. However, we do not welcome unlawful infringement of our patents, and we fully expect other companies to continue to respect Intel's intellectual property rights. Strong intellectual property protections make it possible for Intel to continue to invest the enormous resources required to advance Intel's dynamic x86 ISA, and Intel will maintain its vigilance to protect its innovations and investments.

The graph above shows that SSE and later is still covered by extant patents. SSE is actually part of the x64 architecture - you need to execute SSE instructions to have floating point, and floating point is not optional. The x64 ABI actually requires SSE. I.e. to emulate x64 instructions you need a licence for the SSE patents.

This probably also means that if an emulator supports SSE instructions in x86 mode Intel will sue too.

Of course they might be bluffing about suing and will come to an arrangement with Microsoft and Qualcomm or the hardware vendors of Windows on ARM devices to license the patents. Or maybe they're not but they'd lose in court.

Their blog post is clearly designed to make Microsoft, Qualcomm and the vendors think that a lawsuit is possible though.

I would be surprised if X64 support ever sees the light of day. I'm sure both Intel and AMD have many patents that make implementation of X64 emulators impossible without running afowl and infringing. AMD might be willing to license to MSFT but given Intel's post, Intel is definitely not and is ready to sue. They are lucky that the 386 and older are not patented, that the only reason 32 bit support is possible. The patents start at MMX.

https://www.intel.com/content/...

If they're making expensive laptops to play games, are Linux users their intended market?

Also referencing "Meltdown and Spectre" is a bit bogus. Intel CPUs have a firmware update facility but that's already supported.

https://downloadcenter.intel.c...

And the kernel already does KPTI.

Sure they could assign someone to do LVFS contributions to do firmware updates for their USB devices, but I guess their priorities are elsewhere. It's not at all clear that significant numbers of people are not buying Razer USB devices because you can't update the firmware on Linux. I'm guessing some support engineer got the request, escalated it up to management and management said "No".

It's worth pointing out that when the CEO made his comments, the response here was less than enthusiastic

https://hardware.slashdot.org/...

These machines have Apollo Lake Celeron processors

https://ark.intel.com/products...

They're Goldmont cores - the descendent of Atom - though they've dropped the Atom branding. Still they're very much descendants of the chips that powered the original netbooks.

https://www.anandtech.com/show...

The Lenovo machine has a 11.6" 1366 x 768 display rather than the netbook standard of 10.1" 1024*600, but that's probably the minimum viable display.

Apparently it's got a N3450, which Anandtech points out is a 4 core, 4 thread out of order chip clocked at 1.1 to 2.2 Ghz. I.e. it's a bit quicker than the old dual core, in order N570 in my old Asus 1015PX which I stopped using because Chrome run like a dog. You can also get 4GB of Ram compared with 2GB mac on the 1015PX and 128GB of eMMC storage compared to a 160GB 5400rpm ultra low cost and sluggish hard drive.

https://hothardware.com/news/l...

Sitting at the bottom of the stack is the Lenovo 100e. There are two versions, one with Windows and the other a Chromebook. The Windows version sports "up to" an 11.6-inch display with a 1366x768 resolution powered by an Intel Celeron N3450 Apollo Lake processor and up to 4GB of LPDDR4 RAM. It also has up to 128GB of eMMC storage, a reversible HD camera, spill-proof keyboard, and a 45Wh batter that's good for up to 10 hours of battery life.

Windows 10 S can be upgraded to full Windows 10 too. But I'm guessing for an educational environment they want something which is locked down so the little shits can't install malware on it. Then again you could always reimage the machines when they go fubar.

I buy Xeons for workstation loads and high reliability requirements. I am able to disable prefetching/problematic speculation through the BIOS (similar to this), thanks to the extensive functionality that seems to be on motherboard (I've noticed Xeon boards generally have a lot more options generally).

What is AMD's alternative? In the past it was branded Opteron, but I am struggling to find a modern variant that's comparable to Intel's top end Xeons along with the ability to disable prefetching.

red hat didn't cause this bug, they are just an OS. why can't intel put the microcode file up for download on their website? Oh wait they did

As written in the summary, the CPU maker is the only entity who can create a fixed microcode, be it for inclusion into firmware (BIOS/UEFI) files or in Linux kernel microcode files. So asking the OEM vendors won't help one bit cause they can simply do nothing at all except use a file create by Intel. If RH is too small to force Intel to create working microcode without boot up bugs, then others aren't big enough either.

Then next thing is: what will RH do in the future? Never apply the Spectre microcodes due to instability? If so, what happens in the future when other microcode updates are needed, like before? Intel has afaik only a single microcode file for Linux for pretty much all CPUs together. There is no mix and match, no way for Linux to selectively choose what to load. That is why RH had to go back to an older version without the breakage for Spectre. they couldn't just disable the new buggy part of the microcode.
This file you can see and download here: https://downloadcenter.intel.c...
Normally it lives in your initrd.
Sooner or later RH has to include a current microcode file from Intel in RHEL again. Would have been nice if they had clearly communicated this to their customers. Not "wash their hands" but "we will continually work with Intel until this issue is resolved."

Know how I know you didn't read the article? Here is the table published by Intel, from Intel's website, that covers all the benchmarks they felt like making public. Look at the one that covers "responsiveness." That covers very basic tasks that all desktop users will be familiar with, and will experience dozens or hundreds of times per day.

It's not just about how fast your code compiles; it's also about sluggishness in drawing windows, multitasking, and spinning up new processes, all of which can steal a few seconds here and there, eventually coming out to minutes or hours lost over arbitrary usage periods. A 20% drop in "responsiveness" is a big fucking deal, regardless of whether you or Intel want to admit it.